Value Added Course on

VD18703 - Hardware Modeling and Analysis using EDA Tool

April 3rd , 5th , 6th and 10th 2023
Time Table
Day/ Date/ Faculty Topic
Session/ Time/
No.of Hrs
Day-1 Dr.S.R.Malathi UNIT-I Hierarchical Modeling Concepts
3-4-2023, FN Session Mr.M.Athappan Overview of Digital Design with Verilog HDL, Evolution of
8.30 AM – 10.10 AM Computer Aided Digital Design, Emergence of HDLs, Typical Design
10.25 AM - 12.05 PM Flow, Importance of HDLs, Popularity of Verilog HDL, Trends in
4 Hrs HDLs, Design Methodologies-Example: 4-bit Ripple Carry Counter,
Modules, Instances, Components of a Simulation, Design Block,
Stimulus Block, Example- Ripple Carry Counter,
Day-1 Ms.R.Kousalya UNIT-I Hierarchical Modeling Concepts (continued....)
3-4-2023, AN Session Ms.B.Sarala Basic Concepts, Lexical Conventions, Data Types, System Tasks and
12.45 PM – 2.25 PM Compiler Directives
2 Hrs
Day-1 Ms.R.Kousalya UNIT-II Components of Verilog Module and Gate-Level Modeling:
3-4-2023, AN Session Ms.B.Sarala Modules and Ports, Modules- Components of Verilog Module,
2.25 PM – 3.15 PM Example: S-R Latch, Ports- List of ports – Port Declaration
3.30 PM - 4.15 PM
2 Hrs
Day-2 Ms.R.Kousalya UNIT-II Components of Verilog Module and Gate-Level Modeling:
5-4-2023, FN Session Ms.B.Sarala (continued.....)
8.30 AM – 10.10 AM Port Connection Rules- Connecting Ports to External Signals, Gate-
10.25 AM - 12.05 PM Level Modeling - Gate Types- AND/OR Gates, BUF/NOT Gates,
4 Hrs Array of instances, Examples: Gate-level multiplexer, 4- bit ripple
carry full adder, Gate Delays- Rise, Fall, and Turn-off Delays,
Min/Typ/Max Values, Delay Example;

Day-2 Ms.R.Kousalya UNIT-III Dataflow and Behavioral Modeling

5-4-2023, AN Session Ms.B.Sarala Dataflow Modeling - Continuous Assignments, Delays, Expressions,
12.45 PM – 2.25 PM Operators, and Operands, Operator Types
2 Hrs
Day-2 Ms.R.Kousalya UNIT-III Dataflow and Behavioral Modeling: (continued.....)
5-4-2023, AN Session Ms.B.Sarala Examples: 4-to-1 Multiplexer, 4-bit Full Adder, Ripple Counter;
2.25 PM – 3.15 PM Behavioral Modeling, Structured Procedures, Procedural
3.30 PM - 4.15 PM Assignments, Conditional Statements,
2 Hrs
Day-3 Mrs. S.M. Abinaya UNIT-III Dataflow and Behavioral Modeling: (continued.....)
6-4-2023, FN Session Mr. D. Silambarasan Multiway Branching, Loops, Sequential and Parallel Blocks,
8.30 AM – 10.10 AM Examples: 4-to-1 Multiplexer, 4-bit Counter, Traffic Signal
2 Hrs Controller –FSM design
Day-3 Mrs. S.M. Abinaya UNIT-IV Switch-Level Modeling and User-Defined Primitives:
6-4-2023, FN Session Mr. D. Silambarasan Switch-Level Modeling, Switch-Modeling Elements- MOS switches,
10.25 AM - 12.05 PM CMOS switches, Bi-directional switches, Power and Ground,
2 Hrs Resistive Switches, Delay Specification on Switches,

1 of 2
 Value Added Course on
VD18703 - Hardware Modeling and Analysis using EDA Tool
April 3rd , 5th , 6th and 10th 2023
Time Table
Day-3 Mrs. S.M. Abinaya UNIT-IV Switch-Level Modeling and User-Defined Primitives:
6-4-2023, AN Session Mr. D. Silambarasan (continued.....)
12.45 PM – 3.15 PM Examples: CMOS Nor Gate, 2-to-1 Multiplexer, CMOS Inverter,
3.30 PM - 4.15 PM Hands-on with FPGA; User-Defined Primitives - UDP basics,
4 Hrs Combinational UDPs, Sequential UDPs, UDP Table Shorthand
Symbols
Day-4 Dr.S.R.Malathi UNIT V - Hands-on with CADENCE software Tool
10-4-2023, FN Session Mr.M.Athappan Design, Functional verification and Synthesis of ALU or any given
8.30 AM – 10.10 AM Mrs. S.M. Abinaya subsystems using CADENCE tool and analyzing the same for Area,
10.25 AM - 12.05 PM Mr. D. Silambarasan Power and Delay
4 Hrs
Day-4 Dr.S.R.Malathi UNIT V - Hands-on with CADENCE software Tool: (continued.....)
10-4-2023, AN Session Mr.M.Athappan Design, Functional verification and Synthesis of ALU or any given
12.45 PM – 2.25 PM subsystems using CADENCE tool and analyzing the same for Area,
2 Hrs Power and Delay

Day-4 Mr.K.Ragupathi
10-4-2023, AN Session Ms.Mehzabeen
2.25 PM – 3.15 PM TEST + FEEDBACK
3.30 PM - 4.15 PM
2 Hrs
4 Days x 8 Hours per day (8.30 AM to 4.15 PM) = 32 Hours

2 of 2