Puneeth Perika, M.

Tech

A.S Rao Nagar, ECIL, Hyderabad, Telangana, 500062 ·

Mail ID ·puneethperika@outlook.com
Mobile ·+91 709 3757 047
· ·

Summary
• To obtain a creative and challenging position in an organization that gives me an opportunity to utilize my technical
and organizational skills for self-improvement while contributing to the symbolic growth of the organization.

EDUCATION
• Master of Technology (2021-2023)
National Institute of Technology, Raipur
CGPA: 9.3

• Bachelor of Technology (2014-2018)

VNR Vignana Jyothi Institute of Engineering Technology, Hyderabad
CGPA: 6.3

• Intermediate (2012-2014)
Pragna Junior College, Karimnagar.
Percentage: 84

• SSC (2012)
St. Anthony’s High School,Hyderabad
CGPA: 6.7

PUBLICATIONS
• Design Implementation of High-Frequency 16-bit full adder on FPGA Families. (accepted in
IEEE INCET 2023)

PROJECTS

• Implementation of Pipelining Technique on ALU using Verilog.

• Gate Level Design Techniques for Low Power.

• Comparative analysis of Parallel Prefix Adder performance.

TECHNICAL SKILLS
• Verilog HDL, System Verilog, Digital IC Design, System Verilog Assertions, Static Timing
Analysis, Clock Domain Crossing, SPI Protocol, I2C Protocol, UART Protocol