Steps to execute from login to Ximng graphical interfacing command

login as: tmc-fe09

tmc-fe09@192.168.0.10's password:
Last login: Tue Mar 29 11:18:15 2022 from 192.168.0.1
[tmc-fe09@kailash ~]$ csh
[tmc-fe09@kailash ~]$ cd t
tmc-fe09-Shriniket/ tmc-fe09-Suresh_Kumar/
[tmc-fe09@kailash ~]$ cd tmc-fe09-Shriniket/
[tmc-fe09@kailash ~/tmc-fe09-Shriniket]$ cd Synopsys_examples/basic-hdl/verilog/
syn_fifo/
[tmc-fe09@kailash syn_fifo]$ ls
comp.log DVEfiles fifo.v README simv.daidir ucli.key
csrc fifo.dump Makefile simv tb_fifo.v vcdplus.vpd
[tmc-fe09@kailash syn_fifo]$ make
\rm -rf simv* csrc* *.log
vcs fifo.v tb_fifo.v +v2k -debug_access+pp+f -l comp.log
Chronologic VCS (TM)
Version R-2020.12 -- Tue Mar 29 11:19:47 2022
Copyright (c) 1991-2020 by Synopsys Inc.
ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.

and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.

Parsing design file 'fifo.v'

Parsing design file 'tb_fifo.v'
Top Level Modules:
tb_fifo
No TimeScale specified
Starting vcs inline pass...

1 module and 0 UDP read.

recompiling module tb_fifo
make[1]: Entering directory `/home/tmc-fe09/tmc-fe09-Shriniket/Synopsys_examples
/basic-hdl/verilog/syn_fifo/csrc'
make[1]: Leaving directory `/home/tmc-fe09/tmc-fe09-Shriniket/Synopsys_examples/
basic-hdl/verilog/syn_fifo/csrc'
make[1]: Entering directory `/home/tmc-fe09/tmc-fe09-Shriniket/Synopsys_examples
/basic-hdl/verilog/syn_fifo/csrc'
rm -f _cuarc*.so _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so
if [ -x ../simv ]; then chmod a-x ../simv; fi
g++ -o ../simv -m32 -m32 -rdynamic -Wl,-rpath='$ORIGIN'/simv.daidir -Wl,-
rpath=./simv.daidir -Wl,-rpath=/tools/synopsys/installers/vcs/linux/lib -L/tools
/synopsys/installers/vcs/linux/lib -Wl,-rpath-link=./ objs/amcQw_d.o _23652
_archive_1.so SIM_l.o rmapats_mop.o rmapats.o rmar.o rmar_nd.o rmar_llvm
_0_1.o rmar_llvm_0_0.o -lvirsim -lerrorinf -lsnpsmalloc -lvfs -lvcs
new -lsimprofile -luclinative /tools/synopsys/installers/vcs/linux/lib/vcs_tls.o
-Wl,-whole-archive -lvcsucli -Wl,-no-whole-archive _vcs_pli_stub_.
o /tools/synopsys/installers/vcs/linux/lib/vcs_save_restore_new.o /tools/synop
sys/installers/verdi/share/PLI/VCS/LINUX/pli.a /tools/synopsys/installers/vcs/li
nux/lib/ctype-stubs_32.a -ldl -lc -lm -lpthread -ldl
../simv up to date
make[1]: Leaving directory `/home/tmc-fe09/tmc-fe09-Shriniket/Synopsys_examples/
basic-hdl/verilog/syn_fifo/csrc'
CPU time: .397 seconds to compile + .531 seconds to elab + .389 seconds to link
simv -l run.log
make: execvp: simv: Permission denied
make: *** [run] Error 127
[tmc-fe09@kailash syn_fifo]$ ./simv
Chronologic VCS simulator copyright 1991-2020
Contains Synopsys proprietary information.
Compiler version R-2020.12; Runtime version R-2020.12; Mar 29 11:19 2022
********* FIFO : Underflow = 0, Overflow = 0 **********

************ WRITING INTO FIFO *************

FIFO WRITE: Data = 16, Address = 0

FIFO WRITE: Data = 15, Address = 1

FIFO WRITE: Data = 14, Address = 2

FIFO WRITE: Data = 13, Address = 3

FIFO WRITE: Data = 12, Address = 4

FIFO WRITE: Data = 11, Address = 5

FIFO WRITE: Data = 10, Address = 6

FIFO WRITE: Data = 9, Address = 7

FIFO WRITE: Data = 8, Address = 8

FIFO WRITE: Data = 7, Address = 9

FIFO WRITE: Data = 6, Address = 10

FIFO WRITE: Data = 5, Address = 11

FIFO WRITE: Data = 4, Address = 12

FIFO WRITE: Data = 3, Address = 13

FIFO WRITE: Data = 2, Address = 14

FIFO WRITE: Data = 1, Address = 15

FIFO WRITE: Data = 1, Address = 0

WRITE ERROR: FIFO IS FULL

********* FIFO : Underflow = 0, Overflow = 1 **********

FIFO WRITE: Data = 1, Address = 0

WRITE ERROR: FIFO IS FULL

************ READING FIFO *************

FIFO READ: Address = 0,

********* FIFO : Underflow = 0, Overflow = 0 **********
FIFO READ: Data = 16

FIFO READ: Address = 1,

FIFO READ: Data = 15

FIFO READ: Address = 2,

FIFO READ: Data = 14

FIFO READ: Address = 3,

FIFO READ: Data = 13

FIFO READ: Address = 4,

FIFO READ: Data = 12

FIFO READ: Address = 5,

FIFO READ: Data = 11

FIFO READ: Address = 6,

FIFO READ: Data = 10

FIFO READ: Address = 7,

FIFO READ: Data = 9

FIFO READ: Address = 8,

FIFO READ: Data = 8

FIFO READ: Address = 9,

FIFO READ: Data = 7

FIFO READ: Address = 10,

FIFO READ: Data = 6

FIFO READ: Address = 11,

FIFO READ: Data = 5

FIFO READ: Address = 12,

FIFO READ: Data = 4

FIFO READ: Address = 13,

FIFO READ: Data = 3

FIFO READ: Address = 14,

FIFO READ: Data = 2

FIFO READ: Address = 15,

FIFO READ: Data = 1

FIFO READ: Address = 0,

READ ERROR: FIFO IS EMPTY

********* FIFO : Underflow = 1, Overflow = 0 **********

FIFO READ: Data = 1

FIFO READ: Address = 0,

READ ERROR: FIFO IS EMPTY

FIFO READ: Data = 1

FIFO WRITE: Data = 0, Address = 0

********* FIFO : Underflow = 0, Overflow = 0 **********
FIFO WRITE: Data = 1, Address = 1

FIFO READ: Address = 0,

FIFO READ: Data = 0

FIFO READ: Address = 1,

FIFO READ: Data = 1

FIFO WRITE: Data = 2, Address = 2

FIFO WRITE: Data = 3, Address = 3

FIFO WRITE: Data = 8, Address = 4

FIFO READ: Address = 2,

FIFO READ: Data = 2

$finish called from file "tb_fifo.v", line 116.

$finish at simulation time 955
V C S S i m u l a t i o n R e p o r t
Time: 955
CPU Time: 0.720 seconds; Data structure size: 0.0Mb
Tue Mar 29 11:19:55 2022
[tmc-fe09@kailash syn_fifo]$ vcs fi
fifo.dump fifo.v*
[tmc-fe09@kailash syn_fifo]$ vcs fifo.v tb_fifo.v
Chronologic VCS (TM)
Version R-2020.12 -- Tue Mar 29 11:20:06 2022
Copyright (c) 1991-2020 by Synopsys Inc.
ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.

and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.

Parsing design file 'fifo.v'

Parsing design file 'tb_fifo.v'
Top Level Modules:
tb_fifo
No TimeScale specified
Starting vcs inline pass...

1 module and 0 UDP read.

recompiling module tb_fifo
rm -f _cuarc*.so _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so
if [ -x ../simv ]; then chmod a-x ../simv; fi
g++ -o ../simv -m32 -m32 -rdynamic -Wl,-rpath='$ORIGIN'/simv.daidir -Wl,-
rpath=./simv.daidir -Wl,-rpath=/tools/synopsys/installers/vcs/linux/lib -L/tools
/synopsys/installers/vcs/linux/lib -Wl,-rpath-link=./ objs/amcQw_d.o _24096
_archive_1.so SIM_l.o rmapats_mop.o rmapats.o rmar.o rmar_nd.o rmar_llvm
_0_1.o rmar_llvm_0_0.o -lvirsim -lerrorinf -lsnpsmalloc -lvfs -lvcs
new -lsimprofile -luclinative /tools/synopsys/installers/vcs/linux/lib/vcs_tls.o
-Wl,-whole-archive -lvcsucli -Wl,-no-whole-archive _vcs_pli_stub_.
o /tools/synopsys/installers/vcs/linux/lib/vcs_save_restore_new.o /tools/synop
sys/installers/vcs/linux/lib/ctype-stubs_32.a -ldl -lc -lm -lpthread -ldl
../simv up to date
CPU time: .329 seconds to compile + .384 seconds to elab + .314 seconds to link
[tmc-fe09@kailash syn_fifo]$ dve &
[1] 24264
[tmc-fe09@kailash syn_fifo]$ PuTTY X11 proxy: unable to connect to forwarded X s
erver: Network error: Connection refused

Error-[DVAP021] DVE
Cannot connect to X server.
Please check your DISPLAY setting.

[1] Exit 1 dve

[tmc-fe09@kailash syn_fifo]$
[tmc-fe09@kailash syn_fifo]$ dve &
[1] 24504