Design For Testability

Introduction
Usha Gogineni
31st July 2023
Course Details

Instructor: Usha Gogineni (Guest Faculty) Tentative Grading Policy

Email: usha.gogineni@iiit.ac.in
Assignments 15%
TA: Quizzes 20%
Mid term Exam 20%
End sem Exam 20%
Pre-requisites Final Project 25%
VLSI Design Flow
Combinational and sequential circuits
Familiarity with Verilog or VHDL

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Recommended Books

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Agenda

 VLSI Design Flow

 VLSI Testing
 Testing vs Verification or Validation
 Importance of Testing
 Challenges in Testing
 Design for Testability
 Course Map

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VLSI Design Flow

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VLSI Design Flow

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Semiconductor Manufacturing

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Chip Fabrication

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What is Testing?
Testing is the process of determining whether a piece of hardware is either
a. Functioning correctly per specification (PASS)
b. Defective (FAIL)

Output compared to
a stored response

Why test?
Defects occur in the Manufacturing Process
Break in Metal

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Test Outcomes

Test Escapes = defective chips that pass test

Yield Loss = good chips that fail test

Goal of testing: Reduce test escapes and yield loss.

Trade-off between test cost and test quality.

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Verification, Validation, and Testing

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Verification vs Testing

Verification Test
Verifies correctness of design Verifies correctness of manufactured
hardware

Performed by simulation, formal methods Two-part process:

1.Test generation: software process executed
once during design
2. Test application: electrical tests applied to
hardware

Performed once prior to manufacturing Test application performed on every

manufactured device

Responsible for quality of design Responsible for quality of devices

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Verification, Validation, and Testing

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Levels of Testing

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Rule of Ten

Cost of Testing increases by a factor of 10 in going from one

level to the next higher level of testing! $0.01

$0.1
Detect Faults as soon as possible!
$1

$10

$100

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 Role of Testing

 Characterization: Determination and

correction of errors in design and/or
test procedure.
 Detection: Determination of whether
or not the device under test (DUT)
has some fault.
 Diagnosis: Identification of a specific
fault that is present in the DUT.
 Failure Analysis: Determination of
manufacturing process errors that
may have caused defects on the DUT.

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Challenges in Testing – Design Complexity

 Moores Law: Number of Transistors on a chip

double every 18 months!
 Over a billion transistors on modern chips!
 Enabled by feature size reduction.
 Reduced feature size increases the probability
of manufacturing defects.
 Growing size and complexity of chips
 Many new testing challenges!!

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Challenges in Testing – Test Time

Consider a combinational circuit block with 64 inputs and 64

outputs and 10ns internal delay.
We are testing this block with a tester running at 1GHz clock
frequency.
Assume 2ns for test vector application and 2ns for comparing
output with expected result.
Total test time = 264 * (10+2+2) ns = 8189 years !!!!

Test time gets even longer if we consider sequential circuits where all internal states of the system
need to be considered!

Need to explore alternate test methods to thoroughly test the block in a very short time!
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How to reduce test time?

 Simplify defects that can occur

 Reduce the number of faults

 Find mechanisms for evaluating test vectors

 Identify parts of the circuit that are harder to test

 Generate tests that target hard to test areas

 Evaluate test vectors and keep more efficient ones

 Compact test vectors

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Simplify Defects

Testing detects manufacturing defects.

Difficult to quantify the many defects and predict their effect on
circuit performance.
Fault: Representation of a defect at an abstracted logic level
Eg: Defect: Gate shorted to source.
Fault Model: Gate stuck at 0.

Fault models simplify circuit analysis and enable test automation

 Fault Reduction reduces test time
 Fault Simulation estimates Fault Coverage
 Automatic Test Pattern Generation

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Target Hard to Test Areas

 Hard to test areas in a circuit are identified using two components:

 Controllability: degree of difficulty to control a logic signal to 0 or 1
 Observability: degree of difficulty to observe the logic value of a signal

 Combinational circuits have high testability

 Sequential Circuits have low testability

 Testability analysis helps identify

 areas that are hard to test

 most efficient test vectors

 ways to improve testability and reduce test time

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Design for Testability

 Design for testability involves adding additional hardware to a CUT to make its testing easier,
faster, and more effective in terms of fault coverage.
 Add control and observation points within the circuit
 Scan chains: Convert sequential circuits to combinational circuits
 Built-in Self Test (BIST)

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VLSI Design Flow including DFT

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Course Map

 Types of test and ATE

 Fault Modeling
 Fault Simulation
 Automatic Test Pattern Generation (ATPG)
 Design for Testability
 Testability measures
 Scan Insertion
 Built-in Self Test (BIST)
 Boundary Scan
 Miscellaneous Topics

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