Design for Testability, Yield and

Reliability

Ganesh C. Patil
Course Contents
 Testability Analysis
 Fault Models

 Testability Measures

 ATPG

 Hazards

 Memory Testing, Delay Testing, IDDQ Testing

 DFT (BIST, JTAG, Boundary Scan)
 Yield and Reliability
 Formal Verification
 Property Checking
 Equivalence Checking
 RF Testing (If Time Permits)

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Books
 For Testing
 M. Bushnell and V. D. Agrawal, "Essentials of
Electronic Testing for Digital, Memory and
Mixed-Signal VLSI Circuits", Kluwer Academic
Publishers, 2000.
 L.-T. Wang, C.-W. Wu, X. Wen, “VLSI Test
Principles and Architectures Design for
Testability”, Morgan Kaufmann, 2006
 For Verification
 William K. Lam, “Hardware Design Verification:
Simulation and Formal Method-Based
Approaches”, Prentice Hall, 2005
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Grading Scheme
 Surprise Quizzes Weightage 10 %
 Home Assignments Weightage 10 %
(Hard Deadline for Submission)
 Theory Section
 Lab Section
 Sessional-I Exam : Weightage 10 %
(26th Aug. to 30th Aug.)
 Sessional-II Exam : Weightage 10 %
(7th Oct. to 11th Oct.)
 End Sem exam: Weightage 50 %
(22nd Nov. to 2nd Dec.)
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Design Complexity

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Motivation: Moore’s Law
Complexity Growth of VLSI circuits

Source (Copp, Int. AOC EW Conf., 2002)

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Microprocessor Cost per Transistor

Cost of testing will EXCEED cost of design/manufacturing

(Source: ITR-Semiconductor, 2002)
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Challenges under deep submicron
technologies

Chip size decreases Chip becomes hotter

Source: Wang et al. ISPD 2003
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Cont…..

Power density increases Leakage power make it worse

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 VLSI Realization Process
Customer’s need

Determine requirements

Write specifications

Design synthesis and Verification

Test development

Fabrication

Manufacturing test

Chips to customer
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Conventional SoC Design Flow

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Timeline of Design Cycle

Bottlenecks in Design Cycles: Survey of 545 engineers by EETIMES 2000

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 Definitions
 Design synthesis: Given an I/O function, develop a
procedure to manufacture a device using known
materials and processes.
 Verification: Predictive analysis to ensure that the
synthesized design, when manufactured, will
perform the given I/O function.
 Test: A manufacturing step that ensures that the
physical device, manufactured from the
synthesized design, has no manufacturing defect.

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 Verification vs. Test

 Verifies correctness of  Verifies correctness of manufactured

design. hardware.
 Performed by simulation,  Two-part process:
hardware emulation, or  1. Test generation: software
formal methods. process executed once during
 Performed once prior to design
manufacturing.  2. Test application: electrical tests

 Responsible for quality of applied to hardware

design.  Test application performed on every
manufactured device.
 Responsible for quality of devices.

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Levels of Testing
 Testing can be carried out at various levels:
 – Chip level
 – Board level
 – System level
 Cost :: Rule of 10
– It costs 10 times more to test a device as
we move to the next higher level in the
product manufacturing process.
device -> PCB -> system -> field operation

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Alternate Way of Classification
 Transistor level
 Gate level
 RTL level
 Functional level
 Behavioral level
Important to develop correct fault models and
Simulation models

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Some Real Defects in Chips
 Processing Faults
– missing contact windows, parasitic
transistors, oxide breakdown
 Material Defects
– bulk defects (cracks, crystal imperfections)
– surface impurities (ion migration)
 Time-Dependent Failures
– dielectric breakdown, electron migration
 Packaging Failures
– contact degradation, seal leaks
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Faults, Errors and Failures
 Fault: A physical defect within a circuit or a
system
– May or may not cause a system failure
 Error: Manifestation of a fault that results in
incorrect circuit (system) outputs or states
– Caused by faults
 Failure: Deviation of a circuit or system
from its specified behavior
– Fails to do what it should do
– Caused by an error
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Cont….

An example: a car with a flat tyre

– Fault : pin puncture in the tyre
– Error : Erroneous state of air pressure in
the tyre
– Failure : Car cannot be driven safely

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How To Do Test?
 Fault Modeling
– Identify target faults
– Limit the scope of test generation
 Test Generation
– Automatic or Manual
 Fault Simulation
– Assess completeness of tests
 Testability Analysis
– Analyze a circuit for potential problem on test
generation
 Design For Testability
– Design a circuit for guaranteed test generation
– Introduce both area overhead and performance
degradation Monday, August 01, 2022
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Basic Testing Principle

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Traditional Design Flow
Conduct testing after design

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New Design Mission
Design circuit to optimally satisfy or trade-off their
design constraints in terms of area, performance and
testability.

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New VLSI Design Flow

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The Infamous Design/Test Wall

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 Costs of Testing
 Design for testability (DFT)
 Chip area overhead and yield reduction
 Performance overhead
 Software processes of test
 Test generation and fault simulation
 Test programming and debugging
 Manufacturing test
 Automatic test equipment (ATE) capital cost
 Test center operational cost

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 Verification of DVD Player
DVD Player
•6 inputs
 Nothing is pressed
 Play, Pause, Stop
 FF, Rew

•Internal 5 States
Stopped,
Paused
Play at normal speed
Forward at 2X speed
Rewind at 2X speed

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Verification of DVD Player
 Assume 1024 x 786 pixels
 True colour(32 bits)
 Number of discrete states = 232
 Combination of current states to next states
 Pixels are independent
 Bounded number of total states=
No. of pixels x number of possible colours x number of
internal state machines
1024x786x 232 x5 = 16,888,498,602,639,360
 All transitions from current state to next states are
considered

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 Cont…
 Number of possible next states: No. of pixels x number of
possible colours x number of possible inputs
1024x786x 232 x6 = 20,266,198,323,167,232
 Possible current state to possible next states are to be verified
16,888,498,602,639,360 x 20,266,198,323,167,232 =3.4 x1032
 Assume a simulation engine can verify 1,000,000 transitions
per second
It needs 10,853,172,947,159,498,300 Years to verify

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Integration Technologies
 Integrated Circuits (ICs)
have grown in size and
complexity since the late
1950’s
 SSI
 MSI
 LSI
 VLSI
 Moore’s Law: scale of Ics doubles every 18
months
 Growing size and complexity poses many and new
testing challenges
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Importance of Testing
 Moore’s Law results from decreasing feature
size (dimensions)
 from 10s of μm to 10s of nm for transistors and
interconnecting wires
 Operating frequencies have increased from
100KHz to several GHz
 Decreasing feature size increases probability of
defects during manufacturing process
 A single faulty transistor or wire results in faulty IC
 Testing required to guarantee fault-free products

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Testing During VLSI Life Cycle
 Testing typically consists of
 Applying set of test stimuli to
 Inputs of circuit under test (CUT), and
 Analyzing output responses
 – If incorrect (fail), CUT assumed to be faulty
 – If correct (pass), CUT assumed to be fault-free

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Testing During VLSI Development
 Design verification targets design errors
 Corrections made prior to fabrication
 Remaining tests target manufacturing defects
 A defect is a flaw or physical imperfection that can
lead to a fault

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Design Verification
 Different levels of abstraction
during design
 CAD tools used to synthesize
design from RTL to physical level
 Simulation used at various
level to test for
 Design errors in behavioral or
RTL
 Design meeting system timing
requirements after synthesis

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Yield and Reject Rate

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Electronic System Manufacturing

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System-Level Operation

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System-Level Operation

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Test Generation
 A test is a sequence of test patterns, called
test vectors, applied to the CUT whose
outputs are monitored and analyzed for the
correct response
 Exhaustive testing – applying all possible test
patterns to CUT
 Functional testing – testing every truth table
entry for a combinational logic CUT

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Test Generation

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Test Generation
 Goal: find efficient set of test vectors with
maximum fault coverage
 Fault simulation used to determine fault
coverage
 Requires fault models to emulate behavior of
defects
 A good fault model:
 Is computationally efficient for simulation
 Accurately reflects behavior of defects

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Thank you !!!

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