Poster Session II
Analog Circuit Implementation of LIF and STDP Models for
Spiking Neural Networks
Zhitao Yang∗
11930679@mail.sustech.edu.cn
Southern University of Science and Technology
Shenzhen, China
Jianghan Zhu∗
11930680@mail.sustech.edu.cn
Southern University of Science and Technology
Shenzhen, China
ABSTRACT
Spiking Neural Networks (SNN) is one special implementation
of Artificial Neural Networks (ANN), where the input signals are
encoded in the temporal relationship between consecutive spikes
(spike trains) instead of real-numbered values. Nevertheless, SNN
is believed to be a closer representation of the biological neural
system, because it imitates the current spikes that are transmitted
between neurons in real biological systems. Practical and simplified
SNN models include the Leaky Integrate-and-Fire (LIF) function of
the neurons and the Spiking Timing Dependent Plasticity (STDP)
function of the synapses. While most ANN architectures can be
implemented with digital logic gates, SNN is more suitable to be
implemented in analog circuits. In this paper, we propose revised
analog circuit implementations of SNN neurons with LIF and STDP
functions. Compared with previous works by other researchers, our
proposed analog designs use fewer components and can be cascaded
to form a complete neural system. The circuits are designed and
simulated with SMIC 55nm CMOS LP process. The simulated results
demonstrate that the analog neural system can work under a very
small current (less than 10 µA) and voltage supply (1.0 Volts), and
consumes less power consumption than digital implementations.
CCS CONCEPTS
• Hardware → Very large scale integration design; Analog and
mixed-signal circuits; Analog and mixed-signal circuit optimization;
Network on chip.
∗ Department of Electrical and Electronic Engineering
† University Key Laboratory of Advanced Wireless Communications of Guangdong
Province
‡ Corresponding author
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GLSVLSI ’20, September 7–9, 2020, Virtual Event, China
© 2020 Association for Computing Machinery.
ACM ISBN 978-1-4503-7944-1/20/09. . . $15.00
https://doi.org/10.1145/3386263.3406940
469
GLSVLSI ’20, September 7–9, 2020, Virtual Event, China
Yucong Huang∗
11951011@mail.sustech.edu.cn
Southern University of Science and Technology
Shenzhen, China
Terry Tao Ye∗†‡
yet@.sustech.edu.cn
Southern University of Science and Technology
Shenzhen, China
KEYWORDS
Spiking Neural Networks, Leaky Integrate-and-Fire (LIF), Spiking
Timing Dependent Plasticity (STDP), Analog Circuit
ACM Reference Format:
Zhitao Yang, Yucong Huang, Jianghan Zhu, and Terry Tao Ye. 2020. Analog
Circuit Implementation of LIF and STDP Models for Spiking Neural Net-
works. In Proceedings of the Great Lakes Symposium on VLSI 2020 (GLSVLSI
’20), September 7–9, 2020, Virtual Event, China. ACM, Beijing, China, 6 pages.
https://doi.org/10.1145/3386263.3406940
1 INTRODUCTION
Artificial neural network (ANN) has demonstrated its promising
performance in recent years in many applications that include im-
age recognition, object detection, speech recognition, etc. Along
with these successes, ANN architectures also demand huge compu-
tational resources and data processing capabilities, the limitations
on power consumption, hardware resources and dependency on
huge data storage had been the bottleneck for ANN’s further de-
ployments.
Although inspired from biological neural models, ANN archi-
tectures, such as convolutional neural network (CNN) and recur-
rent neural network (RNN), all use float-point digital values to
represent the signals’ intensity and transition, with tremendous
multiplication-and-accumulation (MAC) computations at every
layer of ANN [1]. Compared with biological neural systems, dig-
ital logic circuit implementation of ANN consumes much larger
hardware resources as well as more power consumption.
Figure 1: Biological sketches of neurons and synapse.
However, in biological neural systems, as shown in Figure 1, the
signals are transmitted between neurons in the form of spikes, and
the information in the signal (such as intensity and transition) is
encoded in the temporal relationship between spikes (spike trains).
Poster Session II
That is why the spiking neural network (SNN) is gaining more and
more attention in recent years, as a much realistic representation
of the biological neural systems.
It has long been known that the reaction of neurons is determined
by the timing relationship between the spikes from the pre-neurons
as well as the spikes from post-neurons. This behavior is mathemati-
cally formulated in the Spiking Timing Dependent Plasticity (STDP)
model, where the relative timing order of spikes from pre-neuron
and post-neuron determines the potentiation level (can be positive
or negative) applied to the neuron. The potentiation levels created
from each synapse are integrated in the neuron, and when the accu-
mulated potentiation reaches a pre-defined threshold, the neuron
will emit a series of spikes to the next neuron, this mechanism
is modeled as Integrate-and-Fire (IF) mechanism. In some more
accurate modeling, the potentiation integrated at the neuron also
decreases over time, which is known as the Leaky Integra-and-Fire
(LIF) model.
Both STDP and LIF are fundamental mechanisms that govern
the behavior of SNN, and SNN implementation needs to accurately
represent these two models in order to achieve a good performance.
SNN have already been used in many applications like pattern
recognition [2] and speech recognition [3], which demonstrate
good results comparable to other ANN architectures.
Many different approaches of analog implementation of SNN
had been explored by different researchers. G. Indiveri, et. al. [4]
proposed an analog circuit to imitate the LIF function that con-
sisted of a source follower, three inverters and a current mirror
integrator. The leaky mechanism is achieved by a capacitor and a
single transistor to create a constant current leak. However, this
LIF circuit cannot be directly connected to the STDP module, so it
cannot be cascaded to form a complete neural system. J. M. Cruz-
Albrecht, et. al [5] presented a circuit with STDP mechanism. The
circuit consisted of a voltage-controlled current source (VCCS), a
hysteresis comparator, a resistor, and a capacitor. However, this
STDP circuit does not include the LIF function. A. Bofill-i-Petit,
et. al [6] presented a VLSI circuit containing neurons and STDP
synapse, nevertheless, the circuit structure of this work is very
complicated and needs a high voltage supply.
In this paper, a revised analog CMOS implementation of a com-
plete neural system with STDP and LIF functions is introduced. The
neural system can be constructed using cascaded LIF neuron mod-
ules and STDP synapses modules. The circuit is designed with the
SMIC 55nm LP CMOS process and operates under the sub-threshold
region, with a low power supply of 1.0 Volt, and achieves extremely
low power consumption.
This paper is organized as follows. In Section 2, the mechanisms
of LIF and STDP models are presented. Section 3 introduces the
circuit implementation of LIF and STDP functions. Circuit layout
and simulation results are presented in Section 4, followed by the
discussion and conclusion in Section 5.
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GLSVLSI ’20, September 7–9, 2020, Virtual Event, China
2 LIF AND STDP MODELS
2.1 LIF Model of Neurons
In SNN, signals are transmitted between neurons in the form of
current spike trains, the information carried by the signals is en-
coded in the temporal relationship between the spikes, instead of
the amplitude and shape [7].
Leaky-Integrate-and-Fire (LIF) is a well-accepted and popular
model of the neuron. In this model, potentials from different synapses
will accumulate and raise the potential level of the neuron (potenti-
ation) with leakage, once the potential reaches the threshold level,
a train of spikes is triggered at the output. The temporal density
of the output spikes is determined by the level of potentials, i.e., a
high level of potentiation will cause to fire a train of more densely
spaced spikes from the neuron.
The LIF circuit functionality can be illustrated in Figure 2, and
quantified by the following equation [8], as shown in Eq. 1:
𝑑𝑉𝑚 Õ
𝐶𝑚 = −𝑔(𝑉𝑚 − 𝑉𝑟𝑒𝑠𝑒𝑡 ) + 𝐶𝑚 Δ𝑉 𝛿 (𝑡 − 𝑡𝑖 ) (1)
𝑑𝑡 𝑖
Figure 2: LIF circuit functionality.
Where 𝐶𝑚 is the capacitance that integrates the input pulses, 𝑉𝑚
is the voltage on the capacitance, conductance 𝑔 is providing the
leakage, and is implemented using the pass transistor 𝑀1 , of which
its source-drain conductance is controlled by its gate voltage 𝑉𝑙𝑘 .
When the input current 𝐼𝑖𝑛 arrives at the neuron, the capacitor will
integrate the current and cause the voltage on the capacitance 𝑉𝑚 to
increase. Meanwhile, the conductance 𝑔 will drain the capacitance.
When the 𝑉𝑚 reaches the threshold voltage, a spike will be gener-
ated and cause the 𝑉𝑚 to return to the initial voltage 𝑉𝑟𝑒𝑠𝑒𝑡 . The
𝑉𝑚 will be recharged by the incoming current 𝐼𝑖𝑛 and the process
will repeat again to form a train of spikes. Figure 3 is an illustration
of the LIF process.
2.2 Synapse with STDP Model
Synapses form the connection for signals traveling between differ-
ent neurons. Each neuron may have several synapses, the accumu-
lated potentiation from different synapses determines the neuron’s
firing activity (through LIF mechanism). A widely accepted synap-
tic model was proposed by Hebbian in 1949 [9]. The theory, often
referred as the Hebbian’s Theory today, describes the principle of
the synaptic plasticity, i.e., the timing order of the spikes between
the pre and post neurons can cause either long-term potentiation
Poster Session II GLSVLSI ’20, September 7–9, 2020, Virtual Event, China

schematic is illustrated in Figure 5. All transistors in the circuit

operate in the sub-threshold region [12] with the same threshold
𝑉𝑡ℎ of 400mV. The power supply 𝑣𝑑𝑑 is set to be 1V, which can
bias the transistors under sub-threshold operation. The Schmitt
Trigger part (illustrated in the dotted region) consists of PMOS
transistors at the top and NMOS transistors at the bottom, which
form an inverter with highly nonlinear load working in a hysteretic
manner [13]. In this circuit, the NMOS W/L ratio is 250nm/200nm,
the PMOS W/L ratio is 400nm/200nm, 𝐶𝑚 equals 300nF.

Figure 3: LIF mechanism of a neuron.

(LTP) or long-term depression (LTD). The Spiking Timing Depen-

dent Plasticity (STDP) model quantifies this behavior and forms
the basic mechanism of the neural systems.
There are different models of STDP mechanism. In this work,
we adopt the pair-based STDP model [10], which has been used
in lots of studies, and its mechanism [11] can be formulated in the
following equation (Eq. 2): Figure 5: LIF function circuit implementation.

+ −Δ𝑡
 𝐴 exp ( 𝜏+ ), Δ𝑡 > 0



 Assume the voltage 𝑉𝑜 is high at the beginning. The input cur-
Δ𝑤 =

(2) rent 𝐼𝑖𝑛 is integrated on the capacitor 𝐶𝑚 and causes the voltage 𝑉𝑚
− Δ𝑡
Δ𝑡 on the capacitor to increase. Once the 𝑉𝑚 reaches the threshold volt-



 −𝐴 exp ( ), < 0
 𝜏− age, the Schmitt Trigger is triggered and set 𝑉𝑜 to low. 𝑉𝑜 also feeds
Where the potentiation level Δ𝑤 is determined by both the po- back to NMOS transistor 𝑀2 through an inverter 𝑈 1 . 𝑀2 causes
larity as well as the magnitude of Δ𝑡, which is the arrival timing the capacitor to quickly discharge until 𝑉𝑚 decreases to 𝑉𝑟𝑒𝑠𝑒𝑡 and
difference between spikes from pre and post neurons, and Δ𝑡 = the 𝑉𝑜 returns to its original value. A spike is fired through this
𝑡𝑝𝑟𝑒 −𝑡𝑝𝑜𝑠𝑡 . Δ𝑤 determines either potentiation (positive) or depres- process. As long as 𝐼𝑖𝑛 is applied at the input, a train of spikes will
sion (negative potentiation) state of the neuron, depending on the be generated. The inverter 𝑈 1 is powered by 𝑉𝑤𝑖𝑑𝑡ℎ , therefore, the
relative arrival time of 𝑡𝑝𝑟𝑒 and 𝑡𝑝𝑜𝑠𝑡 . 𝜏+ and 𝜏− are the time constant discharging speed of 𝐶𝑚 is controlled by 𝑉𝑤𝑖𝑑𝑡ℎ , which in turn
of the exponential relationship between Δ𝑤 and Δ𝑡 in potentiation controls the width of the spike. Additionally, the NMOS transistor
and depression state respectively. STDP behavior can be illustrated 𝑀1 controlled by 𝑉𝑙𝑘 forms the leakage channel to slowly discharge
in Figure 4. 𝐶𝑚 (to imitate the leaking), and the temporal density (the spacing
between the spikes) of the spike train is determined by the mag-
nitude of 𝐼𝑖𝑛 . The circuit closely imitates the behavior of the LIF
function.

3.2 STDP Circuit Implementation

Figure 4: Pair-based STDP mechanism.

Figure 6: STDP function circuits implementation (for

3 CIRCUIT DESIGN AND IMPLEMENTATION
3.1 LIF Circuit Implementation
We have proposed an analog circuit implementation of the LIF
function, following the diagram shown in Figure 2. The circuit
𝑡𝑝𝑟𝑒 <𝑡𝑝𝑜𝑠𝑡 case).
The implementation method of the STDP function is illustrated
in Figure 6. Upon the arrival of pre-neuron spike at 𝑡𝑝𝑟𝑒 , a voltage

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Poster Session II GLSVLSI ’20, September 7–9, 2020, Virtual Event, China

potential is generated by the “synapse potential” block. The voltage the PMOS W/L ratio is 400nm/200nm, and the capacitor 𝐶𝑝𝑜𝑡 1 and
potential starts to discharge until the arrival of post-neuron spike 𝐶𝑝𝑜𝑡 2 is about 300fF.
signal at 𝑡𝑝𝑜𝑠𝑡 , which closes the switch and passes the remaining
charge to the “transconductance amplifier”. The “transconductance
amplifier” amplifies the charge and consequently charges the ca-
pacitance 𝐶. In this process, if the post-neuron spike arrives imme-
diately after the pre-neuron spike, or |Δ𝑡 | = |𝑡𝑝𝑟𝑒 −𝑡𝑝𝑜𝑠𝑡 | is small,
more charge will be passed to the “transconductance amplifier” and
consequently create larger Δ𝑉𝑤 . However, if the post-neuron spike
arrives long after the pre-neuron spike, or |Δ𝑡 | = |𝑡𝑝𝑟𝑒 −𝑡𝑝𝑜𝑠𝑡 | is
large, Δ𝑉𝑤 is small.
This analysis demonstrates that the above design can imitate
the behavior of STDP function when Δ𝑡 = 𝑡𝑝𝑟𝑒 −𝑡𝑝𝑜𝑠𝑡 < 0. For the
case Δ𝑡 > 0, another complementary implementation is needed, as
shown in Figure 7.
Figure 8: Circuit implementation of the transconductance
amplifier.

The transconductance amplifier 𝑈 1 and 𝑈 2 operate under 1.0 V,

the details of the circuit are shown in Figure 8. It consists of three
current mirrors implemented by 𝑀1 -𝑀2 , 𝑀3 -𝑀5 , and 𝑀9 -𝑀10 , and
a differential pair implemented by 𝑀6 and 𝑀7 . The 𝑀8 is used as a
current source in the differential pair and controlled by 𝑉𝑔𝑠 . This
transconductance amplifier is enabled/disabled by two inputs, 𝑏𝑖𝑎𝑠
and 𝑔𝑎𝑡𝑒. When the input 𝑏𝑖𝑎𝑠 is high and 𝑔𝑎𝑡𝑒 is low, 𝑀4 and 𝑀11
are in the OFF state and 𝑀5 and 𝑀10 are in the ON state. When the
input 𝑏𝑖𝑎𝑠 is low and 𝑔𝑎𝑡𝑒 is high, 𝑀4 and 𝑀11 will be in the ON
state and cause transistor 𝑀5 and 𝑀10 to be in the OFF state. All of
the transistors have the same threshold voltage (400 mV), and in
this implementation, they all operate in the sub-threshold region.

Figure 7: Schematic of the STDP circuit (both 𝑡𝑝𝑟𝑒 <𝑡𝑝𝑜𝑠𝑡 and 4 SIMULATION RESULTS
𝑡𝑝𝑟𝑒 >𝑡𝑝𝑜𝑠𝑡 cases). 4.1 LIF Circuit
The complete circuit is designed with SMIC 55nm LP (low power)
The design has two parts, namely, the top part corresponds to process node and simulated under HSPICE. Different input patterns
the case where 𝑡𝑝𝑟𝑒 <𝑡𝑝𝑜𝑠𝑡 , and the bottom parts corresponds to the are applied to test the circuit.
complementary case where 𝑡𝑝𝑟𝑒 >𝑡𝑝𝑜𝑠𝑡 . When the pre-neuron spike
arrives, transistor 𝑀1 is conducting and 𝐶𝑝𝑜𝑡 1 begins to charge,
when the post-neuron spike arrives, the gate of the transconduc-
tance 𝑈 1 is opened; the remaining charge on 𝐶𝑝𝑜𝑡 1 drives 𝑈 1 from
terminal 𝑖𝑛𝑝 and consequently charges 𝐶 𝑤 , which causes 𝑉𝑤 to
rise. Conversely, when the post-neuron spike arrives before the
pre-neuron spikes, the bottom part will work complementarily.
Please notice that in the bottom part, 𝐶𝑝𝑜𝑡 2 is connected to the 𝑖𝑛𝑛
terminal of the transconductance 𝑈 2 , therefore, when 𝑡𝑝𝑟𝑒 >𝑡𝑝𝑜𝑠𝑡 ,
𝐶 𝑤 will be discharged and 𝑉𝑤 will decrease accordingly.
More specifically, in this design, the timing constant 𝜏+ and 𝜏−
for 𝑡𝑝𝑟𝑒 <𝑡𝑝𝑜𝑠𝑡 and 𝑡𝑝𝑟𝑒 >𝑡𝑝𝑜𝑠𝑡 conditions in Eq. 2 are controlled by
the voltage signal 𝑉𝑡𝑎𝑢−𝑝𝑟𝑒 and 𝑉𝑡𝑎𝑢−𝑝𝑜𝑠𝑡 respectively, i.e., capac-
itance 𝐶𝑝𝑜𝑡 1 and 𝐶𝑝𝑜𝑡 2 are discharged through transistor 𝑀2 and Figure 9: Simulation results of the LIF neuron circuit.
𝑀4 , 𝑉𝑡𝑎𝑢−𝑝𝑟𝑒 and 𝑉𝑡𝑎𝑢−𝑝𝑜𝑠𝑡 control the gate of 𝑀2 and 𝑀4 and con-
sequently control how much charges on 𝐶𝑝𝑜𝑡 1 and 𝐶𝑝𝑜𝑡 2 can be In LIF function, the temporal density of the output spike train
passed through 𝑈 1 and 𝑈 2 to charge/discharge 𝐶 𝑤 . is modulated by the potentiation level 𝐼𝑖𝑛 . In order to verify this
Compared with other STDP implementations in [14] [15]. We mechanism, current input 𝐼𝑖𝑛 with different values is applied. 𝑉𝑙𝑘 is
adopt a much simpler design [11], the time constant of 𝑉𝑡𝑎𝑢−𝑝𝑟𝑒 set to 500mV and 𝑉𝑤𝑖𝑑𝑡ℎ is set to 900mV. The simulation results are
(also 𝑉𝑡𝑎𝑢−𝑝𝑜𝑠𝑡 ) only needs three transistors to implement, as shown illustrated in Figure 9, the top trace is the value of 𝐼𝑖𝑛 , the middle
in Figure 7. In our design, the NMOS W/L ratio is 250nm/200nm, trace is the voltage 𝑉𝑚 on the capacitor 𝐶𝑚 , and the bottom trace

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Poster Session II GLSVLSI ’20, September 7–9, 2020, Virtual Event, China

Table 1: Comparison of energy per spike between our neu-

ron circuit and other circuit designs

Reference Energy per Spike[pJ]

Indiveri [4] 3000 ∼ 15000
Indiveri [16] 900
Wijekoon [17] 8.5 ∼ 9
Cruz-Albrecht [5] 0.4
This work 45.26

is the output spike train. Obviously, when the current 𝐼𝑖𝑛 goes into
the LIF neuron circuit, 𝑉𝑚 begins to rise, and only when 𝑉𝑚 reaches
the threshold, as seen in the figure, the capacitor quickly discharges
and creates a spike. And it is clear that the spike train is getting
denser when the current 𝐼𝑖𝑛 gets larger, which is expected with the
LIF neuron model.
When being operated under 1.0 Volt of power supply, with 𝑉𝑙𝑘
set to 500mV and 𝑉𝑤𝑖𝑑𝑡ℎ set to 900mV, the LIF circuit consumes
45.26pJ of energy per spike. Table 1 lists the comparison of energy
per spike between our implementation and other designs. In fact,
different implementations were aimed at different applications, for
example, some circuits operate in pA range and cannot be used
together with other circuits. That is why the energy consumption
in Table 1 differ so significantly and is hard to compare fairly. More
specifically, the input current range is ∼0.1µA in [17] and the input
current is in pA range in [5]. In our design, the current spike is in
the range of ∼µA, which can be easily integrated with other CMOS
circuits.
4.2 STDP Circuit
To verify the functionality of our STDP implementation, pre-neuron
spike trains as well as post-neuron spike trains are programmed
in HSPICE and generated as inputs. By manipulating the timing
relationship between the pre and post neuron spike pairs, we can
accurately test the potentiation level of the STDP circuit under
different spike pairs. The spike pulse has a width of 0.5ms with 1.0V
amplitude, which is compatible to the neuron output spikes from
our LIF circuit.
Figure 10(a) illustrates the simulation results. The top trace is
the pre-neuron spike train and the second trace is the post-neuron
spike train, the output potentiation 𝑉𝑤 is illustrated in the third
trace. Both 𝑡𝑝𝑟𝑒 <𝑡𝑝𝑜𝑠𝑡 and 𝑡𝑝𝑟𝑒 >𝑡𝑝𝑜𝑠𝑡 cases are tested. At first, pre-
neuron spike arrives before post-neuron spike, or 𝑡𝑝𝑟𝑒 <𝑡𝑝𝑜𝑠𝑡 , 𝑉𝑤
increases. Then post-neuron spike arrives before pre-neuron spike,
and 𝑉𝑤 decreases accordingly. The simulation results align well
with the STDP mechanism.
We have generated different pairs of pre-neuron spikes and post-
neuron spikes and plot the resulting potentiation Δ𝑉𝑤 in Figure
10(b). The relationship between Δ𝑡 and Δ𝑉𝑤 closely follow Eq.2,
and proves that our STDP circuit successfully imitate the STDP
functionality.
4.3 Integration with LIF and STDP Functions
Previous designs of neuromorphic circuits focus mostly on the
individual implementation of either LIF or STDP functions. Fewer
(a)
(b)
Figure 10: Simulation results of the STDP circuit. (a) Potenti-
ation changes in the case of 𝑡𝑝𝑟𝑒 <𝑡𝑝𝑜𝑠𝑡 and 𝑡𝑝𝑟𝑒 >𝑡𝑝𝑜𝑠𝑡 . (b) The
potentiation and 𝑡𝑝𝑟𝑒 / 𝑡𝑝𝑜𝑠𝑡 arrival timing relationship.
of those works integrate the LIF and STDP functions together to
form a complete neuron. However, in real biological neural systems,
the potentiation generated from the STDP function at each synapse
is accumulated at the neuron and controls the firing behavior of
spike trains through the LIF mechanism. Therefore, it is crucial
that the STDP output can be cascaded into LIF function to imitate
a complete neuron. In this work, we have tuned the STDP and LIF
circuits such that the outputs and inputs of different modules can
be cascaded.
We use two LIF blocks and one STDP block to demonstrate the
complete neuron integration. The two LIF blocks generate the pre-
neuron and post-neuron spike trains, and feed the spike trains to
the STDP block as inputs, as shown in Figure 11(a). The results
are shown in Figure 11(b). The top and middle traces illustrate the
pre-neuron spike train and post-neuron spike train respectively.
The potentiation changes (𝑉𝑤 ) from STDP block are shown in the
bottom trace. Because we are using the pairwise STDP model, the
weight will be determined by each pair of pre and post neuron
spikes. The potentiation variation can be clearly seen from the
bottom trace of Figure 11(b). When the post-neuron spike arrives
before the pre-neuron spike, the weight decreases and when the
pre-neuron spike arrives before the post-neuron spike, the weight
increases. These results match well with the STDP model.
The 2-LIF-1-STDP circuit had been designed with SMIC 55nm
LP process, and the layout is illustrated in Figure 12. The whole

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Poster Session II
(a)
(b)
Figure 11: STDP potentiation (weight) changes under the
spike trains from pre-neuron and post-neuron train gener-
ated from LIF. (a) Circuit schematic. (b) Testing results.
Figure 12: Layout of the LIF and STDP integration (two LIF
neuron circuits and a STDP circuit).
layout area is 44.807 × 34.933𝜇𝑚 2 , and can be operated under 1.0
volts power supply. Specifically, in this design, with the frequency
of pre-spike train equals 30Hz and the frequency of post-spike
train equals 20Hz, the power consumption of the whole circuit is
4.907𝜇𝑊 .
5 CONCLUSION
In this paper, analog circuit implementations of spiking neural net-
works (SNN) are explored. Both the Leaky-Integrate-and-Fire (LIF)
functions of the neurons as well as the Spiking Timing Dependent
Plasticity (STDP) functions of the synapses are proposed and tested.
Compared with previous works by other researchers, the circuits
for the LIF and the STDP functions are much simpler and have fewer
components. And the LIF neuron circuit can be easily cascaded with
the STDP circuit. The pulse width, the leaky time constant as well
474
GLSVLSI ’20, September 7–9, 2020, Virtual Event, China
as the STDP sensitivity can all be parameterized to imitate real-life
biological neural systems. Designed with the SMIC 55nm LP pro-
cess, the circuit simulation demonstrates that the circuit functions
align well with the biological modeling. Furthermore, the circuits
can operate in the sub-threshold domain and consume extremely
low power consumption.
ACKNOWLEDGMENTS
Thanks to the fund and support of Key-Area Research and Develop-
ment Program of Guang Dong Province (Project No. 2019B010140001
and 2019B010142001), High-level University Fund, (Project No.
G02236002), and University Key Laboratory of Advanced Wireless
Communications of Guangdong Province (Project No.2018KSYS005).
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