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#l embedding and construct a heuristic 1-dimensional ordering of the

modules. Dynamic programming is then applied to efficiently compute the
optimal k-way split of the ordering for a variety of objective functions. This
integrated technique yields multi-way partitioning with lower cost than previ-
ous spectral approaches.
It has been shown that a linear objective yields better spectral placement in
terms of wirelength than a quadratic objective. On the other hand, a quadratic
objective tends to place nodes more sparsely than a linear objective, resulting
in less overlap among the nodes. The authors of [Li et al., 1996] proposed so
called the α-order objective function, which is linear α (1 ≤ α ≤ 2). Depending
on how to tune α, the objective becomes closer to linear or quadratic. The goal
is to capture the benefit of both the linear and quadratic objectives.
FBB Algorithm
Logic replication has been shown empirically to reduce pin count and parti-
tion size in partitioned networks. The authors of [Hwang and El Gamal, 1995]
presented a network flow based algorithm for determining min-cut replication
from a given partitioning solution. The algorithm is extended to hypergraphs,
and replication heuristics are proposed to handle area balance constraints.
When applied to the problem of partitioning a given design to multiple field-
programmable gate arrays (FPGA), it is shown that min-cut replication pro-
vides substantial reductions in the numbers of FPGAs and pins required.
Given a flow network G with only two-pin nets, the authors of [Liu et al.,
1995] first introduced an algorithm for optimum partitioning with replication
under no area constraints. Compared with [Hwang and El Gamal, 1995] which
requires an initial partitioning solution, this work computes both partitioning
and replication simultaneously. Several heuristic extensions are then added to
handle multi-pin nets and area balance constraints. The authors show that the
area overhead from replication can be traded for cutsize reduction.
The authors of [Liu and Wong, 1998] extended the FBB algorithm to han-
dle multi-way partitioning under both area and pin constraints. This problem
occurs when a design needs to be partitioned into multiple FPGAs. Given a
netlist graph G(V, E), the basic approach is to find a subset of nodes V i ∈ V
so that V i satisfies both area and pin constraint. This is done by repeated com-
putation of maximum flow. The authors try to maximize the area of V i in order
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