VerilogHDL

Verilog HDL

92


.................................................... III
................................................... IV
.................................................... V
............................................... 1
1.1 ........................................... 1
1.2 ........................................... 1
1.3 IC .................................... 2
1.3.1 ........................ 2
1.3.2 ............................ 2
1.3.3 .................... 3
1.3.4 .................................. 4
1.3.5 ................................ 4
1.3.6 IC ............................. 4
1.3.7 HDL .............................. 5
1.4 ................................... 6
1.5 ........................................... 6
IC .............................. 7
2.1 VHDL Verilog................................. 7
2.1.1 ...................... 7
2.1.2 HDL....................... 7
2.1.3 VHDL Verilog ......................... 7
2.1.4 Verilog HDL ........................... 10
2.1.5 ....................... 10
2.2 IC ............................. 11
2.2.1 IC ...................... 11
2.2.2 ......................... 12
Altera ............................ 13
3.1 OPEN FPGA 3.0 .......................... 13
3.2 OPEN FPGA 3.0 ....................... 14
3.3 EMP3064A .......................... 14
3.4 ...................................... 14
3.5 MAX3000A ..................................... 15
I

 ..................................
4.1 ....................................
4.2 ....................................
4.3 ......................................
................................
5.1 ..........................................
5.2 ..........................................
5.3 ......................................
5.4 rpt ......................................
5.5 ........................................
........................................
6.1 MAX+PLUS ..............
6.2 MAX+PLUS ......................
6.3 ..........................................
..............................................
7.1 ..............................................
7.1.1 OPEN FPGA 3.0 ...................
7.1.2 Verilog HDL .....................
7.1.3 License .......................
7.1.4 .............................
7.1.5 .....................................
7.1.6 Verilog HDL C .......................
7.2 ............................................
7.2.1 Verilog HDL ...............
7.2.2 .....................................
7.2.3 License ...............................
7.2.4 ModelSim ..............................
7.2.4 .....................................
7.2.5 .............................
7.2.6 .................................
7.3 ..........................................
............................................

II

16
16
19
19
21
21
21
22
22
24
25
25
30
33
39
39
39
39
39
40
41
42
42
42
42
43
43
43
44
44
44
46


IC
Verilog HDL VHDL
IC
OPEN FPGA 3.0

III

2-1 IC ....................... 11
3-1IC ........................... 13
4-1Altera ........................... 16
4-2............................ 17
4-3.................................. 17
4-4.................................. 18
4-5................................ 18
4-6JTAG ..................... 19
4-7................ 20
4-8............................ 20
5-1.............................. 22
6-1Compiler ................................. 25
6-2Assign Device................................. 26
6-3 EMP3064ATC44-4 ........................... 26
6-4...................................... 27
6-5...................................... 28
6-6.................................... 29
6-7...................................... 30
6-8Waveform Editor............................... 30
6-9...................................... 31
6-10................................. 31
6-11 rst ..................................... 32
6-12 clk ..................................... 32
6-13..................................... 33
6-14................................... 33
6-15................................... 34
6-16................................... 35
6-17................................... 36
6-18................................... 36
6-19................................... 37
6-20................................... 38

IV


1-1........... 5
5-1.......................... 21


1.1
IC
68.7%

IC
SOC

IC
IC

JTAG OPEN FPGA 3.0

IC
IC IC

IC IC
ModelSimLeonardo
SpectrumMAX+PLUS BASELINE
ALTERA
IC IC
IC

1.2
,

OPEN FPGA 3.0

IC
IC

1.3 IC
1.3.1
21

1.3.2

PDA

Application Engineer

Back-endPCB Layout

Front-end
ARM
Intel Intel IC IC Designer
IC

IP-Intellectual Property IC
Back-endIC
Placement & Routing

IC
Front-endIC
Intel IC ARM
ARM IP
IP Designer
IP

IC
2

SOC

ARM IP
IC

IC

Linux
Open Source

1.3.3

Virtual Fab
Engineering
Collaboration

VNC-Virtual Network Computing

1.3.4

ASPApplication Service Provider

IC
IC
IC
CAD-Computer Added Design
IC
IC

EDA-Electronic Design Automation

IC

IC

1.3.5

IC

IC
HDLHardware Description Language
EDA-Electronic Design Automation
PLD-Programmable Logic Device
IC
1.3.6 IC
IC
4

Synthesis & Simulation

Emulation

IC
IC
IC

ModelSim
Leonardo Spectrum
MAX+PLUS BASELINE
1.3.7 HDL
IEEE
Verilog HDL VHDLVerilog HDL C
VHDL

VHDL Verilog HDL

System C
Verilog HDL

IC

.v->.edf->.pof
Editor.c ->Complier.obj

->Linker.exe

1-1

1.4
PAL Programmable Array Logic GAL Generic Array
LogicCPLDComplex Programmable Logic Device
FPGAField Programmable Gate Array

Programmable Logic Device

CPLD
FPGA PAL GAL
SPLDSimple Programmable Logic
Device

Verilog HDL VHDL

FPGA CPLD IC

1.5

IC IC
Verilog HDL VHDL IC

Altera OPEN FPGA

3.0 EMP3064A
MAX3000A

 IC
2.1 VHDL Verilog
2.1.1
(1)SSI

(2)MSI

(3)LSI

(4)
CADComputer
Aided Design
2.1.2 HDL

Hardware Description Language

(1)
(2) Verilog HDL VHDL
(3)Verilog HDL Gateway Design Automation
(4)VHDL DARPA

(5)1980

Register Transfer Level

(6)

(7)
system boards
interconnect buses

FPGAs Field Programmable Gate Arrays PALs

Programmable Array Logic
2.1.3 VHDL Verilog
VHDL is like structural language ADAVerilog is like C++
7

VHDL Verilog
1970 1980 The
United States Department of Defense

reuse
VHSICVery High Speed Integrated
Circuit
formatsyntax

VHSIC

gate level

VHSIC VHSIC
Hardware Description Language 1982
VHDL 1986
International Electrical & Electronic
EngineeringIEEE IEEE
standard 1076
Gateway Design Automation
1984 VHDL Verilog
HDL VHDL Verilog HDL
Programming Language Interface, PLI

Verilog

VHDL

reuse

VHDL
8

VHDL PASCAL Verilog

C Verilog
C
Verilog VHDL
Verilog VHDL
Verilog
Gateway
EDA ASIC
Application Specific Integrated Circuit Foundry
Simulator
Gateway Verilog
Verilog-XL
Verilog

primitive model
ASIC
sign-off
VHDL
ASIC
Verilog
Verilog
ASIC
time-to-market
Verilog
niche
ASIC Verilog
Verilog HDL
1987
Synopsys Verilog HDL
digital circuit synthesizer
Verilog

Verilog HDL get-level

net-list
Verilog
9


Verilog
Verilog

ASIC EDA
VHDL IEEE standard
Verilog
VHDL EDA VHDL
Verilog EDA
Verilog IEEE
1995 Verilog IEEE
IEEE standard 1364
EDA

EDA

Verilog HDL
VHDL VHDL

2.1.4 Verilog HDL

Verilog HDL
(1)Verilog HDL
C
(2)Verilog HDL
(3) Verilog HDL

(4) Verilog HDL

(5) C Verilog
HDL
2.1.5
(1)

10

(2)

(3)

(4)
RTL
Verilog HDL
(5)

RTL
(6)
bottom-up Verilog HDL

2.2 IC
2.2.1 IC

2-1 IC
11

2.2.2

(1)

(2)

(3)

12

 Altera
3.1 OPEN FPGA 3.0

Test Pattern
Test Coverage
FGPA

IC
OPEN FPGA 3.0
IC
IC

3-1IC
OPEN FPGA 3.0
ALTERA CPLD MAX EPM3064A-100TQFP-10
8 LED
4
8

512 KHz
JTAG
3.3V 5V

13

3.2 OPEN FPGA 3.0

(1) Altera CPLD MAX EPM3064A-100TQFP-100TQFP-10

(2)9 /500ma
(3)9 5 3.3
(4) 512KHz
(5)JTAG
(6)
8
4
(7)
8 LED

(8)
3.3 EMP3064A
Altera EMP3064A PLD OPEN FPGA 3.0

(1)CMOS EEPROM

(2) JTAG ISP

(3)MultiVoltI/O 5V3.3V 2.5V
(4) 1250 gates
(5) I/O 64
3.4
(1)
OPEN FPGA 3.0
8 LED

8 8
LED
(2)8
OPEN FPGA 3.0

8 LED
14


(3)8 LED
OPEN FPGA 3.0 LED

LED
(4)
OPEN FPGA 3.0

7SEGM_IO1
7SEGM_IO2

(5)
OPEN FPGA 3.0
512KHz
1KHz
3.5 MAX3000A
MAX3000A ISP
3.3V MAX3000A
ISP
32 256 4.5ns

15


4.1
(1) Altera
Altera
http://www.altera.com/support/licensing/lic-index.html
Free Software Licenses

4-1Altera
(2)MAX+PLUS II Student Edition software
Version 10.1 or 9.23 Continue
(3) MS-DOS
dir/p Continue

16

 4-2
(4)
E-mail
Continue
C:\flexlm

4-3
17

(5)

Next

Next
(6) MAX+PLUS II 10.1 BASELINE
MAX+PLUS 10.1 BASELINEOptionsLicense
SetupBrowse4

License.datOK
MAX3000A Family Unlicensed Features
Licensed Features OK

4-4

4-5
18

4.2
(1) OPEN FPGA3.0
JTAG

4-6JTAG
(2) OPEN FPGA 3.0

4.3
License
Free
License
Compiler

MAX+PLUS License
License
License Compiler

License Verilog Entry

License
19

4-7:

4-8

20


5.1
Q
LED

rst

LED
LED 0
1

7 3
7
17

7 3
10
5.2

mgsrnull
7
mysrnull
3
mgml
sr
bz7
mrsgnull
7
mrsynull
3
5-1
21

 5-1
5.3
512KHZ
64KHZ512/2^3 512KHZ 1

15.625us 16us End

Time 16us
End Time 900us
2 clk 500ns

1.clk

2.

3.counter
5.4 rpt

22

75%
** DEVICE SUMMARY **
Chip/
POF

tl

Device

EPM3064ATC100-4

User Pins:

Input

Output

Bidir

Shareable

Pins

Pins

Pins

LCs

Expanders

% Utilized

48

27

75 %

** RESOURCE USAGE **
Logic Array Block
A:

LC1 - LC16

B:

Logic Cells

I/O Pins

Shareable

External

Expanders

Interconnect

1/166%

1/166%

1/166%

8/3622%

LC17 - LC32

16/16100%

5/1533%

16/16100%

27/3675%

C:

LC33 - LC48

15/16 93%

6/1637%

16/16100%

26/3672%

D:

LC49 - LC64

16/16100%

2/1513%

15/16 93%

21/3658%

Total dedicated input pins used:

1/4
Total I/O pins used:
14/62
Total logic cells used:
48/64
Total shareable expanders used:
27/64
Total Turbo logic cells used:
48/64
Total shareable expanders not availablen/a: 21/64
Average fan-in:
8.83
Total fan-in:
424
Total input pins required:
2
Total output pins required:
9
Total bidirectional pins required:
0
23

25%
22%
75%
42%
75%
32%

Total
Total
Total
Total
Total
Total

reserved pins required:

logic cells required:
flip flops required:
product terms required:
logic cells lending parallel expanders:
shareable expanders in database:

Synthesized logic cells:

4
48
17
190
0
26
21/64

32%

5.5
state next_state
finite state machine
Compiler

always always
Verilog HDL
always

always

24


6.1 MAX+PLUS
(1) MAX+PLUSFileProject
Name
(2) MAX+PLUS.v .pof

d:\eden-3\example\traffic\rtl\TL.v
OK
(3)MAX+PLUSCompiler

Start
MAX3000A
EMP3064ALC44-4

6-1Compiler
(4)
AssignPin/Location/Chip

Assign Device
25

 6-2Assign Device
(5)Compiler Device Family
MAX3000AEMP3064ATC44-4
44 Devices
EMP3064ATC100-4

6-3 EMP3064ATC44-4
(6)
26

Search
Node Name*
List Nodes of Type
Output
Bidirectional

Input
List
(7) 11
clkOK

6-4
(8)
clk OPEN FPGA 3.0
clk 87 512 KHz
Pin Type
Add
(9)7

bz = 69Pin Type = Output

clk = 87Pin Type = Input
27

mg = 35Pin Type = Output

ml = 40Pin Type = Output
mr = 37Pin Type = Output
my = 36Pin Type = Output
null = 41Pin Type = Output
rst = 29Pin Type = Input
sg = 45Pin Type = Output
sr = 42Pin Type = Output
sy = 44Pin Type = Output
(10)
Start
.pof OPEN FPGA 3.0

6-5
(11) MAX+PLUS BASELINE MAX+PLUS
Programmer
OptionsHardware Setup

(12)Hardware TypeByte Blaster

28

MV
Parallel Port
OK
(13)File
Select Programming File
Step 10 tl.pof

OK

6-6
(14)Program
LED

29

 6-7
6.2 MAX+PLUS
(1)MAX+PLUSWaveform Editor

6-8Waveform Editor
30

(2)NodeEnter Nodes from SNF

OK

6-9
(3)FileEnd Time
End Time Time 900us
OK

6-10
31

(4) rst clk rst 1 clk

Overwrite Clock

Clock Period 500nsOK

6-11 rst

6-12 clk
32

(5)Start

6-13
6.3
(1)

6-14
33

(2)
mg=0sr=0bz=0

6-15
(3) 7 7
mg=0sr=0bz=0

34

 6-16
(4)
my=0sr=0bz=0

35

 6-17
(5) 2 2
my=0sr=0bz=0

6-18
(6)
36

mr=0ml=0sr=0bz=0

6-19
(7) 7 7
mr=0ml=0sr=0bz=1

37

 6-20
(8)

38


7.1
7.1.1 OPEN FPGA 3.0

7.1.2 Verilog HDL

IC www.icdiy.org
--

Verilog HDL
Test
BenchFunction Module
Verilog HDL

7.1.3 License

MAX+PLUSLeonardo Spectrum
ModelSim
MAX+PLUSLeonardo Spectrum
License

MAX+PLUS
License Leonardo
39

Spectrum License
License
autoexec.bat

E-mail CIC
License
Leonardo Spectrum License NIC Number
ipconfig/all MAX+PLUS LicenseHard disk
volume serial number dir/p

ModelSim License

7.1.4

Leonardo Spectrum License

.v
.edf MAX+PLUS
.pof
LeonardoSpectrum

LeonardoSpectrum
.pof MAX+PLUS
.v .pof
MAX+PLUS
Leonardo Spectrum

40


Leonardo Spectrum
Compiler

MAX+PLUS

MAX+PLUS

Chip Chip
MAX+PLUS
Leonardo Spectrum
MAX+PLUS
Leonardo Spectrum

MAX+PLUS

Verilog HDL

7.1.5

Leonardo Spectrum

MAX+PLUS compiler rpt

75% 3/4 compiler
rpt

41

 Verilog HDL

7.1.6 Verilog HDL C

Verilog HDL C
C

Verilog HDL

C Verilog HDL

C Verilog HDL
7.2
7.2.1 Verilog HDL

7.2.2
MAX+PLUSLeonardo Spectrum
ModelSim MAX+PLUS
Leonardo Spectrum
ModelSim

42

C pin
MAX+PLUS
Assign Pin/Location/Chip
MAX+PLUS Waveform Editor
MAX+PLUS

MAX+PLUS
7.2.3 License
MAX+PLUS
License
License
License
MAX+PLUSLeonardo Spectrum
License MAX+PLUS
Leonardo Spectrum License Setup Leonardo
Spectrum License
License

License
License

License

7.2.4 ModelSim
License

License

7.2.4
43

 LED
10

01

7.2.5

http://www.cic.edu.tw/cicforum/index.php3
CIC CIC
altera Altera

IC

7.2.6

7.3

key-in

44


[1]IC 2002
6
[2]CPLD 90 3 10
[3] CPLD -
87 2
[4]CPLD -
90 9
[5]CPLD Max+plusII
2001 8
[6]CPLD MAX+plus II
88 10
[7] CPLD MAX+plus II

[8] FPGA
90 7 1
[9] VHDL FPGA 90 5

[10]Van den BoutDave, XILINX FPGA/CPLD

87
[11]VHDL FPGA 90
[12] http://www.icdiy.org
[13] http://www.cic.edu.tw/cicforum/index.php3

45


//**********************************************************
module
//**********************************************************
module tlclk,rst,mg,my,mr,ml,sg,sy,sr,null,bz;
input clk,rst; // 512khz rst

reg [4:0]Q; //
output mg,my,mr,ml,sg,sy,sr,null; //
output bz; //
reg mg,my,mr,ml,sg,sy,sr,null;
//**********************************************************

//**********************************************************
reg [10:0] count_1; //
wire
clk_1;
always @ posedge clk begin // clk = 512KHz
count_1=count_1+1;
end
assign clk_1=count_1[10];

// 11-bit 250Hz

reg [7:0] count_2; //

wire
clk_2;
always@posedge clk_1 begin
count_2=count_2+1;
end
46

// clk = 250Hz

assign clk_2=count_2[7];

// 8-bit 0.97Hz

assign bz =clk_2&!my|clk_2&!sy
;
//
//**********************************************************

//**********************************************************
always@posedge clk_2 or negedge rst
begin
if!rst
//
01
begin
mg=1'b0;
my=1'b1;
ml=1'b1;
mr=1'b1;
sg=1'b1;
sy=1'b1;
sr=1'b0;
null=1'b1;
Q=5'b00000;
end
else ifmg==1'b0&&sr==1'b0&&Q!=5'b00111
// 7
begin
mg=1'b0;
my=1'b1;
ml=1'b1;
mr=1'b1;
sg=1'b1;
sy=1'b1;
47

sr=1'b0;
null=1'b1;
Q=Q+1;
end
else ifmg==1'b0&&sr==1'b0&&Q==5'b00111
// 7
begin
mg=1'b1;
my=1'b0;
ml=1'b1;
mr=1'b1;
sg=1'b1;
sy=1'b1;
sr=1'b0;
null=1'b1;
Q=5'b00000;
end
else ifmy==1'b0&&sr==1'b0&&Q!=5'b00010
// 2
begin
mg=1'b1;
my=1'b0;
ml=1'b1;
mr=1'b1;
sg=1'b1;
sy=1'b1;
sr=1'b0;
null=1'b1;
Q=Q+1;
end
else ifmy==1'b0&&sr==1'b0&&Q==5'b00010
// 2
begin
mg=1'b1;
48

my=1'b1;
ml=1'b0;
mr=1'b0;
sg=1'b1;
sy=1'b1;
sr=1'b0;
null=1'b1;
Q=5'b00000;
end
else ifmr==1'b0&&ml==1'b0&&sr==1'b0&&Q!=5'b00110
// 6
begin
mg=1'b1;
my=1'b1;
ml=1'b0;
mr=1'b0;
sg=1'b1;
sy=1'b1;
sr=1'b0;
null=1'b1;
Q=Q+1;
end
else ifmr==1'b0&&ml==1'b0&&sr==1'b0&&Q==5'b00110
// 6
begin
mg=1'b1;
my=1'b1;
ml=1'b1;
mr=1'b0;
sg=1'b0;
sy=1'b1;
sr=1'b1;
null=1'b1;
Q=5'b00000;
49

end
else ifmr==1'b0&&sg==1'b0&&Q!=5'b00111
// 7
begin
mg=1'b1;
my=1'b1;
ml=1'b1;
mr=1'b0;
sg=1'b0;
sy=1'b1;
sr=1'b1;
null=1'b1;
Q=Q+1;
end
else ifmr==1'b0&&sg==1'b0&&Q==5'b00111
// 7
begin
mg=1'b1;
my=1'b1;
ml=1'b1;
mr=1'b0;
sg=1'b1;
sy=1'b0;
sr=1'b1;
null=1'b1;
Q=5'b00000;
end
else ifmr==1'b0&&sy==1'b0&&Q!=5'b00010
// 2
begin
mg=1'b1;
my=1'b1;
ml=1'b1;
mr=1'b0;
50

sg=1'b1;
sy=1'b0;
sr=1'b1;
null=1'b1;
Q=Q+1;
end
else ifmr==1'b0&&sy==1'b0&&Q==5'b00010
// 2
begin
mg=1'b0;
my=1'b1;
ml=1'b1;
mr=1'b1;
sg=1'b1;
sy=1'b1;
sr=1'b0;
null=1'b1;
Q=5'b00000;
end
end
endmodule

51