ACEE 7

Parity Bit Error Generator

and Checker
Members:
MALABANAN, ISMAEL J.
VILLAMAYOR, JULZ HENRYK L.
LAPITAN, AARON RONALD S.
DELOS SANTOS, KYLE ANDRIE B.
CARPIO, VINCH HIZON L.
BSEE 3B
 Introduction
A 3-bit odd parity error generator is a circuit designed to produce an error every time a given set of inputs
is present. This circuit can be used to test digital systems for the ability to detect and correct errors. The
3-bit odd parity error generator is made up of logic gates and flip-flops arranged in a specific
configuration. This configuration can be designed to generate a single-bit error at certain steps of the
circuit.
 3-bit Odd Parity Error Generator
Truth Table Karnaugh Map

3 Bit Parity
A B C P
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
3-bit Odd Parity Error Generator
Boolean Algebra Solution
 3-bit Odd Parity Error Generator
In Multisim Design
A B C P
0 0 0 1
 3-bit Odd Parity Error Generator
In Multisim Design
A B C P
0 0 1 0
 3-bit Odd Parity Error Generator
In Multisim Design
A B C P
0 1 0 0
 3-bit Odd Parity Error Generator
In Multisim Design
A B C P
0 1 1 1
 3-bit Odd Parity Error Generator
In Multisim Design
A B C P
1 0 0 0
 3-bit Odd Parity Error Generator
In Multisim Design
A B C P
1 0 1 1
 3-bit Odd Parity Error Generator
In Multisim Design
A B C P
1 1 0 1
 3-bit Odd Parity Error Generator
In Multisim Design
A B C P
1 1 1 0
 4-bit Odd Parity Error
Truth Table Karnaugh Map
4 Bit Parity Error
A B C P E
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 0
1 0 0 0 0
1 0 0 1 1
1 0 1 0 1
1 0 1 1 0
1 1 0 0 1
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1
4-bit Odd Parity Error
Boolean Algebra Solution
 4-bit Odd Parity Error Generator
In Multisim Design

A B C P E
0 0 0 0 1
 4-bit Odd Parity Error Generator
In Multisim Design

A B C P E
0 0 0 1 0
 4-bit Odd Parity Error Generator
In Multisim Design

A B C P E
0 0 1 0 0
 4-bit Odd Parity Error Generator
In Multisim Design

A B C P E
0 0 1 1 1
 4-bit Odd Parity Error Generator
In Multisim Design

A B C P E
0 1 0 0 0
 4-bit Odd Parity Error Generator
In Multisim Design

A B C P E
0 1 0 1 1
 4-bit Odd Parity Error Generator
In Multisim Design

A B C P E
0 1 1 0 1
 4-bit Odd Parity Error Generator
In Multisim Design

A B C P E
0 1 1 1 0
 4-bit Odd Parity Error Generator
In Multisim Design

A B C P E
1 0 0 0 0
 4-bit Odd Parity Error Generator
In Multisim Design

A B C P E
1 0 0 1 1
 4-bit Odd Parity Error Generator
In Multisim Design

A B C P E
1 0 1 0 1
 4-bit Odd Parity Error Generator
In Multisim Design

A B C P E
1 0 1 1 0
 4-bit Odd Parity Error Generator
In Multisim Design

A B C P E
1 1 0 0 1
 4-bit Odd Parity Error Generator
In Multisim Design

A B C P E
1 1 0 1 0
 4-bit Odd Parity Error Generator
In Multisim Design

A B C P E
1 1 1 0 0
 4-bit Odd Parity Error Generator
In Multisim Design

A B C P E
1 1 1 1 1
 Conclusion
We get to the conclusion that a 3-bit odd parity error generator in this circuit is a circuit
created to generate an error each time a specific combination of inputs is present. Using the
multisim, we developed a 3-bit odd parity error generator. Additionally, we use an XOR and NOT
Gate to build the circuit's error generator, and the switch will decide based on a variety of digital
signals that enter its inputs. Additionally, we draw the conclusion that in the odd parity error
generator, the parity error is 1 if all 0s are present, 0 if only 1 is present, and 1 if there are two
1s. Last but not least, the led lights are turned on using the multisim application, and it is
dependent on the combination of binary code.
PICTURES OF THE GROUP WORKING TOGETHER
PICTURES OF THE GROUP WORKING TOGETHER