1) Explain various addressing modes and instruction

formats based on the number of address fields used

in the instruction format with an example.
Addressing Modes
The term addressing modes refers to how the operand of an instruction is
specified. The addressing mode specifies a rule for interpreting or modifying
the address field of the instruction before the operand is executed. The
different ways in which the location of an operand is specified in instruction are
referred to as addressing modes.

 Addressing Modes Definition

The addressing modes are used to specify the effective address in an
instruction. The effective address contains the object. The object can be a data
element or an address that must be evaluated in the instruction. The
addressing modes are divided into two:
• Sequential Control Flow Addressing Mode: Focuses on data.
• Transfer of Control Flow Addressing Mode: Focusses on instruction.

 Types of Addressing Modes

The addressing modes are categorized into two types: memory-based
addressing mode and transfer control addressing mode. The memory-based
addressing mode is further classified into different types that are as follows:

 Memory-Based Addressing Modes

• Implied Addressing Mode: In this mode, the operands are implicitly specified
in the instruction definition.
• Immediate Addressing Mode: In this mode, the operand is specified in the
instruction itself, or we can say that an immediate mode instruction has an
operand rather than an address.
Example: ADD R1, 5 adds the value 5 to the content of register R1.
• Register Addressing Mode: In this mode, one of the operands is in registers,
and the other is taken from memory.
Example: MOV R2, R3 copies the content of register R3 into register R2.
• Direct Addressing Mode: In this mode, the address of the memory location
that holds the operand is included in the instruction. The effective address is
the address part of the instruction.
Example: LOAD R1, 0x1000 loads the content from memory address 0x1000
into register R1.
• Indirect Addressing Mode: In this mode, the address field of the instruction
gives the address where the effective address is stored in memory.
Example: LOAD R1, [R2] loads the content from the memory address pointed to
by the content of register R2 into register R1.
• Relative Addressing Mode: In this mode, the content of the program counter
is added to the address part of the instruction to calculate the effective
address.
• Indexed Addressing Mode: In this mode, the effective address will be
calculated as the addition of the content of the index register and the address
part of the instruction.
Example: LOAD R1, [R2 + 4] loads the content from the memory address
obtained by adding 4 to the content of register R2 into register R1.

 Transfer Of Control Addressing Modes

• PC Relative Addressing Mode: This addressing mode is used to access the
instruction within the segment. Therefore only one offset address is required.
• Base register Addressing Mode: This addressing mode is used to access the
instructions between two segments. Therefore, a base address, as well as an
offset, is required.

Instruction Format
 What is an Instruction Format?
An instruction consists of bits, which are grouped up to make fields. Some
fields in instruction format are as follows
1. Opcode, which tells about the operation to be performed.
2. Address field designating a memory address or a processor register.
3. Mode field specifying how the operand or effective address is determined.

 Different Types of Instruction Formats

Some common types are three address instruction format, Two address
instruction format, One address instruction format, and Zero address
instruction format.

 Three Address Instruction Format

This system contains three address fields (address of operand1, address of
operand2 and address where the result needs to be put). The next instruction
address is held in a CPU register called Program Counter (PC).
ADD RESULT ADDRESS OP1 ADDRESS OP2 ADDRESS

Bits 8 24 24 24

Here, the number of bytes required to encode an instruction is 10 bytes.

Each address requires 24 bits = 3 bytes.
Since there are three addresses and one opcode field. Therefore 3 × 3 + 1 = 10
bytes.
The number of memory access required is 7 words.
4 words for instruction fetch, 2 words for operand fetch, and 1 word for the
result to be placed back in memory.

 Two Address Instruction Format

Two addresses and an operation field are there in this format. The result is
stored in either of the operand address, i.e., either an address of the first or
second operand's address. CPU register called Program Counter (PC) contains
the address of the next instruction.

ADD RESULT ADDRESS OP1 ADDRESS

BITS 8 24 24

 One Address Instruction Format

 One address field and an operation field. This address is of the first operand.
The second operand and the result are stored in a CPU register called
Accumulator Register (AR). Since a machine has only one accumulator, it
must not be explicitly mentioned in the instruction. A CPU register (i.e.,
Program Counter (PC) holds the address of the next instruction. In this
scenario, two additional instructions are required to load and store the
accumulator contents.

OP CODE

ADD RESULT ADDRESS

BITS 8 24

The number of bits required to encode an instruction is 4 bytes. i.e., each

address requires 24 bits = 3 bytes. Since there are one address and one
operation code field, 1* 3 + 1= 4 bytes.
The number of memory access required is 3 words, i.e., 2 words for instruction
fetch +1 word for code for operand fetch.

 Zero Address Instruction Format

Stack is included in the CPU for performing arithmetic and logic instructions
with no addresses. The operands are pushed onto the stack from memory, and
ALU operations are implicitly performed on the top elements of the stack. The
address of the next instruction is held in a CPU register called the program
counter.

ADD
BITS
8

e.g. ADD
Top of stack Top of stack + Second top of the stack
2) With flow chart explain the restoring and non-restoring
division operations on two decimal Numbers P and Q.

restoring division operation

 What is Restoring Division Algo ?

The Restoring Division Algorithm is a method used to perform division
operations on unsigned integers in computer arithmetic. It’s designed to
efficiently compute the quotient and remainder when dividing one
unsigned integer (dividend) by another (divisor), while also minimizing
the number of computational steps.
In this article, a restoring procedure for unsigned integers will be used.
The term "restoring" refers to the fact that after each repetition, the value
of register A is restored.

M A D D[0]

ADDER/SUBSTRACTOR

Register Q in this case holds the quotient, while register A holds the
remainder. Here, the divisor is loaded in M and the n-bit dividend is loaded
in D. The register whose value is restored after iteration and for which it is
named Restoring is initially held at 0.

 Flow Chart For Restoring Division Algo

 Step 1: Initiate the process by setting up the registers with their
corresponding values D=P and M=Q , where D represents the Dividend,
M denotes the Divisor, A starts at 0, and n signifies the number of bits
within the dividend.
 Step 2: Proceed by shifting the content of registers A and D to the
left, treating them as a unified unit.

 Step 3: Perform subtraction by deducting the content of register M

from A, and store the result back into A.

A0
MQ
D P
COUNT  n

Shift A,D

D[0] 1 D[0] 0
A  A+M

 Step 4: Examine the most significant bit of A. If it’s 0, set the least
significant bit of D to 1. Conversely, if the most significant bit is 1,
set the least significant bit of D to 0. Additionally, restore the value
of register A to its state before the subtraction with M.
  Step 5: Reduce the value of the counter n by one.

 Step 6: Check if the value of n has reached zero. If not, return to

step 2 and repeat the process.

 Step 7: Finally, the division process concludes with the quotient

residing in register D, while register A holds the remainder.

Non-restoring division operation

 What is the Non-Restoring Division Algo?
The Non-Restoring Division Algorithm is a method used to perform division
operations on unsigned integers without relying on restoring intermediate
remainders. It’s an iterative approach that approximates the quotient and
updates the remainder in each iteration, leading to an accurate division
result.

 Flow Chart for Non-Restoring Division Algo

 Step 1: Initialization involves loading pertinent values into
registers. Specifically, register A is initialized with 0, register M
holds the Divisor, register D retains the Dividend, and N designates
the number of bits in the dividend.

 Step 2: Proceeding to the next phase, we assess the sign bit of

register A.

 Step 3: Should this bit within register A be 1, we shift the A,D value
to the left and execute A = A + M. In contrast, if the bit is 0, we
again shift the A,D value leftward but perform A = A – M. In the
latter case, the 2’s complement of M is added to register A, and
the outcome replaces A.

 Step 4: A subsequent verification of the sign bit of A is carried out.

 Step 5: When the sign bit within register A is 1, D[0] is set to 0.

Conversely, if the bit is 0, D[0] is set to 1. Here, D[0] signifies the
least significant bit of D.
  Step 6: Afterward, N is decremented, acting as a counter in the
process.

 Step 7: If N equals 0, the progression advances to the ensuing step.

Otherwise, a return to step 2 is warranted.

A <- 0
M <- Q
D <- P
Count <- n

Shift A,D

D[0] <- 1 D[0] <- 1

A <- A+M
  Step 8: If the sign bit of register A is 1, we proceed with A = A + M.

 Step 9: Concluding the algorithm, in this final step, register A holds

the remainder, while register D embodies the quotient.

CONCLUSION
In conclusion, this report has provided a comprehensive overview of
addressing modes and instruction formats, showcasing how they vary
based on the number of address fields used in the instruction format.
Various examples were presented to illustrate each addressing mode's
characteristics and usage within computer architecture.

Furthermore, the report also delved into the division operations, specifically
restoring and non-restoring division, demonstrating the process through
flowcharts. These division methods were applied to two decimal numbers,
P and Q, offering a clear visual representation of the steps involved in
performing these arithmetic operations.