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LOGIC GATES

1. The output of an AND gate with 11. TTL operates from a ________.
three inputs, A, B, and C, is HIGH
when ________.
12. The output of a NOR gate is HIGH
if ________.
2. If a 3-input NOR gate has eight
input possibilities, how many of
those possibilities will result in a 13. The switching speed of CMOS is
HIGH output? now ________.

3. If a signal passing through a gate 14. The format used to present the
is inhibited by sending a LOW into logic output for the various
one of the inputs, and the output is combinations of logic inputs to a
HIGH, the gate is a(n): gate is called a(n):

4. A device used to display one or 15. The power dissipation, PD, of a


more digital signals so that they can logic gate is the product of the
be compared to expected timing ________.
diagrams for the signals is a:

16. A logic probe is again applied to


5. When used with an IC, what does the pins of a 7421 IC with the
the term "QUAD" indicate? following results. Is there a problem
with the circuit and if so, what is the
problem?
6. The output of an OR gate with
three inputs, A, B, and C, is LOW
when ________.

7. Which of the following logical


operations is represented by the +
sign in Boolean algebra? 17. If a 3-input AND gate has eight
input possibilities, how many of
those possibilities will result in a
8. Output will be a LOW for any case HIGH output?
when one or more inputs are zero for
a(n):
18. The Boolean expression for a 3-
input AND gate is ________.
9. How many pins does the 4049 IC
have?
19. A CMOS IC operating from a 3-
volt supply will consume ________.
10. Which of the following choices
meets the minimum requirement
needed to create specialized 20. What does the small bubble on
waveforms that are used in digital the output of the NAND gate logic
control and sequencing circuits? symbol mean?
21. What are the pin numbers of the 30. Which of the following gates has
outputs of the gates in a 7432 IC? the exact inverse output of the OR
gate for all possible input
combinations?
22. The output of a NOT gate is HIGH
when ________.
31. What is the difference between a
7400 and a 7411 IC?
23. If the input to a NOT gate is A and
the output is X, then ________.
32. Write the Boolean expression for
an inverter logic gate with
24. A logic probe is used to test the input C and output Y.
pins of a 7411 IC with the following
results. Is there a problem with the
chip and if so, what is the problem? 33. The output of an exclusive-OR
gate is HIGH if ________.

34. A clock signal with a period of


1  s is applied to the input of an
enable gate. The output must contain
six pulses. How long must the enable
pulse be active?
25. How many inputs of a four-input
AND gate must be HIGH in order for
the output of the logic gate to go 35. The AND function can be used to
HIGH? ________ and the OR function can be
used to ________ .

26. If the output of a three-input AND


gate must be a logic LOW, what must 36. One advantage TTL has over
the condition of the inputs be? CMOS is that TTL is ________.
37. A 2-input NOR gate is equivalent
to a ________.
27. Logically, the output of a NOR
gate would have the same Boolean
expression as a(n): 38. If a 3-input OR gate has eight
input possibilities, how many of
those possibilities will result in a
28. A logic probe is placed on the HIGH output?
output of a gate and the display
indicator is dim. A pulser is used on
each of the input terminals, but the 39. Fan-out is specified in terms of
output indication does not change. ________.
What is wrong?

40. How many input combinations


29. What is the Boolean expression would a truth table have for a six-
for a three-input AND gate? input AND gate?

41. What is the circuit number of the


IC that contains four two-input AND
gates in standard TTL?
42. The terms "low speed" and "high 54. The basic types of programmable
speed," applied to logic circuits, refer arrays are made up of ________.
to the ________.

55. The logic gate that will have HIGH


43. The NOR logic gate is the same or "1" at its output when any one (or
as the operation of the ________ gate more) of its inputs is HIGH is a(n):
with an inverter connected to the
output.
56. CMOS IC packages are available
in ________.
44. The logic expression for a NOR
gate is ________.
57. Which of the following is not a
basic Boolean operation?
45. With regard to an AND gate,
which statement is true?
58. Which of the following gates is
described by the
46. The term "hex inverter" refers to: expression  ?

47. How many inputs are on the logic 59. What is the Boolean expression
gates of a 74HC21 IC? for a four-input OR gate?

48. The basic logic gate whose 60. How many truth table entries are
output is the complement of the input necessary for a four-input circuit?
is the:

61. How many entries would a truth


49. When reading a Boolean table for a four-input NAND gate
expression, what does the word have?
"NOT" indicate?

62. The Boolean expression for a 3-


50. The output of an exclusive-NOR input OR gate is ________.
gate is HIGH if ________.

63. From the truth table for a three-


51. How many AND gates are found input NOR gate, what is the only
in a 7411 IC? condition of inputs A, B, and C that
will make the output X high?

52. Which of the following equations


would accurately describe a four- 64. The logic gate that will have a
input OR gate when A = 1, B = 1, C = LOW output when any one of its
0, and D = 0? inputs is HIGH is the:

53. What is the name of a digital 65. The output of a NAND gate is
circuit that produces several LOW if ________.
repetitive digital waveforms?
66. The gates in this figure are
implemented using TTL logic. If the 73. When does the output of a NAND
input of the inverter is open, and you gate = 1?
apply logic pulses to point B, the
output of the AND gate will be
________. 74. The number of input
combinations for a 4-input gate is
________.

75. When does the output of a NOR


gate = 0?
67. The gates in this figure are
implemented using TTL logic. If the
output of the inverter is open, and
you apply logic pulses to point B, the
output of the AND gate will be
________.

68. If A is LOW or B is LOW or BOTH


are LOW, then X is LOW. If A is HIGH
and B is HIGH, then X is HIGH. These
rules specify the operation of a(n)
________.

69. A major advantage of ECL logic


over TTL and CMOS is ________.

70. The output of an XOR gate is


HIGH only when ________.

71. A 2-input gate that can be used to


pass a digital waveform unchanged
at certain times and inverted at other
times is a(n) ________.

72. The gates in this figure are


implemented using TTL logic. If the
output of the inverter has an internal
open circuit, what voltage would you
expect to measure at the inverter's
output?
12. An OR gate output is HIGH only if
TRUE OR FALSE: all the inputs are HIGH.
13. A waveform can be enabled or
disabled by both AND and OR gates.
1. A truth table illustrates how the
input level of a gate responds to all
the possible output level 14. An exclusive-OR gate output is
combinations. HIGH when the inputs are unequal.

2. A NOR gate output is LOW if any 15. In a Boolean equation the use of
of its inputs is LOW. the + symbol represents the OR
function.
3. As a rule, CMOS has the lowest
power consumption of all IC families. 16. A logic gate has one or more
output terminals and one input
terminal.
4. A popular waveform generator is
the Johnson shift counter.
17. A logic pulser is used to
determine the level of floating in a
5. Good troubleshooting is done by circuit.
looking at the input signal and how it
interacts with the circuits.
18. An inverter output is the
complement of its input.
6. A NOR gate and an OR gate
operate in exactly the same way.
19. It is important to memorize logic
symbols, Boolean equations, and
7. An OR array is programmed by truth tables for logic gates.
blowing fuses to eliminate selected
variables from the output functions.

8. A NAND gate output is LOW only if


all the inputs are HIGH.

9. An AND gate output is LOW if all


the inputs are HIGH.

10. Power is connected to pins 7 and


14 of a 7408 quad two-input AND gate
IC to allow voltage for all four AND
gates on the IC.

11. An exclusive-NOR gate output is


HIGH when the inputs are unequal.

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