College Code: 4043

College Name: Sinhgad Academy of Engineering, Pune

Department of Computer Engineering
Class: SE Computer:
Subject: Digital Electronics and Logic Design
First 50 questions include UNIT 1 and UNIT 2
Sr.No Unit No. Question Option A
How many full adders are required to construct an m-bit
1 1 parallel adder ? m/2

Boolean
algebra and
Which of the following statements accurately represents Karnaugh
2 1 the two BEST methods of logic circuit simplification? mapping
3 1 Which gate is best used as a basic comparator? NOR
The digital multiplexer is basically a combination logic
4 1 circuit to perform the operation AND-AND

The output of a ____circuit at any instant of time is Combinatio

5 1 dependent only on the inputs present at that instant time. nal
Combinatio
6 1 Two bit comparator is------circuit. nal
7 1 The decoder circuit does not have the --input. Select
How many 3-line-to-8-line decoders are required for a
8 1 1-of-32 decoder? 1
How many data select lines are required for selecting
9 1 eight inputs? 1
10 1 The carry propagation can be expressed as ________. Cp =((A))B
When adding an even parity bit to the code 110010, the
11 1 result is 1110010
What is the function of an enable input on a multiplexer To apply
nine's-
12 1 binary
chip? code that progresses such that only one bit Vcc(+5V)
complement
difference of
13 1 changes between two successive codes is: code
the previous
14 1 The full adder adds the Kth bits of two numbers to the bits

15 1 The Ex-NOR is sometimes called the ________. parity gate

Reflective
16 1 Gray code is Code
8 half-
The number of full and half-adders required to add 16- adders, 8
17 1 bit numbers is full-adders
 to decode
18 1 The function of a multiplexer is information
Which of the following circuit can be used as parallel to
19 1 serial converter ? Multiplexer

20 1 The IC 74138 is a Multiplexer

21 1 A 32:1 multiplexer has ----number of select lines. 2
Perform the followling addition in 8-4-2-1 BCD (48) + 0001 0000
22 1 (58). 0010

EX-OR gate
23 1 The gates required to build a half adder are and OR gate
24 1 The number of inputs and outputs in a full adder are 2 and 1
25 1 IC 74153 is a 4:1 mux

tying all
enable pins
26 1 A decoder can be used as a demultiplexer by ________ LOW
An encoder in which the highest and lowest value input
digits are encoded simultaneously is known as a priority
27 1 encoder 0
Single looping in groups of three is a common K-map
28 1 simplification technique TRUE
The following combination is correct for an EVEN
parity data transmission system:data = 100111100 and
29 1 parity = 0 0
1 WITH
30 1 In binary subtrctor 0 - 1 = BORROW

31 1 The relation between n output lines and m select lines is 2m

sum= a (b
32 1 Sum output of full adder is Exor c in)
A full subtractor can be constructed using --- half
33 1 subtractor and ---- OR gate 1,1
34 1 for 16:1 mux if S3S2S1S0= 1011 then Y = D10
 OR gate and
Exclusive
35 1 DeMorgan’s first theorem shows the equivalence of OR gate.

The simplest equation which implements the K-map in

36 1 Figure 4-6 is:  X = AC+B
The binary value “1010110” is equivalent to decimal
37 1 __________ 86
A standard POS form has __________ terms that have
38 1 all the variables in the domain of the expression. Sum

39 1 The AND Gate performs a logical __________function Addition

All of the
inputs are
40 1 The output of an AND gate is one when ______ one
using
The systematic reduction of logic circuits is Boolean
41 1 accomplished by: algebra

All the
variables in
domain of
expression
42 1 A SOP expression is equal to ______________ are present
A non-standard POS is converted into a standard POS
43 1 by using the rule _____ A+A'=1
The binary numbers A = 1100 and B = 1001 are applied A > B = 1,
to the inputs of a comparator. What are the output A < B = 0,
44 1 levels? A<B=1
combination
45 1 Two bit comparator is------circuit. al
Two 16:1 and one 2:1 multiplexer can be connected to 16:1
46 1 form a ------ Multiplexer
Perform the followling addition in 8-4-2-1 BC((D)) (48) 0001 0000
47 1 + (58) 0010
The combinational circuit in BCD adder produces an
48 1 add command 6 if the carry is----- and sum is----- 0 , <9
49 1 Convert BCD 0001 0010 0110 to binary 1111110
data = 1101
________ is a correct combination for an ODD-parity 1011 parity
50 1 data transmission system =1
 when the
51 2 On a master-slave flip-flop, when is the master enabled? gate is LOW
Which table shows the logical state of a digital circuit
output for every possible combination of logical states Function
52 2 in the inputs ? table
A J-K flip-flop is in a "no change" condition when
53 2 ________. J = 1, K = 1
In sequential circuits the output states depends upon
54 2 ---------- past inputs

55 2 -----Flip flop can be used to provide delay in the circuts. SR

For JK flip flop with J=1, K=0, the output after clock
56 2 pulse will be 0
57 2 The output of SR flip flop when S=1, R=0 is 1

to reduce the
The preset and clear inputs are used in flip flop circuits power
58 2 ---- consumption
both the
59 2 Race around condition occurs in a JK FF when---- inputs are 0
AND and
60 2 latch is constructed using two cross-coupled OR gates
Use the Q
How can parallel data be taken out of a shift register output of the
61 2 simultaneously? first FF.
sequence of equally spaced timing pulses may be easily
62 2 generated by which type of counter circuit? ring shift
How many clock pulses will be required to completely
63 2 load serially a 5-bit 2
Past input
64 2 In Sequential circuit the output state depend upon State
65 2 How is a J-K flip-flop made to toggle? J=0 , K= 0
Sequetial circuit used for counting pulses is known as
66 2 ----- Register
On the fifth clock pulse, a 4-bit Johnson sequence is Q0 Q0 = 1, Q1
= 0, Q1 = 1, Q2 = 1, and Q3 = 1. On the sixth clock = 0, Q2 = 0,
67 2 pulse, the sequence is ________. Q3 = 0
What is a shift register that will accept a parallel input,
or a bidirectional serial load and internal shift features,
68 2 called? tristate
 A bidirectional 4-bit shift register is storing the nibble
1101. Its input is HIGH. The nibble 1011 is waiting to
be entered on the serial data-input line. After three clock
69 2 pulses, the shift register is storing ________. 1101
70 2 when a flip flop is set ,its output will be --------- Q=0
On the fifth clock pulse, a 4-bit Johnson sequence is Q0 Q0 = 1, Q1
= 0, Q1 = 1, Q2 = 1, and Q3 = 1. On the sixth clock = 0, Q2 = 0,
71 2 pulse, the sequence is ________. Q3 = 0
The bit sequence 0010 is serially entered (right-most bit
first) into a 4-bit parallel out shift register that is
initially clear. What are the Q outputs after two clock Q3Q2Q1Q0
72 2 pulses? =0000
On the third clock pulse, a 4-bit Johnson sequence is Q0 Q0 = 1, Q1
= 1, Q1 = 1, Q2 = 1, and Q3 = 0. On the fourth clock = 1, Q2 = 1,
73 2 pulse, the sequence is ________. Q3 = 1
A bidirectional 4-bit shift register is storing the nibble
1101. Its input is HIGH. The nibble 1011 is waiting to
be entered on the serial data-input line. After three clock Q3Q2Q1Q0
74 2 pulses, the shift register is storing ________. =1101
Use the Q
How can parallel data be taken out of a shift register output of the
75 2 simultaneously? first FF.

clearing all
To operate correctly, starting a ring shift counter the flip-
76 2 requires: flops
In a 6-bit Johnson counter sequence there are a total of
77 2 how many states, or bit patterns? 2
A modulus-12 ring counter requires a minimum of
78 2 ________. 10 flip-flops
The group of bits 11001 is serially shifted (right-most
bit first) into a 5-bit parallel output shift register with an
initial state 01110. After three clock pulses, the register Q4Q3Q2Q1
79 2 contains Q0=01110
Assume that a 4-bit serial in/serial out shift register is
initially clear. We wish to store the nibble 1100. What
will be the 4-bit pattern after the second clock pulse? Q3Q2Q1Q0
80 2 (Right-most bit first.) =1100
The bit sequence 10011100 is serially entered (right-
most bit first) into an 8-bit parallel out shift register that
is initially clear. What are the Q outputs after four clock
81 2 pulses? 10011100
If an 8-bit ring counter has an initial state 10111110,
82 2 what is the state after the fourth clock pulse? 11101011
 If a logic circuit does not contain any feedback loops, Combinatio
and the output is wholly dependent on the input, it is nal logic
83 2 called a circuit
84 2 A ring counter consisting of five Flip-Flops will have 5 states
The device which changes from serial data to parallel
85 2 data is COUNTER
In this logic, output depends not only on the current
inputs but also on the past input values. It needs some Logical
86 2 type of memory to remember the past input values Circuit
A _________________ is a circuit, which can
remember values for a long time or change values when Logical
87 2 require D Circuit
A ________________ circuit is not suitable in the
synchronous circuit design because of its transparency
88 2 nature. Latch

89 2 The different types of flip-flops are R-S

Up
It is a bi-directional counter capable of counting in Synchronou
90 2 either of the direction depending on the control signal s Counter
A MOD-16 ripple counter is holding the count 10012.
91 2 What will the count be after 31 clock pulses? 1000
The terminal count of a modulus-11 binary counter is
92 2 ________ 1010

Synchronous construction reduces the delay time of a all flip-flops

93 2 counter to the delay of: and gates

input clock
pulses are
applied only
to the first
Synchronous counters eliminate the delay problems and last
94 2 encountered with asynchronous counters because the: stages
A 4-bit ripple counter consists of flip-flops, which each
have a propagation delay from clock to Q output of 15
ns. For the counter to recycle from 1111 to 0000, it
95 2 takes a total of ________. 15 ns
 The counter
can count in
either
direction,
but must
continue in
that
Which of the following statements best describes the direction
96 2 operation of a synchronous up-/down-counter? once started.
parallel data
97 2 The parallel outputs of a counter circuit represent the: word
If T flip flop function is obtained from a JK flip flop,
98 2 if ........ J=K=1
In JK Flip - flop, when J = K = 1 and clock is applied,
99 2 the output Q will ....... not change
Both inputs of JK flip flop are tied high, the FF behaves
100 2 like ........ D Flip flop

accepts
101 2 An universal register ................... serial input
increase its
clocking
102 2 Master slave configuration is used in FF to .......... rate
In JK Flip - flop, when J = K = 1 and clock is applied,
103 2 the output Q will ....... not change

104 2 A mod 4 counter will count ....... From 0 - 4

The logic
level at the
D input is
transferred
to Q on
Which statement BEST describes the operation of a NGT of
105 2 negative-edge-triggered D flip-flop? CLK.
How many flip-flops are required to produce a divide-
106 2 by-128 device? 1

HIGHs are
applied
simultaneou
sly to both
An invalid condition in the operation of an active-HIGH inputs S and
107 2 input S-R latch occurs when ________ R
 To completely load and then unload an 8-bit register
108 2 requires how many clock pulses? 2
They must
Why are the S and R inputs of a gated flip-flop said to occur with
109 2 be synchronous? the gate.

a ring
counter has
fewer flip-
flops but
requires
more
comparison between ring and johnson counters decoding
110 2 indicates that: circuitry

Shifting the
data in all
flip-flops
simultaneou
111 2 What is meant by parallel-loading the register? sly

Mod-6 and mod-12 counters are most commonly used frequency

112 2 in: counters

The Q
output is
either SET
or RESET
as soon as
the D input
Which of the following is correct for a gated D-type goes HIGH
113 2 flip-flop? or LOW.
To overcome the difficulty of race around condition
114 2 which of the following flip flop is used Jk

The PLA
has a
programmab
le OR plane
and a
programmab
le AND
plane, while
the PAL
only has a
programmab
le AND
115 4 The difference between a PLA and a PAL is: plane.
 Array Logic
116 4 ALM is the acronym for ________. Matrix
117 4 PALs tend to execute ________ logic. SAP
Each programmable array logic (PAL) gate product is the polarity
applied to an OR gate and, if combinational logic is fuse is
118 4 desired, the product is ORed and then: restored
_______ are used at the inputs of PAL/GAL devices in
order to prevent input loading from a large number of Simplified
119 4 AND gates AND gates
A(n) ________ consists of a programmable array of
AND gates that connects to a fixed array of OR gates
120 4 and is usually OTP. GAL

What is another name for digital circuitry called logic

121 4 sequential logic? macrocell

More than
122 4 When did the first PLD appear? 10 years ago
SPLDs, CPLDs, and FPGAs are all which type of
123 4 device? PAL

What is the major downfall of microprocessor/DSP Speed—they

124 4 systems? are too fast
advanced
speed
integrated
125 4 ASIC stands for: circuit.
One PLD
does the
work of
126 4 Why have PLDs taken over so much of the market? many ICs.
The final step in the device programming sequence is
127 4 ________. Compiling
By adding an OR gate to a simple programmable logic
device (SPLD) the foundation for a(n) ________ is
128 4 made possible. PAL
Which one of the following is an embedded function of AND-OR
129 4 the Stratix II FPGA? logic
Field-programmable gate arrays (FGPAs) use ________ DRAM,
130 4 memory technology, which is ________. nonvolatile
10 inputs
and 8
131 4 A PAL16L8 has: outputs.
 Now many times can a GAL be erased and
132 4 reprogrammed? 0
A point that
is
What does a dot mean when placed on a PLD circuit programmab
133 4 diagram? le
Generic
134 4 GAL is an acronym for ________. Array Logic

135 4 What gives a GAL its flexibility? Its speed

a
programmab
le AND-OR
gate array
and some
136 4 A macrocell basically contains ________ input buffers
What programmable technology is used in FPGA
137 4 devices? SRAM

Flexible
Programmin
g [of]
Generic
138 4 FPGA is the acronym for ________. Assemblies
139 4 Which is not a type of PLD? SPLD
Which type of PLD could be used to program basic
140 4 logic functions? PLA
Product terms are the outputs of which type of gate
141 4 within a PLD array? OR

only two
142 4 A slice consists of ________. logic cells
143 4 What is PROM? SPLD
A unit of logic in an FPGA that is made up of multiple
smaller logic modules and a local programmer
interconnect that is used to connect internal logic
144 4 modules is called a ________. bed-of-nails
Most FPGA logic modules utilize a(n) ________
145 4 approach to create the desired logic functions. AND array

part of a
PAL or
146 4 A macrocell is ________ GAL
 standard
logic
147 4 Most complex digital designs include ________. devices
The programming technologies that are used in FPGA
devices include SRAM, flash, and antifuse, with
148 4 ________ being the most common. SRAM
lowest
speed,
Full custom ICs can operate at ________ and require largest die
149 4 the ________. area
Design costs for standard cell ASICs are ________
150 4 those for MPGAs. lower than
The ________ can generate any possible logic function
of the input variables because it generates every
151 4 possible AND product term. GAL
The distinction between CPLDs and FPGAs is
152 4 ________. well known

AND/OR
153 4 The flexibility of the GAL16V8 is in its ________. array
In a programmable logic device circuit diagram, the
inputs to each of the OR gates are designated by
154 4 ________ a dot
The SPLD classification includes the ________ PLD
155 4 devices. earliest
Four subcategories of ASIC devices are available to
create digital systems. These are PLDs, gate arrays,
156 4 standard cells, and ________. HCPLDs
Permanent
Read Only
157 4 PROM stands for Memory
portable
158 4 PLD stands for large device
non volatile
159 4 ROM is a memory

Electrical
Programmab
le Read
Only
160 4 EPROM stands for Memory

161 4 In a ROM each bit combination input variable is called cell

 An integrated circuits with internal logic gates A. portable
162 4 connected through electronic fuses is called large device
163 4 Blowing of fuses are referred to as ROM's memory

portable
164 4 PAL stands for array logic
sum of
165 4 ROM is a two level implementation in maxterms
 What do the Programmable Logic Devices (PLDs)
designed specially for the combinational circuits
166 4 comprise? Only gates
Which among the following statement/s is/are not
an/the advantage/s of Programmable Logic Devices Short design
167 4 (PLDs)? cycle
What is/are the configurable functions of each and
every IOBs connected around the FPGA device from Input
168 4 the operational point of view? operation
Which type of CPLD packaging can provide maximum
number of pins on the package due to small size of the
169 4 pins? PLCC

How many logic gates can be implemented in the circuit

170 4 by complex programmable logic devices (CPLDs)? 10
 If the number of nichrome fuse links in PAL are equal Number of
171 4 to 2M xn, then what does 'n' represent in it? inputs
Which among the following are used in programming Input
172 4 array logic (PAL) for reducing the loading on inputs? buffers
173 3 ASM charts resembles to--- map
174 3 state box without decision and conditional box is--- asm block
command
175 3 Control information gives knowledge about the signals
176 3 ASM chart has 4 exits
177 3 Number of basic notations of an ASM are-- 1

178 3 A rectangular box in ASM is ----box state

179 3 ASM chart is composed of--- 2 elements
180 3 Sate box of ASM chart represents---- condition
181 3 Logic desgin consists of --- 1 part
182 3 No of inputs and outputs in a state table are-- equal
183 3 Signal that starts operation is indicated by -- INITIAL
184 3 In VHDL, the mode of a port does not define -- an input
which VHDL data type can only have a value of '1' and
185 3 '0' signal
 synthesis
and
simulation
186 3 VHDL can be used for -- only
which is of the following statements is not a concurrent
187 3 statement if statement

188 3 which is symbol used for signal assignment ? <=

189 3 __type is the group of elements of same type? Array

which statement is used to JUMP out of loop statement
190 3 currently in execution? EXIT
CONSTAN
191 3 ____type of object can have values TRUE and FALSE T
Onlu
192 3 Which are the possible modes of a port? IN,OUT
____declaration specifies only the outer description of a
193 3 circuit? Entity
194 3 In VHDL a digital system is modeled as___ module
195 3 STD_LOGIC_1164 is a __in a VHDL IEEE library module

196 3 the PROCESS statement itself is a concurrent

what is used to bind ta component instance to an entity configuration

197 3 architecture pair? declaration

198 3 In a dataflow modeling statements are executed sequentialy

199 3 The signal written in parenthesis after keyword PROCESS is variable

wait until
time
200 3 which is an invalid form of wait? expression
Option B Option C Option D Marks Correct Option
m 1
m-1 m+1 C
Actual circuit 1
Karnaugh trial and error
mapping and evaluation and Boolean algebra
circuit waveform and actual
waveform analysis circuit trial and
analysis error evaluation A
OR Ex-OR AND 1 C

OR-OR AND-OR OR-AND 1 A

Combinational
sequential and sequential None 1 A

sequential FF None 1 A
data Control Strobe 1 B

2 4 8 1 C

2 3 4 1 C
Cp=A+B Cp =A+B' Cp=A'+B 2 B

1111001 1111001 1101 1 C

to connect to active the to active one
ground entire chip half of the chip 1 C
8421 code
sum of all excess-3
carry from ( K - Gray
code sum ofcode
previous 2 D
previous bits 1 )TH bit bit 1 C

parity gate or
equality gate inverted OR the equality gate 1 B
Non-Weighted
Cyclic Code code All of these 1 D

1 half-adder, 16 half-adders, 0 4 half-adders,

15 full-adders full-adders 12 full-adders 2 B
to select 1 out
of N input
data sources
and to to perform serial
transmit it to to transit data on to parallel
single channel N lines conversion 1 B

Demultiplexer Decoder Digital counter 2 A

Demultiplexer BCD adder Comparator 1 B

3 4 5 1 D
0110 0000
0001 0001 0000 0110 0001 0000 0101 2 C

EX-OR gate EX-OR gate and EX-OR gate and

and NOR gate AND gate NAND gate 1 C
1 and 2 3 and 1 2 and 2 1 C
8:1 mux 16:1 mux dual4:1 mux 1 D

using the input

lines for data
tying all data- tying all data- selection and an
select lines select lines enable line for
LOW HIGH data input 1 D

0 1 B

0 1 B

0 2 B

0 1 10 1 A

log2 m log2 n log m 1 A

sum= a Exor sum= a Exor c
b Exor c in sum= b Exor c in in 2 B

2,2 1,2 2,1 2 D

D11 D12 D13 1 B
NOR gate and
Bubbled NOR gate and NAND gate and
AND gate. NAND gate. NOT gate 1 B

X=
ABC'+ABC+AB'
X= AB'X C NONE 1 A

87 67 55 1 A

Product Min Composite 1 A

Subtraction Multiplication Division 1 C

Any of the Any of the input All the inputs

input is one is zero are zero 1 A

symbolic using a truth

reduction TTL logic table 1 A

At least one When one or When one or

variable in more product more product
domain of terms in the terms in the
expression is expression are expression are
present. equal to 0. equal to 1. 1 D

((A))A'=0 1+A=1 A+B=B+A 1 B

A > B = 0, A A > B = 0, A <
< B = 1, A = A > B = 1, A < B = 1, A = B =
B=0 B = 0, A = B = 0 1 2 C

sequential FF NONE 1 A
32:1
Multiplexer 8:1 Multiplexer 64:1 Multiplexer 2 B
0110 0000
0001 0001 0000 0110 0001 0000 0101 2 C

1,>9 1 , =9 1, < 9 2 B
11110 1110010 1111111 1 A
data = 1101
0010 parity = data = 0001 data = 0001
0 0101 parity = 1 0101parity = 1 2 A
 when the gate both of the neither of the
is HIGH above above 1 A

Truth table Routing table ASCII table 1 B

J = 1, K = 0 J = 0, K = 1 J = 0, K = 0 1 D
Present as well
present inputs None as past inputs 1 D

D T JK 1 B

1 high impedance. no change. 1 B

0 high impedance. no change. 1 A

to increse to set the initial for

speed conditions sychronization 1 C
both the inputs are any condtion is
inputs are 1 complementry present 1 B

AND Exor gates NAND gate 1 D

Use the Q Use the Q
output of the Tie all of the Q output of each
last FF. outputs together. FF. 1 D

CLOCK Johnson Binary 1 A

3 4 5 1 D
Present input Present as well
State as Past input None of Above 1 C
J=0 , K=1 J=1 , K=0 J=1 , K=1 1 D

Counter Flip flop NONE 1 B

Q0 = 1, Q1 =
1, Q2 = 1, Q3 Q0 = 0, Q1 = 0, Q0 = 0, Q1 = 0,
=0 Q2 = 1, Q3 = 1 Q2 = 0, Q3 = 1 2 C

end around universal conversion 1 C

 111 1 1110 2 C
Q=1 Q=00 NONE 2 B
Q0 = 1, Q1 =
1, Q2 = 1, Q3 Q0 = 0, Q1 = 0, Q0 = 0, Q1 = 0,
=0 Q2 = 1, Q3 = 1 Q2 = 0, Q3 = 1 2 C

Q3Q2Q1Q0= Q3Q2Q1Q0=100 Q3Q2Q1Q0=11

0010 0 11 2 C
Q0 = 1, Q1 =
1, Q2 = 0, Q3 Q0 = 1, Q1 = 0, Q0 = 0, Q1 = 0,
=0 Q2 = 0, Q3 = 0 Q2 = 0, Q3 = 0 2 A

Q3Q2Q1Q0= Q3Q2Q1Q0=000 Q3Q2Q1Q0=11

0111 1 10 2 B
Use the Q Use the Q
output of the Tie all of the Q output of each
last FF. outputs together. FF. 2 D
presetting one clearing one
flip-flop and flip-flop and
clearing all presetting all presetting all the
others others flip-flops 2 B

6 12 24 1 C

12 flip-flops 6 flip-flops 2 flip-flops 1 B

Q4Q3Q2Q1Q Q4Q3Q2Q1Q0= Q4Q3Q2Q1Q0=

0=00001 00101 00110 2 C

Q3Q2Q1Q0= Q3Q2Q1Q0=000 Q3Q2Q1Q0=11

0011 0 11 2 C

11000000 10001100 11110000 2 A

11001011 11110000 All Zeros 2 D

Sequential Delay logic
logic circuit circuit ADDER 2 B
10 states 32 states Infinite states. 1 A
MULTIPLEX DEMULTIPLEX
ER ER FLIP-FLOP 1 C

Connected Sequential
Circuit Circuit Parallel Circuit 1 C

Digital Circuit Memory Element Complex Circuit 1 C

None of the
Parallel Diagonal Circuit above 1 A

D,T J-K All of the above 1 D

Down
Synchronous Synchronous
Counter Counter Both A and B 1 C

1010 1011 1101 1 A

1000 1001 1100 1 A

all flip-flops
and gates a single flip-flop
after a 3 count a single gate and a gate 1 D

input clock input clock input clock

pulses are pulses are not pulses are
applied only used to activate applied
to the last any of the simultaneously
stage counter stages to each stage 1 D

30 ns 45 ns 60 ns 1 D
The counter The count
can be sequence cannot
reversed, but In general, the be reversed,
must be reset counter can be once it has
before reversed at any begun, without
counting in point in its first resetting
the other counting the counter to
direction. sequence. zero. 2 C
clock
frequency counter modulus clock count 1 D
None of the
J = K =0 J =1 and K =0 above 1 A

become 0 become 1 race condition 1 D

None of the
SR Flip flop T Flip flop above 1 C

accepts gives serial and is capable of all

parallel output parallel output the above 2 D

reduce power eleminate race improve its

dissipation around condition reliability 1 C

become 0 become 1 race condition 2 D

None of the
0-5 0-3 above 2 C

The Q output
is ALWAYS The Q output is
identical to ALWAYS The Q output is
the CLK input identical to the D ALWAYS
if the D input input when CLK identical to the
is HIGH. = PGT. D input. 2 A

4 6 7 1 D

LOWs are
applied a LOW is a HIGH is
simultaneousl applied to the S applied to the S
y to both input while a input while a
inputs S and HIGH is applied LOW is applied
R to the R input to the R 1 A
 4 8 16 1 D
They occur
independent None of the
of the gate. All of the above above 1 A

a johnson
a ring counter counter has more a johnson
has an flip-flops but less counter has an
inverted decoding inverted
feedback path circuitry feedback path 1 D

Momentarily
disabling the
Loading data Loading data in synchronous
in two of the all four flip-flops SET and
flip-flops at the same time RESET inputs 1 C
power
multiplexed consumption
displays digital clocks meters 1 C

The output
complement The output
follows the Only one of the toggles if one of
input when inputs can be the inputs is
enable((D)) HIGH at a time. held HIGH 1 A

Sr D Master salve 1 D

The PAL has

a
programmabl
e OR plane
and a
programmabl
e AND plane,
while the
PLA only has The PAL has
a more possible PALs and
programmabl product terms PLAs are the
e AND plane. than the PLA. same thing. 2 A
Arithmetic Asynchronous Adaptive Logic
Logic Module Local Modulator Module 1 D
SOP PLA SPD 1 B
sent to an sent passed to the
inverter for immediately to AND function
output an output pin for output 1 B

Fuses Buffers Latches 1 C

CPLD PAL SPLD 1 C

flip-flop memory
logic array circuitry Inverter 1 C

More than 20 More than 30 More than 40

years ago years ago years ago 1 C

PLD EPROM SRAM 1 B

Speed—they Too much Not enough

are too slow flexibility flexibility 1 B
advanced application
standard application speedy
integrated specific integrated
circuit. integrated circuit. circuit. 1 C

The PLDs are Less power is

cheaper. required. All of the above 1 D

downloading simulation synthesis 1 B

PLA CPLD EEPROM 1 A

Programmabl Digital signal None of the
e SOP processing above 1 C
SRAM,
nonvolatile SRAM, volatile RAM, volatile 2 C

8 inputs and 16 inputs and 16 16 inputs and 8

8 outputs. outputs. outputs. 1 A
At least 100 At least 1000 Over 10,000 1 B

A point that An intersection An input or

cannot change of logic blocks output point 1 B
General Array Giant Array Generic
Logic Logic Analysis Logic 1 A
Its Its
reprogramma Its large logic programmable
ble EPROM arrays OLMCs 1 D

an OR-gate
array and an AND-OR gate
some output array and some licensed
logic output logic programming 1 B

FLASH Antifuse All of the above 1 D

Field
Programmabl Field Field
e Generic Programmable Programmer's
Array Gate Array Gate Assembly 1 C
HPLD CPLD FPGA 1 B

PAL CPLD all the above 1 D

XOR AND flip-flop 1 C

between 2 and up to 16 logic

8 logic cells cells a single CLB 1 A
QPLD HPLD PLD 1 D

boundary scan CLB CPLD 1 C

AND and OR
Look-up table OR array array 1 B
a type of one-
time an example of
programmabl intellectual a logic array
e SPLD property block 1 A
 a mix of
different
microprocessor/ hardware
ASIC devices DSP devices categories 1 D

flash antifuse SRAM and flash 1 A

lowest speed,
smallest die highest speed, highest speed,
area largest die area smallest die area 1 D
about the none of the
same as higher than above 1 C

SOP PROM LAB 1 C

very small often fuzzy very large 1 C

programmable
output logic
D flip-flops macro cells EEPROM 1 C

a bus a single line 4 inputs 1 C

smallest largest newest 1 A

full custom GAL FPLDs 1 B

Programmable
Portable Read Read Only D. Plugin Read
Only Memory Memory Only Memory 1 C
portable logic programmable programmable
device large device logic device 1 D
A. secondary
memory volatile memory small memory 1 A

Erasable
Electrical Programmable D. Erasable
Portable Read Read Only Portable Read
Only Memory Memory Only Memory 1 C

block address memory 1 C

 A.
portable logic programmable programmable
device large device logic device 1 D
cells blocks programming 2 D
programmabl
e advanced programmable portable
logic array logic advanced logic 1 C
sum of product of product of
minterms maxterms minterms 1 C

Only flip None of the

flops Both a and b above 1 A
Increased
space Increased
requirement switching speed All of the above 1 B
Tristate
output Bi-directional
operation I/O pin access All of the above 1 D

QFP BGA PGA 1 C

100 1000 10000 1 D

Number of Number of Number of
arrays outputs product terms 1 D
Output
buffers OR matrix AND matrix 1 A
data flowchart operation 1 C
defined block simple block Both A and B 1 C

data metadata operation 1 A

3 exits 2 exits any no exits 1 D
2 3 4 1 C
conditional None of the
decision output above 1 A
3 elements 4 elements 5 elements 1 B
clock state pulse 1 C
2 parts 3 parts 4 parts 1 B
same unequal not present 1 A
GO BEGIN START 1 D
an output Both a and b the type of bit 1 D

std_logic bit integer 1 C

 Synthesis ans
documentatio
n programing None 1 A
signal condtional signal selected signal
assignment assignment assignment 1 D
both of the
:= above None 1 A
None of the
Record Both a and b above 1 A

NEXT LOOP END 1 A

None of the
BOOLEAN VARIABLE above 2 B
IN, OUT,
INOUT CLK None 2 B

Architecture Package Attribute 1 A

entity process All of the above 1 D
package function procedure 2 B
None of the
sequential data flow above 1 A

Identifier port map sensitivity list 1 A

None of the
concurrently Both a and b above 1 B

constant sensitivity list none 1 C

wait on signal wait for condtion Both A and C 2 D