DELD All Units MCQ

S.
r No Question A B C D Answer Marks

1 A standard SOP form hasterms that have all the variables in the SUM SUB Mult DIV A 1
domain of the expression.
2 A small dot or circle printed on top of an ICindicates Vcc Gnd Pin 14 D 1
Pin 1
3 What logic function is produced by adding an inverter to the output NAND NOR XOR OR A 1
of an AND gate ?
4 Route the data from Select data from A 1
single several inputs and
input to one of many route it to single
outputs output Perform serial to
parallel conversion
A demultiplexer is used to All of these
5 How many full adders are required to construct an m-bit parallel m-1 m m+1 B 1
adder ?
m/ 2
6 combinational logic circuits
sequential logic circuits
both (a) and (b) None of these B 1
Parallel adders are
7 What is the largest number of data inputs which a data selector with 2 4 6 8 B 1
two control inputs can have ?
8 If a logic gates has four inputs, then total number of possible input 4 8 16 32 C 1
combinations is
9 A combinational logic circuit which generates a particular binary Decoder Multiplexer Encoder A 1
word or number is Demultiple xer
10 Cyclic Self- complementi ng code
Algebraic code. C 1
Weighted code redundancy code
Excess-3 code is known as
11 How many inputs are required for a 1-of-10 BCD decoder? 4 8 10 1 A 1
12 decimal to hexadecimalsingle input, odd parity B 1
Most demultiplexers facilitate which of the following? multiple outputs ac to dc to even parity
13 code conversion parity checking parallel-to- serial data data generation C 1
One application of a digital multiplexer is to facilitate: conversion
14 accepts data B 1
inputs from several
lines and multiplexe
accepts data inputs accepts data inputs s this
from one line and uses one display to from multiple input data to four
passes this data to present two lines and passes this BCD lines
multiple output lines or more pieces of data to multiple
output lines
information
A multiplexed display:
15 In which of the following gates, the output is 1, if and only if at least NOR AND OR NAND C 1
one
input is 1?
16 Odd parity of word can beconveniently tested by OR gate AND gate NOR gate XOR gate D 1
17 Which one of the following will give the sum of full adders as outputThree point majority circuit
Three bit Three bit comparator Three bit counter D 1
? parity checker
18 1 half-adder, 16 half- adders, 0 full- adders
4 half- B 1
The number of full and half-adders required to add 16-bit numbers is 8 half-adders, 15 full- adders adders, 12 full-
8 full-adders adders
19 The t ime required for a pulse to decrease from 90 to 10 per cent of Binary level transition Propagatio n delay B 1
its maximum value is called Rise t ime Decay t ime period
20 Which of the following gates would output 1 when one input is 1 and D 1
other input is 0 ? OR gate AND gate NAND gate AND gate
21 Which of the following expressions is not equivalent to X ' ? X NAND X X NOR X X NAND 1 X NOR 1 D 1
22 Which of the following gates are added to the inputs of the OR gate NOT AND OR XOR A 1
to convert it to the NAND gate ?
23 The EXCLUSIVE NOR gate is equivalent to which gate followed by OR gate AND NAND XOR D 1
an
inverter ?
24 A one-to-four line demultiplexer is to be implemented using a 1 BIT 2 BITS 4 BITS 8 BITS A 1
memory.
How many bits must each word have ?
25 What logic function is produced by adding an inverter to the output NAND NOR XOR OR A 1
of an AND gate ?
26 Which of the following gates is known as coincidence detector ? AND GATE OR GATE NOT GATE NAND A 1
GATE
27 Which table shows the logical state of a digital circuit output for B 1
every possible combination of logical states in the inputs ? Function table Truth table Routing table ASCII table
28 A positive AND gate is also a negative NAND gate NOR gate AND GATE OR GATE D 1
29 Select data from A 1
Route the data from several inputs and Perform serial to
single route it to single parallel conversion
input to one of many output
A demultiplexer is used to outputs All of these
30 Sw itches connected inSw
series
itches connected MOS
in parallel B 1
transistors connected None of these
in series
An OR gate can be imagined as
31 Which combination of gates does not allow the implementation of an OR gates and exclusive
OROR
gates
gate
and
only
NOT gates only A 1
arbitrary boolean function? OR gates and AND NAND
gates only gates only
32 combinational logic circuits
sequential logic circuits
both (a) and (b) None of these A 1
Parallel adders are
33 The digital multiplexer is basically a combination logic circuit to AND-AND OR-OR AND-OR OR-AND C 1
perform
the operation
34 Low if all of its inputs High
are low
if all of its inputs High if only of its C 1
High if all of its are inputs is
The output of NOR gate is inputs are high low low
35 How many lines the truth table for a four-input NOR gate would 4 8 12 16 D 1
contain
to cover all possible input combinations ?
36 A toggle operation cannot be performed using a single NOR gate AND gate NAND gate XOR gate B 1
37 Which table shows the electrical state of a digital circuit's output for A 1
every possible combination of electrical states in the inputs ? Function table Truth table Routing table ASCII table
38 What is the minimum number of 2 input NAND gates required to 6 5 4 3 C 1
implement the function
F = (x'+y') (z+w)
39 How many truth tables can be made from one function table ? One Two Three Any B 1
numbers
40 operates at the same A 1
speed as parallel is more complicate
A comparison between serial and parallel adder reveals that serial is slower is faster adder d
order
41 What is the largest number of data inputs which a data selector with 2 4 8 16 B 1
two
control inputs can have ?
42 If a logic gates has four inputs, then total number of possible input 4 8 16 32 C 1
combinations is
43 input combination at A 1
input combination that t ime present output and
and the previous and the previous input the previous output
input combination at
the t ime output combination
A combinational circuit is one in which the output depends on the
44 to select 1 out of N B 1
input data sources to perform serial to
and to transmit it to parallel
single to transit data on N
to decode lines conversion
channel
The function of a multiplexer is information
45 A combinational logic circuit which generates a particular binary Decoder Multiplexer Encoder Demultiple A 1
word
or number is
xer
46 Which of the following circuit can be used as parallel to serial Multiplexer Demultiplexe Decoder Digital A 1
converter ?
r counter
47 Car ry- look- ahead C 1
In which of the following adder circuits, the carry look r ipple delay is Parallel adder adder
eliminated ? Half adder Full adder
48 Adders Is called so A 1
because a full needs two input and
adder generates two output
involves two half-
adds 2 bits adders All of these
49 How many 3-line-to-8-line decoders are required for a 1-of-32 1 2 4 8 C 1
decoder?
50 For the device shown here, let all D inputs be LOW, both Sinputs be LOW Cannot be A 1
HIGH, and the input be LOW. What is the status of the Y output? HIGH Don't Car e determine
d
51 How many data select lines are required for selecting eight inputs? 1 2 3 4 C 1
52 How many 1-of-16 decoders are required for decoding a 7-bit binary 5 6 7 8 D 1
number?
53 The implementation of simplified sum-of-products expressions may NAND NOR B 1
be easily implemented into actual logic circuits using all universal
gates with lit t le or no increase in circuit complexity. (Select the
response for the blank space that will BEST make the statement AND/ OR OR/ AND
true.)
54 Actual Boolean algebra A 1
circuit tr ial and error and actual circuit
tr ial and error
Boolean algebra and Karnaugh mapping evaluation and evaluation
Karnaugh mapping and circuit waveform analysis
waveform analysis
Which of the following statements accurately represents the two
BEST methods of logic circuit simplification?
55 Which gate is best used as a basic comparator? NOR OR Exclusive-OR AND C 1
56 For the device shown here, assume the D input is LOW, both All but are LOW. All but are HIGH. A 1
Sinputs are HIGH, and the input is HIGH. What is the status of the All are HIGH. All are LOW.
outputs?
57 The maximum A 1
number of gates
that any signal must
All logic circuits are No signal must pass pass through is
reduced to The delay t imes through more than two reduced by a factor
nothing more than are greatly gates, not of two.
simple AND and OR reduced over other including inverters.
Which of the following is an important feature of the sum-of-products operations. forms.
form of expressions?
58 An output gate is connected to four input gates; the circuit does not Oscilloscope A 1
function. Preliminary tests with the DMM indicate that the power is
applied; scope tests show that the primary input gate has a pulsing
signal, while the interconnecting node has no signal. The four load Logic analyzer
gates are all on different ICs. Which instrument will best help isolate Cur rent tracer Logic probe
the
problem?
59 The dim indication A 1
on the logic probe
indicates that the
supply voltage is The dim
probably indication is a result of
a bad ground
A logic probe is placed on the output of a gate and the display The output of the low. connection on the The gate may be a
indicator is dim. A pulser is used on each of the input terminals, but gate appears to be logic probe. tr istate device.
the output open.
indication does not change. What is wrong?
60 a DON'T CARE A 1
condition for all
possible
a HIGH for each a HIGH
input truth table output on the truth input
a LOW truth table
condition that table for all LOW output for all possible combinati ons.
produces a HIGH input combination HIGH input conditions.
Each "1" entry in a K-map square represents: output. s.
61 There is a signal D 1
loss to all gates on
the node, and the
affected node will
be stuck in the
LOW state.
Only the output of There is a signal The affected node will
the defective gate loss to all gates on be stuck in the LOW
is affected. the node. state.
What is the indication of a short on the input of a load gate?
62 Which of the following expressions is in the sum-of-products form? (A + B )(C + D ) (AB )(CD ) AB (CD ) AB + CD D 1
63 using the input lines D 1
for data selection
and an enable
line for
tying all enable pins tying all data-select tying all data- select data input
A decoder can be used as a demultiplexer by. LOW lines LOW lines HIGH
64 How many 4-bit parallel adders would be required to add two binary 1 2 3 4 C 1
numbers each representing decimal numbers up through 30010?
65 Karnaugh maps D 1
The Karnaugh provide a visual
approach to
map Variable complements simplifyin g Boolean
A Karnaugh map can eliminates the need can be expression
be used to for using NAND eliminated by using
and NOR gates. Karnaugh maps. s.
replace Boolean
Which statement below best describes a Karnaugh map? rules.
66 A certain BCD-t o-decimal decoder has active-HIGH inputs and 0 3 9 None. All outputs C 1
active- LOW outputs. Which output goes LOW when the inputs are are HIGH.
1001?
67 A full-adder has a Ci n = 0. What are the sum and the carry (Cout ) = 0, Cout = 0 = 0, Cout = 1 = 1, Cout = 1, B 1
when A =0 Cout = 1
= 1 and B = 1?
68 When adding an even parity bit to the code 110010, the result is. 1110010 110010 1111001 1101 A 1
69 One 4-input AND gate,
Oneone4-input
OR gateNAND gate,One
one4-
inverter D 1
Which of the following combinations of logic gates can decode One 4-input AND input AND gate,
binary 1101? gate one inverter
70 The affected node B 1
The node may be will be stuck in the
stuck in either the HIGH
Only the output of There is a signal
the defective gate loss to HIGH or the LOW state.
What is the indication of a short to ground in the output of a driving state.
gate? is affected. all load gates.
71 How many outputs would two 8-line-to-3-line encoders, expanded to 3 4 5 6 B 1
a
16-line-to-4-line encoder, have?
72 carry in carry out two inputs all of the A 1
A half-adder does not have. above
73 data = 1101 1011 data = 1101 0010 data = 0001 0101 data = 1010 1111 A 1
is a correct combination for an ODD-parity data transmission parity = 1 parity = 0 parity
system. =1 parity = 0
74 A circuit that can convert one of ten numerical keys pressed on a priority decoder multiplexer demultiple A 1
keyboard to BCD is a. encoder xer
75 Theprefix on IC's indicates a broader operating temperature range, 54 2N 74 A 1
and the devices are generally used by the military. TTL
76 The largest truth table that can be implemented directly with an 8- 3 rows 4 rows 8 rows 16 rows C 1
line-
to-1-line MUX has.
77 when a binary B 1
counter counts
which of two errors in binary errors in arithmetic in incorrectly
Parity generation and checking is used to detect. numbers is greater data computers
transmission
78 Except for, STD_LOGIC may have the following values. 'z' 'U' '?' 'L' C 1
79 A gate that could be used to compare two logic levels and provide a XOR gate XNOR gate NAND gate NOR gate B 1
HIGH
output if they are equal is a(n).
80 The AND-OR-INVERT gates are designed to simplify POSlogic DeMorgan's NAND logic SOP logic B 1
implementation of
.
theorem
81 show A 1
whether the gate is probably not be able be able to identify
identify the defective shorted to to locate the problem the defective load
gate V cc or ground node
The output of a gate has an internal short; a current tracer will.
82 Parity generators and checkers usegates. exclusive-AND exclusive- exclusive-OR exclusive- B 1
OR/ NOR NAND
83 test the display to A 1
assure all segments
are
turn off the display turn off the display turn off the display for
for any for any zero leading or operationa
The 7447A is a BCD-t o-7-segment decoder with r ipple blanking
input and output functions. The purpose of these lines is to. nonsignificant trailing zeros l
digit
84 One reason for using the sum-of-products form is that it can be NOR NAND AND DOOR B 1
implemented using allgates without much difficulty.
85 to the cascading ground A 1
inputs of the least
significant 4- bit
Two 4-bit comparators are cascaded to form an 8-bit comparator. to the outputs from A = B to a logic high,
The cascading inputs of the most significant 4 bits should be the least significant comparator A
connected 4- bit comparator < b and a > B to a
. logic low
86 When Karnaugh mapping, we must be sure to use thenumber of maximum minimum median Karnaugh B 1
loops.
87 After each circuit in a subsection of a VHDL program has been, designed tested engineered produced B 1
they can be combined and the subsection can be tested.
88 When grouping cells within a K-map, the cells must be combined in 2's 1, 2, 4, 8, etc. 4's 3's B 1
groups of.
89 Thecircuit produces a HIGH output whenever the two inputs are exclusive-AND exclusive- exclusive-OR inexclusive C 1
unequal. NOR -OR
90 The carry output of each adder in a r ipple adder provides an TRUE FALSE None of the Can not A 1
additional above predict
sum output bit.
91 Truth tables are great for listing all possible combinations of TRUE FALSE None of the Can not A 1
independent variables. above predict
92 A square in the top row of a K-map is considered to be adjacent to TRUE FALSE None of the Can not A 1
its above predict
corresponding square in the bottom row.
93 To implement the full-adder sum functions, two exclusive-OR gates TRUE FALSE None of the Can not A 1
can above predict
be used.
94 TTL stands for transistor-technology-logic. TRUE FALSE None of the Can not B 1
above predict
95 The following combination is correct for an ODD parity data TRUE FALSE None of the Can not A 1
transmission system: data = 011011100 and parity = 0 above predict
96 The XOR gate will produce a HIGH output if only one but not both of TRUE FALSE None of the Can not A 1
the above predict
inputs is HIGH.
97 When decisions demand one of many possible actions, the ELSIF TRUE FALSE None of the Can not A 1
control above predict
structure is used.
98 The K-map provides a "graphical" approach to simplifying sum-of- TRUE FALSE None of the Can not A 1
products expressions. above predict
99 Even parity is the condition of having an even number of 1s in every TRUE FALSE None of the Can not A 1
group of bits. above predict
100 The look-ahead carry method suffers from propagation delays. TRUE FALSE None of the Can not B 1
above predict
101 A pull-up resistor is a resistor used to keep a given point in a circuit TRUE FALSE None of the Can not A 1
HIGH when in the active state. above predict
102 A data selector is also called a demultiplexer. TRUE FALSE None of the Can not B 1
above predict
103 A digital circuit that converts coded information into a familiar or non- TRUE FALSE None of the Can not B 1
coded form is known as an encoder. above predict
104 An exclusive-OR gate will invert a signal on one input if the other is TRUE FALSE None of the Can not A 1
always HIGH. above predict
105 ---Circuit is logic Circuit which depends only on the sequential combinatioal VHDL both A & B B 1
combination of inputs
106 In ---- circuit does not need memory sequential combinatioal VHDL both A & B B 1
107 which are the following are examples of combinational counters regixters adders PAL C 1
circuits
108 flip-flop is an example of ----- circuit combinational sequential mixed none of these B 1
109 Truth table is step of ---- method to design LSI MSI tradinational none of these C 1
combinational circuit.
110 If Y= AC +BC is given expression then A,B,C are Minterm Maxterm Literal both A & B C 1
called as
111 The expression Y= A'B' + BC+A'C is in ---- form SOP POS both A &B none of these A 1
112 The expression Y= (A+B)(B+C)(A+C) is in ---- form SOP POS both A &B none of these B 1
113 which form means each term used in a switching standard non-standard canonical none of these C 1
equation must contain all the availble input variables.
114 the expression Y= ABC+AB'C' is in ----form standard POS standard SOP both A &B none of these B 1
115 The expression Y=(A+B)(A'+B') is in --- form standard POS standard SOP both A &B none of these A 1
116 which form means each term may contain one,two or non-standard mixed standard both A&C A 1
any number of literals.
117 which is the nonstandard SOP form equation ? Y=A+BC+AC Y=A'B+AB' Y=A'B+BC'+AB' both A&C D 1
118 the standard form of the SOP expression Y= AB+AC' is ABC+A'B'C'+AB'C'
ABC+ABC'+AB'C'
ABC+A'BC'+AB'C'ABC+ABC' B 1
Y=
119 In conversion from SOP to standard SOP --- each term OR AND Add Substract B 1
with the term formed by OR ing missing literal and its
compement
120 In conversion from POS to standard POS --- each term OR AND Add Substract A 1
with the term formed by AND ing missing literal and its
compement
121 Each individual term in the standard SOP form is called minterm maxterm both A &B none of these A 1
as---
122 Each individual term in the standard SOP form is called minterm maxterm both A &B none of these B 1
as---
123 Minterm corresponding to 011 combination is--- A'BC AB'C AB'C' A'B'C A 1
124 Maxterm corresponding to 011 combination is-- A'+B+C A+B'+C A+B'+C' A'+B'+C C 1
125 The relation between the expressions expressed using additive complementary dual none of these B 1
minterm and maxterms is of ---- nature
126 Standard two forms of boolean expression are ---- SOP & POS SOP&SOS POS&POP none of these A 1
127 the minterm designator of the term AB'CD' is 4 15 10 none of these C 1
128 the maxterm designator of the term A'+B'+C+D' is--- 2 13 10 none of these B 1
129 A switching function f(A,B,C,D) = ∑(1,3,5,7,9) ∑3,5,7,9,11) ∑(3,5,9,11,13) ∑(5,7,9,11,13) B 1
A'B'CD+A'BC'D+A'BCD+AB'C'D+AB'CD can also be
writteh as--
130 The switching function f(A,B,C,D)=∑(5,9,11,14) can be AB'CD'+A'BCD'+A'BC'D+A'B'C'D
AB'C+AB'C'D+ABC'D+ABCD'
A'B'CD+A'BC'D'+A'BCD'+ABC'D
A'BC'D+AB'C'D+AB'CD+ABCD'
D 1
written as equal to
131 Logical expression in the SOP form is most suitable for NOR NAND AND EX-NOR B 1
designing logic circuit using only---
132 The boolean expression in the POS form is must suitable EX-NOR AND NAND NOR D 1
for designing logic circuits using only--
133 The IC 7483 is a ---- BCD adder comparator multiplexer demultiplexer A 1
S.r No Question A B C D Answer Marks

1 How many data select lines are required for selecting eight inputs? 1 2 3 4 C 2
2 Half of an AND gate A circuit to Half of a NAND gate none of above B 2
Half adder circuit is? add two bits
together
3 sum of all previous bits
carry from ( K - 1 )TH bit C 2
The full adder adds the Kth bits of two numbers to the difference of the sum of previous bit
previous bits
4 The number of two input multiplexers required to construct a 210 31 10 127 1023 D 2
input multiplexer is,
5 Which of the following adders can add three or more numbers at a t Car ry-save- adder B 2
ime ?
Parallel adder Car ry-look- ahead D. Full adder
adder
6 gives an output B 2
when
all input signals are
present
simultaneous ly
is a memory circuit is a -ve OR gate is a linear circuit
An AND circuit
7 The device which changes from serial data to parallel data is COUNTER MULTIPLEXE DEMULTIPLE FLIP-FLOP C 2
R XER
8 A device which converts BCD to Seven Segment is called MULTIPLEXER DEMULTIPL ENCODER DECODER D 2
EXER
9 How many 3-line-to-8-line decoders are required for a 1-of-32 1 2 4 8 C 2
decoder?
10 A device which converts BCD to Seven Segment is called Encoder Decoder Multiplexer Demultiple B 2
xer
11 accepts one input accepts many accepts many inputs accepts one input C 2
and inputs and gives and gives one output and gives one
gives several output many output output
A multiplexer is a logic circuit that
12 In order to implement a n variable switching function, a MUX must 2n inputs 2n+1 inputs 2n-1 inputs 2n-1 A 2
have
inputs
13 Design circuits Register A 2
Logic gates with a set of input and outputs is arrangement of Combinat ional Logic circuit
circuit
14 A latch is constructed using two cross-coupled AND and OR AND gates NAND and NAND D 2
gates NOR gates
gates
15 A combinational logic circuit which sends data coming from a single Decoder Encoder Multiplexer Demultiple D 2
source to two or more separate destinations is
xer
16 Combinat ion al circuits A/ D converters A 2
Data can be changed from special code to temporal code by using Shift registers Count ers
17 The gray code equivalent of (1011)2 is 1101 1010 1110 1111 B 2
18 Odd parity of word can beconveniently tested by XOR gate D 2
OR gate AND gate NOR gate
19 Which one of the following will give the sum of full adders as output D 2
? Three bit parity
Three point majority checker Three bit comparator Three bit counter
circuit
20 The number of full and half-adders required to add 16-bit numbers is B 2
4 half-
8 half-adders, 1 half-adder, 16 half- adders, 0 full- adders, 12 full-
8 full-adders 15 full- adders adders adders
21 A one-to-four line demultiplexer is to be implemented using a A 2
memory. How many bits must each word have ?
1 bit 2 bits 4 bits 8 bits
22 The digital multiplexer is basically a combination logic circuit to OR-OR AND-OR OR-AND C 2
perform the operation
AND-AND
23 4 8 12 16 D 2
How many lines the truth table for a four-input NOR gate would
contain to cover all possible input combinations ?
24 How many truth tables can be made from one function table ? 1 2 3 B 2
ANY NO
25 operates at the same A 2
speed as parallel
adder
A comparison between serial and parallel adder reveals that serial is more complicate
order is slower is faster d
26 nput combination at A 2
that t ime
and the previous input
input combination present output and
and the combination the previous output
If a logic gates has four inputs, then total number of possible input input combination at
combinations is the t ime previous output
27 Which of the following circuit can be used as parallel to serial Multiplexer Decoder A 2
converter ? Digital counter
Demultiplexe r
28 In which of the following adder circuits, the carry look r ipple delay is Car ry- look- ahead adder C 2
eliminated ?
Half adder Full adder Parallel adder
29 Adders is called so D 2
because a full
adder
involves two half-
adders needs two input and
generates two output All of these
adds 2 bits
30 The number of control lines for 32 to 1 multiplexer is 4 16 5 6 C 2
31 The selector inputs to an arithmetic-logic unit (ALU) determine the: selection of arithmetic data word clock B 2
32 What are the two types of basic adder circuits? half adder and half adder asynchronou one's A 2
33 The inverter OR-gate and AND gate are called deeision-making words,high bytes,low bytes,high character,l A 2
elements
because they can recognize some input while disregarding others. A
ow
gate
34 Which one of the following set of gates are best suited for 'parity' NOR B 2
checking and 'parity' generation. EX-NOR or gates
AND, OR, NOT EX-OR gates NAND gates
gates
35 What are the three output conditions of a three-state buffer? HIGH, LOW, 1, 0, float both of the neither of C 2
float above the above
36 best suited for A 2
detecting double-bit
errors that occur
during the
transmission of
best suited for codes
detecting from one location to
NONE OF THE
single-bit errors in another.
Select one of the following statements that best describes the parity ABOVE
transmitted codes.
method of error detection: A AND B
37 What is the minimum number of two-input NAND gates used to one two three Four C 2
perform
the function of two input OR gate ?
38 How many full adders are required to construct an m-bit parallel m-1 m m+1 B 2
adder ? m/ 2
39 Conver t BCD 0001 0010 0110 to binary. 1111110 1111000 1111101 1111111 A 2
40 Conver t BCD 0001 0111 to binary. 10101 10001 10010 11000 C 2
41 Cor ners in the same column Overlappin g C 2
Which of the following combinations cannot be combined into K-map Cor ners in the same Diagonal corners combinati
groups? row ons
42 A C 2
A defective IC chip A solar bridge defective output IC
As a technician you are confronted with a TTL circuit board that is between the inputs An open chip that has an
containing dozens of ICchips. You have taken several readings at drawing excessive on input on the first internal open to V cc
numerous IC current from the the first IC chip on ICchip on the board
chips, but the readings are inconclusive because of their erratic power supply the board
nature. Of the possible faults listed, select the one that most
probably is causing the problem.
43 The device shown here is most likely a. comparator multiplexer demultiplexe parity C 2
r generator
44 Which of the following expressions is in the product-of-sums form? (A + B )(C + D ) (AB )(CD ) AB (CD ) AB + CD A 2
45 The binary numbers A = 1100 and B = 1001 are applied to the A > B = 1, A < B A > B = 0, A < A > B = 1, A < A > B = 0, C 2
inputs of a comparator. What are the output levels? = 0, A < B = 1 B = 1, A = B = 0 B = 0, A = B = 0 A < B = 1, A = B = 1
46 variables within the variables within the C 2
variables within the loop that appear in loop that appear
loop that both only in
variables that complemente d and their uncomple
appear only in their remain unchanged
complemented form. within the uncompleme mented
nted form. form.
loop.
Looping on a K-map always results in the elimination of:
47 Give the design to a B 2
Program a chip and technician to verify the
What will a design engineer do after he/ she is satisfied that the Put it in a flow chart test it design Perform a vector
design will work? test
48 go LOW, because go HIGH, be unpredicta ble; it D 2
there is no current react as if the open since full voltage may go HIGH
in an open circuit input were a HIGH appears across an or LOW
open
When an open occurs on the input of a CMOS gate, the output will.
49 To subtract a signed number (the subtrahend) from another signed complemented complemente always never D 2
number (the minuend) in the 2's complement system, the minuend is only if it is positive d only if it is complemente d compleme nted
. negative
50 In an odd-parity system, the data that will produce a parity bit = 1 is data = data = data = All of the D 2
. 1010011 1111000 1100000 above
51 The addition of two signed numbers in the 2's complement system have the same sign have C 2
can cause overflow. For overflow to occur both numbers must. be positive be negative opposite signs
52 give an overall A 2
picture of how the
signals flow
eliminate the need allow any circuit to produce the simplest
for be sum-of- through
tedious Boolean implemented with products expression the logic circuit
simplifications just AND and OR
A Karnaugh map will. gates
53 the number of 1s in the number of 1s in D 2
the number is odd the number is
An 8-bit binary number is input to an odd parity generator. The parity the number is odd the number is even even
bit will equal 1 only if.
54 The final output of a POScircuit is generated by. an AND an OR a NOR a NAND A 2
55 Theseries of IC's are pin, function, and voltage-level compatible ALS CMOS HCT 2N C 2
with the 74 series IC's.
56 Thecircuit produces a HIGH output whenever the two inputs are exclusive-AND exclusive- exclusive- exclusive- C 2
equal. NAND NOR OR
57 A 4-bit adder has the following inputs: C0 = 0, A1 = 0, A2 = 1, A3 = 0, 1100 10101 11000 11 C 2
A4 = 1, B1 = 0, B2 = 1, B3 = 1, B4 = 1. The output will be.
58 Thestatement evaluates the variable status. IF/ THEN IF/ THEN/ EL CASE ELSIF A 2
SE
59 In VHDL, data can be each of the following types except. BIT BIT_VECTOR STD_LOGIC STD_VECT D 2
OR
60 Occasionally, a particular logic expression will be of no A 2
consequence in the operation of a circuit, such as in a BCD-t o- spurious, AND's, spurious, 1's, 0's,
decimal converter. These OR's,
result interms in the K-map and can be treated as either or, in order don't care, 1's, 0's, duplicate, 1's, 0's, simplify
tothe resulting term. simplify eliminate verify
61 A good rule of thumb for determining the pin numbers of dual-in-line TRUE None of the above Can not predict B 2
package ICchips would be to place the notch to your r ight and pin # FALSE
1
will always be in the lower r ight corner.
62 The input at the 1, 2, 4, 8 inputs to a 4-line to 16-line decoder with TRUE FALSE None of the Can not B 2
active- above predict
low outputs is 1110. As a result, output line 7 is driven LOW.
63 When decisions demand two possible actions, the IF/ THEN/ ELSE TRUE FALSE None of the Can not A 2
control structure is used. above predict
64 The 54 prefix on ICs indicates a broader operating temperature TRUE FALSE None of the Can not A 2
range, above predict
generally intended for military use.
65 This is an example of a POSexpression: TRUE FALSE None of the Can not A 2
above predict
66 The abbreviation for an exclusive-OR gate is XOR. TRUE FALSE None of the Can not A 2
above predict
67 In an even-parity system, the parity bit is adjusted to make an even TRUE FALSE None of the Can not A 2
number of one bits. above predict
68 In an even-parity system, the following data will produce a parity bit TRUE FALSE None of the Can not B 2
= 1. above predict
data = 1010011
69 The following combination is correct for an EVEN parity data TRUE FALSE None of the Can not B 2
transmission system:data = 100111100 and parity = 0 above predict
70 The CASE control structure is used when an expression has a list of TRUE FALSE None of the Can not A 2
possible values. above predict
71 An encoder in which the highest and lowest value input digits are TRUE FALSE None of the Can not B 2
encoded simultaneously is known as a priority encoder. above predict
72 Three select lines are required to address four data input lines. TRUE FALSE None of the Can not B 2
above predict
73 Single looping in groups of three is a common K-map simplification TRUE FALSE None of the Can not B 2
technique. above predict
74 In true sum-of-products expressions, the inversion signs cannot TRUE FALSE None of the Can not A 2
cover above predict
more than single variables in a term.
75 A combinatorial logic circuit has memory characteristics that TRUE FALSE None of the Can not B 2
"remember" the inputs after they have been removed. above predict
76 A BCD adder adds two --- digits and produces ----digit BCD,BCD Binary,Binary Digital,Digital BCD,Binary A 2
77 A BCD number cannot be greater than --- 10 7 9 2 C 2
78 If sum is less than or equal to 9 and carry=0,then ----- is correction no correction B 2
necessary
79 Wrong result of BCD addition can be corrected by adding 6 3 1 2 A 2
------ to invalid BCD
80 The combinational circuit in BCD adder produces an add 0,<9 1,>9 1,=9 1,<9 B 2
command 6 if the carry is ----- or sum is ----
81 The output of combinational circuit should be 1 if sum 9 8 7 2 A 2
produced by adder 1 is greater than ---
82 The sum and carry outputs of a half adder are ----- and ------ 0,0 0,1 1,0 1,1 C 2
for 0+1
83 Full adder is ----- input and ----output combinational circuit 2,2 3.2 3,3 2,3 B 2
84 A full adder can be realized using--- 1 half adder,2 OR 2 half adder,1 OR gate
2 half adder,2 OR gatenone of these B 2
gate
85 Which of the following is known as sum of half adder XOR gate XNOR gate NAND gate NOR gate A 2
86 A sum bit output of full adder is same as ---- sum bit output of difference bit output
carry
of half
bit output
substractor
of half
difference
adder bit output of full
D substractor
2
half adder
87 The result of binary addition 1+1+1=--- carry 0,sum 0 carry 0,sum 1 carry 1,sum 0 carry 1,sum 1 D 2
88 Half adder circuit is --- half of an AND a circuit to add twohalf
bitsof
together
a NAND gate none of these B 2
gate
89 The sum and carry output of Half Adder are 1 and 0,then its Both B & C 0,1 1,0 1,1 A 2
inputs are ----
90 In half adder addition is limited to ---- bits 2 3 4 5 A 2
91 Minimization of logical expression while designing digital cost space requirementspower requirements all of the above D 2
systems helps in reduing----
92 In 4-variable k-map , a group of eight adjacent ones leads to 1 variable 2 variable 3 variable 0 variable A 2
a term with----
93 In k-map simplification , a group of four adjacent ones leadsone literal less two literals less three literals less four variables less B 2
to a term with --- than the total than the total than the total than the total
number of number of number of variables number of
variables variales variables
94 The code used for labelling the cells of the K-map is natural BCD hexadecimal gray octal C 2
95 Any 1 can be included any number of times without affecting TRUE FALSE A 2
the expression in K-map
96 In K-map --- grouping of 1's is not allowed Horizontal vertical Diagonal Corner C 2
97 A ----group should be eliminated because it increase the Adjacent redundant don't care none of these B 2
number number of gates requied to realize the minimized
expression
98 Don't care condition (X) may be assumed to be ---- 0 1 0 or 1 none of these C 2
99 Which eliminates three variables Quad Octet Pair none of these B 2
100 Quad eliminates --- variables 2 4 3 1 A 2
101 By pairing two adjacents 1's we can eliminates ---- variable 1 2 3 4 A 2
102 A group of ---- adjacent 1's or 0's is called as an Octet 8 4 16 32 A 2
103 A group of two adjacent 1's or 0's is called as ----- Quad Pair Octet none of these B 2
104 A group of four adjacent 1's or 0's is called as ---- pair octet quad none of these C 2
105 K-map is ----- method of simplifying ---- equation Graphical,Boolean Analytical,Boolean Tabular,arithmetic none of these A 2
106 2 Variable K-map cinsists of ----- rectangular boxes 4 2 8 1 A 2
107 In K-maps input values are ordered in ---- code sequence Binary Gray decimal none of these B 2
DELD Unt 3 Sequential Circuit
Sr. Question Option A Option B Option C Option D Correct
No. Option Marks
1 Which of the following is not a form of multivibrator? Astable. Monostable. Tristable. Bistable. C 1
A J-K flip-flop has two control inputs. What happens to the Q output on the active edge of the clock if The Q output The Q output The Q output The Q A
both control inputs are asserted simultaneously? toggles to the is set to 1. is reset to 0. output
2 other state. remains 2
unchanged
.
A master/slave bistable is formed using two bistable connected in series. TRUE False A
3 1
An astable has two metastable states and produces the function of a digital oscillator TRUE False A
4 1
In synchronous counters the clock input of each of the bistables are connected together so that each changes
TRUEstate at the same
False
time. A
5 1
1: When the maximum clock rate is quoted for a logic family, then it applies to a shift register flip-flop counter Multiplexe r B
6 1
2: The number of flip-flops required in a modulo N counter is log2 (N) + 1 log2(N-1) log2 (N) N log2 (N) C
7 2
3: Flip-flop outputs are always Complimentary The same Independentsame as previous input
A
8 of each other 1
4: How many gates (minimum) are needed for a 3-bit up-counter using standard binary and using T lip- 6 3 2 1 C
9 lops ? Assume unlimited fan-in. 2
5: The clear data and present input of the JK lip-lop are known as Synchronous inputs
Directed inputs Either (a) or None of C
10 1
(b) thes
A mod-2 counter followed by a mod-5 counter is Same as a A decade A mod-7 Ripple A
mode-5 counter counter counter carry
followed by a Counter
11 mod- 2 counter 1
What is the maximum counting speed of a 4-bit binary counter which is composed of flip-flops with a propagation
1 MHz delay of 25
10ns
MHz
? 100 MHz 8 MHz B
12 2
8: A JK flip-lop has its J input connected to logic level 1 and its input to the Q output. A clock pulse is fed Change its state Go to state 1 Go to state 0 Retain its D
to its clock input. The flip-lop will now at each clock and stay and stay there previous
pulse there state
13 2
9: Consider an RS lip-lops with both inputs set to 0. If a momentary '1' is applied at the input S,then the Q willQflip
willfrom
flip from 0 to 1 and then
Q will
backflip
to 0 Q will flip D
output 0 to 1 and then from 1 to 0 from 0 to 1
14 back to 0 2
The output of a sequential circuit depends on Present inputs Past outputs Both present Present C
only only and past outputs
inputs only
15 2
The ring counter is analogous to Toggle switch Latch Stepping switchJ-K flip- flop C
16 1
12: In a digital counter circuit feedback loop is introduced to Improve Reduce
Improve
the number of input pulses toAsynchron
reset the counter
C
distortion stability ous input
17 and 1
output
pulses
A J-K lip-lop has its J-input connected to logic level 1 and its input to the Change its state at each
Go to
clock
state
pulse
1 andGo
stay
to state
there0 andRetain
stay there
its present state
A
18 Q output pulse is fed to its clock input the flip-flop will now 2
Which of the following conditions must be met to avoid race around problem ? Δ t < tp < T T > Δt > tp 2 tp < Δt < T None of theseB
19 2
With the use of an electronic counter six capsules are to be filled in bottles automatically. In such a counter3 what will be the 12
number of flip- 6flops required ? 8 C
20 2
A pulse train can be delayed by a finite number of clock periods using A serial-in A serial-in Both
A parallel-
(a) and in parallel- out shift
D register
serial-out shift parallel-out (b)
21 register shift register 1
22 How many illegitimate states has synchronous mod-6 counter ? 3 2 1 6 A 1

A 2 bit binary multiplier can be implemented using 2 input ANDsXORs and 4 input
2 input 2 input
AND
NORs
gates
andonly
one XNOR
NORgate
gates B
only and shift
23 registers 2
A ring counter is same as up-down parallel- shift register

Ripple carry Counter
C
24 counter counter 1
The dynamic hazard problem occurs in Combinational circuit

Sequential
alone circuitBoth
only(a) and None of theseC
25 1
(b)
26 A n-stage ripple counter will count up to 2n 2n-1 n 2n-1 A 1
The clock signals are used in sequential logic circuits to Tell how
Tell
much
the time
time of
has elapsed since theCarry
systemparllel
was turned
Synchroniz
on D
the day data signals e events in
various
27 parts of 2
system
74L5138 chip functions as Decoder/demu Encoder Multiplexer Demultiple A

ltiplexer xer
28 1
A sequential circuit outputs a ONE when an even number (> 0) of one's are input; otherwise the output is 0
ZERO. The minimum
1 number of states
2 required isNone of C
29 these 2
A shift register can be used for Digital delay

Serial to parallelParallel
conversion
to serial conversion
All of these D
30 line 1
Popular application of flip-flop are Transfer register Shift registers Counters All of these D
31 2
For which of the following flip-flops, the output is clearly defined for all combinations of two inputs ? Q type flip-flop R-S flip-lop J-K flip-lop D flip-flop C
32 2
When a large number of analog signals are to be converted an analog multiplexer is used. In this case Ripple carry Dual stop Forward Successive D
most suitable A.D. converter will be counter type type counter type approxima
33 tion type 2
34 To build a mod-19 counter the number of flip-flops required is 3 5 7 9 B 2

The astable multivibrator has Two quasi TwoOne
stable
stable and one quasi-stable
Nonestate
of A
stable states states these
35 2
How many bits are required to encode all twenty six letters, ten symbols, and ten numerals ? 5 6 10 48 B
36 2
The functional difference between S-R flip-flop and J-K flip-flop is that J- K flip-flop is faster than S- Has a feed- Accepts both Both (a) C
37 R flip-flop back path inputs 1 and (b) 1
In a positive edge triggered JK flip-flop, a low J and low K produces No change Low state High state None of A
thes
38 1
When an inverter is placed between both inputs of an SR flip-flop, then resulting flip-lop is JK flip-flop D flip-flop SR flip-flop Master slave JK
B flip-flop
39 2
A 2 MHz signal is applied to the input of a J-K lip-lop which is operating in the 'toggle' mode. The 1 MHz 2 MHz 6 MHz 8 MHz D
40 frequency of the signal at the output will be 2
The master slave JK lip-flop is effectively a combination of A SR flip-flop and

Ana SR
T flip-
flip-flop
lfop and
A Taflip-flop
D flip-flop
and a D flip-
Two
flopD flip- A
41 flops 2
It is difficult to design asynhronous sequential circuit because External clock is It is more Both
Generally
(a) andthey involve stability
D problem
to be provided complex (b)
42 2
A stable multivibrator is used as Comparator Demultiplexe

Frequency to voltage converter
Voltage to frequency
A converter
43 circuit r 2
How many flip-flop are needed to divide the input frequency by 64 ? 2 5 6 8 C

44 1
41: In a ripple counter using edge triggered JK flfp-flops, the pulse input is applied to the clock input of all clock input of J and KJinputs
and K inputs of one flip-
C flop
flip-flops one flip- flops of all flip-flops
45 1
The number of clock pulses needed to shift one byte of data from input to the output of a 4-bit shift register
10is 12 16 32 C
46 2
The main difference between JK and RS flip-flop is that JK flip flop There is a JK flip-flop JK flip-flop C
needs a clock feedback in JK accepts both is acronym
pulse lip-lop inputs as 1 of Junction
cathode
47 multivibra 2
tor
Which of the following unit will choose to transform decimal number to binary code ? Encoder Decoder Multiplexer Counter A
48 1
The flip-flops which operate in synchronism with external clock pulses are known as Synchronous flip-flop
Asynchronou s flip-flop
Either of the above
None of theseA
49 1
Which of the following flip-flop is free from race-around problem ? Q flip-flop T flip-flop SR flip-flop Master- slaveDJK flip-flop
50 2
If the input J is connected through K input of J-K, then flip-flop will behave as a D type flip-flop T type flip- S-R flip-flop Master slave JK
A flip-flop
51 flop 2
If a clock with time period 'T' is used with n stage shift register, then output of final stage will be delayed by
nT sec (n-1)T sec n/T sec (2n+1)T B
52 2
sec
Register is a set of capacitor used to register
temporary
input instructions
storage
setunit
toinpaper
within
a digital
thecomputer
CPU having dedicated
part of the
or general
C purpose use
tapes and main
cards put in a memory
53 file 1
54 The number of flip-flops required in a decade counter is 3 4 8 10 B 1

If in a shift resistor Q0 is fed back to input the resulting counter is Twisted ring Ring counter Twisted ring Ring C
with N : 1 scale with N : 1 with 2N : 1 counter
55 scale scale with 2 N : 1
1 scale
A 8-bit serial in / parallel out shift register contains the value “8”, clock signal(s) will be required to shift
1 the value completely
2 out of the
4 register. 8 D
56 2
In a sequential circuit the next state is determined by and State variable, Current state, CurrentInput
stateand clock signal D
applied
current state flip- flop and external
57 output input 2
The divide-by-60 counter in digital clock is implemented by using two cascading counters: Mod-6, Mod-10 Mod-50, Mod-10Mod-10, Mod-50Mod-50, Mod-6
A
58 2
In NOR gate based S-R latch if both S and R inputs are set to logic 0, the previous output state is maintained.
True FALSE A
59 2
The minimum time for which the input signal has to be maintained at the input of flip-flop is called Set-up time Hold time Pulse Pulse B
of the flip-flop. Interval time Stability
60 time (PST) 2
61 74HC163 has two enable input pins which are and ENP, ENT ENI, ENC ENP, ENC ENT, ENI A 4
The input overrides the input Asynchronous Synchronous, Preset
Clear
input
input (CLR), Preset input
A (PRE)
, synchronous asynchronou (PRE), Clear
s input (CLR)
62 4
A decade counter is . Mod-3 counter Mod-5 counter Mod-8 counter Mod-10 counter
D
63 2
In asynchronous transmission when the transmission line is idle, It is set to logic It is set to Remains in State of B
low logic high previous state transmissi
on line is
64 not used 2
to start
transmissi
on
65 A Nibble consists of bits 2 4 8 16 B 1

66 The output of this circuit is always . 1 0 A Abar C 1
is one of the examples of synchronous inputs. J-K input EN input Preset input Clear Input (CLR)
A
67 (PRE) 2
occurs when the same clock signal arrives at different times at different clock inputs due to Race condition Clock Skew Ripple Effect None of B
propagation delay given
68 options 2
Consider an up/down counter that counts between 0 and 15, if external input(X) is “0” the counter 0 1101 1011 1111 B
counts
upward (0000 to 1111) and if external input (X) is “1” the counter counts downward (1111 to 0000),
69 now 1
suppose that the present state is “1100” and X=1, the next state of the counter will be
In a state diagram, the transition from a current state to the next state is determined by Current stateCurrent state and
Previous
outputsstatePrevious
and inputs
state and outputs
A
70 and the inputs 1
is used to simplify the circuit that determines the next state. State diagram Next state State State assignmenDt
71 table reduction 2
A 8-bit serial in / parallel out shift register contains the value “8”, clock signal(s) will be required to shift
1 the value completely
2 out of the
4 register. 8 D
72 1
Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. 1100 11 0 1111 C
What
73 will be the 4-bit pattern after the second clock pulse? (Right-most bit first.) 2
LUT is acronym for Look Up Table Local User Least Upper

None of given options
A
74 Terminal Time Period 2
The diagram given below represents Demorgans law Associative Product of Sum of product form
D
75 law sum form 2
The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop Doesn’t have an It
Sets
does
to not
clearshow transition on change
It doesinnot
pulseA
invalid state when both J accept
76 = 0 and K = 0 asynchron 1
ous inputs
A multiplexer with a register circuit converts Serial data to Parallel data Serial data to Parallel data to
B parallel
77 parallel to serial serial 1
How many flip-flops are required to produce a divide-by-32 device? 2 5 6 4 B

78 2
A reduced state table has 18 rows. The minimum number of flip flops needed to implement the sequential18
machine is 9 5 4 C
79 2
Advantage of synchronous sequential circuits over asynchronous ones is fasterease
operation
of avoiding problems due
lower
to hazard better A
hardware noise
80 requirement immunity 1
The characteristic equation of a JK flip flop is Qn+1=J.Qn+K.Q Qn+1=J.Q’n+ Qn+1=QnJ.K Qn+1=(J+K B

81 n K’.Qn )Qn 1
WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J-K FLOP-FLOP ARE SET TO LOGIC ZERO ------- THE FLOP- Q=0 AND QTHE OUTPUT
Q=1 ANDOF
Q FLIP- FLOP REMAINS
D UNCHANG ED
FLOP IS ‟=1 ‟=0
TRIGGERED
82 2
In Q output of the last flip-flop of the shift register is connected to the data input of the first Moore machine Meally Johnson Ring D
flip-flop of the shift register. machine counter counter
83 2
5-BIT JOHNSON COUNTER SEQUENCES THROUGH STATES 7 10 32 25 B

84 2
A 8-bit serial in / parallel out shift register contains the value “8”, 1 2 4 8 D
clock signal(s) will be required to shift the value completely out of the register.
85 1
AT T0 THE VALUE STORED IN A 4-BIT LEFT SHIFT WAS “1”. WHAT WILL BE THE VALUE OF 2 4 6 8 D
REGISTER AFTER THREE CLOCK PULSES?
86 1
The alternate solution for a multiplexer and a register circuit is Parallel in / Serial in / Parallel
Serial
in /in / Serial Out shiftA register
Serial out shift Parallel out Parallel out
87 register shift register shift register 1
B parallel
A synchronous decade counter will have flip-flops 3 4 7 10 B

89 2
In outputs depend only on the current state. Mealy machine Moore State Reduction
State
table
Assignmen t table
B
90 Machine 1
Given the state diagram of an up/down counter, we can find The next state of The previous Both the next The state A
a given present state of a and previous diagram
state given states of a shows only
present state given state the
91 inputs/out 1
puts of a
given states
THE HOURS COUNTER IS IMPLEMENTED USING ONLY A SINGLE MOD-10 MOD-10 A SINGLE D
MOD- AND MOD-6 AND MOD-2 DECADE
12 COUNTER IS COUNTERS COUNTERS COUNTER
92 REQUIRED AND A 2
FLIP-FLOP
THE GLITCHES DUE TO RACE CONDITION CAN BE AVOIDED BY USING A GATED FLIP- PULSE POSITIVE- NEGATIVE D
FLOPS TRIGGERED EDGE -EDGE
93 FLIP-FLOPS TRIGGERED TRIGGERE 2
FLIP-FLOPS D FLIP-
FLOPS
A
94 (PRE) 1
A positive edge-triggered flip-flop changes its state when Low-to-high High-to-low Enable input
Preset input (PRE) is
A set
transition of transition of (EN) is set
95 clock clock 1
Flip flops are also called Bi-stable Bi-stable Bi-stable Bi-stable C

dualvibrators transformer multivibrator singlevibra
96 s tors 1
A FIELD-PROGRAMMABLE LOGIC ARRAY CAN BE PROGRAMMED BY THE USER AND NOT BY TRUE FALSE A
THE MANUFACTURER.
97 2
THE FOUR OUTPUTS OF TWO 4-INPUT MULTIPLEXERS, CONNECTED TO FORM A 16-INPUT AND OR NAND XOR B
MULTIPLEXER, ARE CONNECTED TOGETHER THROUGH A 4-INPUT
98 GATE 2
A particular half adder has 2 INPUTS AND 2 INPUTS 3 INPUTS 3 INPUTS B

99 1 OUTPUT AND 2 AND 1 AND 2 2
OUTPUT OUTPUT OUTPUT
A full-adder has a Cin = 0. What are the sum (<PRIVATE "TYPE=PICT;ALT=sigma"> ) and the carry = 0, Cout = 0 = 0, Cout = 1 = 1, Cout = 0 = 1, Cout B
(Cout) =1
100 when A = 1 and B = 1? 2
The sequence of states that are implemented by a n-bit Johnson counter is n+2 (n plus 2) 2n (n 2n (2 raise to n2 (n raise B
multiplied by power n) to power 2)
101 2) 2
A 8-bit serial in / parallel out shift register contains the value “8”, 1 2 4 8 D
clock signal(s) will be required to shift the value completely out of the register.
102 1
on line is
103 not used 1
to start
transmissi
on
The alternate solution for a demultiplexer-register combination circuit is Parallel in / Serial in / Parallel
Serial
in /in / Serial Out shiftB register
The alternate solution for a multiplexer and a register circuit is Parallel in / Serial in / Parallel
Serial
in /in / Serial Out shiftA register
In outputs depend only on the current state. Mealy machine Moore State Reduction
State
table
Assignmen t table
B
106 Machine 2
occurs when the same clock signal arrives at different times at different clock inputs due to Race condition Clock Skew Ripple Effect None of B
propagation delay. given
107 options 2
is one of the examples of asynchronous inputs. J-K input S-R input D input Clear Input (CLR)
D
108 1
Bi-stable devices remain in either of their states unless the inputs force the device to switch its state
Ten Eight Three Two D
109 1
A set
110 clock clock 2
The low to high or high to low transition of the clock is considered to be a(n) State Edge Trigger One-shot B
111 2
In asynchronous digital systems all the circuits change their state with respect to a common clock TRUE FALSE B
112 1
If the S and R inputs of the gated S-R latch are connected together using a gate then there is only a AND OR NOT XOR C
single input to the latch. The input is represented by D instead of S or R (A gated D-Latch)
113 1
If S=1 and R=0, then Q(t+1) = for positive edge triggered flip-flop 0 1 Invalid Input is invalid
B
114 1
The high density FLASH memory cell is implemented using 1 floating-gate 2 floating- 4 floating- 6 floating- A
MOS transistor gate MOS gate MOS gate MOS
115 transistors transistors transistors 1
A bidirectional 4-bit shift register is storing the nibble 1110. Its input is 1110 111 1000 1001 D
LOW. The nibble 0111 is
116 waiting to be entered on the serial data-input line. After two clock pulses, the shift register is storing 1
.
At T0 the value stored in a 4-bit left shift was “1”. What will be the value of register after three clock pulses?
2 4 6 8 D
117 2
on line is
118 not used 2
to start
transmissi
on
B parallel
In outputs depend only on the combination of current state and inputs Mealy machine Moore State Reduction
State
table
Assignmen t table
A
120 Machine 1
The input overrides the input Asynchronous, Synchronous, Preset

Clear
input
input (CLR), Preset input
A (PRE)
synchronous asynchronou (PRE), Clear
s input (CLR)
121 1
is one of the examples of asynchronous inputs. J-K input S-R input D input Clear Input (CLR)
122 2
A set
123 clock clock 1
In asynchronous digital systems all the circuits change their state with respect to a common clock TRUE False B
124 1
For a gated D-Latch if EN=1 and D=1 then Q(t+1) = 0 1 Q(t) Invalid B
125 2
If S=1 and R=1, then Q(t+1) = for negative edge triggered flip- flop 0 1 Invalid Input is
126 C 2
invalid
The sequence of states that are implemented by a n-bit Johnson counter is n+2 2n 2 raise to power n n raise to
127 power 2 2
B
At T0 the value stored in a 4-bit left shift was “1”. What will be the value of register after three clock pulses?
2 4 6 8 D
128 2
A
129 (PRE) 1
A set
130 clock clock 2
Flip flops are also called Bi-stable Bi-stable Bi-stable multivibrator

Bi-stable ssinglevibraCtors
131 dualvibrators transformer 1
The sequence of states that are implemented by a n-bit Johnson counter is n+2 (n plus 2)2n (n multiplied by 2n
2) (2 raisen2
to (n raise to power
B 2)
132 power n) 1
A transparent mode means The changes in The changes Propagation Input Hold A
the data at the in the data at Delay is zero time is zero
inputs of the the inputs of (Output is (no need to
latch are seen at the latch are immediately maintain
the output not seen at changed when input after
the output clock signal is clock
133 applied) transition) 2
A positive edge-triggered flip-flop changes its state when Low-to-high High-to-low Preset input (PRE) is
Enable input A set
134 clock clock 2
If the S and R inputs of the gated S-R latch are connected together using a gate then there is only a AND OR NOT XOR C
single input to the latch. The input is represented by D instead of S or R (A gated D-Latch)
135 2
If S=1 and R=0, then Q(t+1) = for positive edge triggered flip-flop 0 1 Invalid Input is invalid
136 1
If an S-R latch has a 1 on the S input and a 0 on the R input and then the S set reset invalid clear A
137 input goes to 0, the latch will be 2
For a positive edge-triggered J-K flip-flop with both J and K HIGH, the outputs will if the clock goes HIGH.
toggle set reset not change A
138 2
What is the difference between a D latch and a D flip-flop? The D latch has TheThe
D flip-
D latch is usedThe
for Dfaster
flip- flop
operation.
has a clock
D input.
a clock input. flop has an
139 enable input. 2
A frequency counter Counts pulse Counts

Countshigh
no. ofand low range of given
None
clock
of pulse
B
width clock pulses given
140 in 1 second options 2
DELD Unit IV MCQ
S.r No Question A B C D Answer Marks
ASM
State box without decision and conditional asm defined simple both a
1 box is
C 1
block block block and b
operatio
2 ASM chart resembles with map data flowchart C 1
n
decision conditio
3 Control sequence state is indicated by state box data box A 1
box nal box
Control information gives knowledge Command metadat operatio
4 Signal
data A 1
about the a n
clear initial enable reset
5 If system is performing no function then it is B 2
in state state state state
any
6 ASM chart has 4 exits 3 exits 2 exits number of D 2
exits
2 3 4 5
7 ASM chart is composed of B 1
elements elements elements elements
present next
In designing ASM with multiplexers, the
8 registers hold binary input binary output A 2
state state
master clock
9 All inputs are synchronized with counter latch B 1
clock pulses
Pervious
A state table for a controller is a list of next
states states current
10 present states and inputs and their and
states
None A 2
and outputs
corresponding
output
conditio
11 State box of ASM chart represents clock state pulse C 1
n
One that is not present in the list of present next previous
12 state
input
state
D 1
state table is state
Difference in conventional flowchart time
master
13 clock
flow relationshi clock C 1
and ASM chart is p
Design ASM with multiplexers, is the
14 1 level 2 level 3 level 4 level C 1
method consists of
state
15 Sequential circuit is also called state encoder flip flop D 1
machine
16 ASM chart takes entire block as 1 unit 2 unit 3 unit 4 unit A 1
state
17 ASM chart is very same to
diagram
flowchart data box operation A 1
The rounded corners of conditional box
18 state box decision
box
data box
conditiona
l box
A 2
differentiate it from
19 For going to the next state flip-flop is set to 1 0 y don’t care A 1
Master
The timing for all flip-flops in digital system clock
20 is controlled by Memory latches None B 1
Generato
r
The number of inputs and outputs in a state not
21 table are
equal same unequal
present
A 1
The third level of design with multiplexer Demultip
22 consists of
mux encoder decoder D 1
lexer
algorithmi algorith arithmeti arithmeti
23 ASM stands for c state mic solid c state c solid A 2
machine
machine machine machine
negative negative positive negative
In ASM design flip-flops are considered to
24 be
edge level edge level C 2
triggered triggered triggered triggered
pentago
25 State box is a shape of square rectangle rhombus B 1
n
pentago
26 Conditional box has a shape of square rectangle oval C 1
n
Box that tells the effect of input on control decision conditio
27 subsystem is called
state box data box B 1
box nal box
decision conditiona
28 One that is not the element of ASM chart is state box
box
data box
l box
C 1
29
30 PLD
Which type of PLD should be used to
31 program basic logic functions?
PLA PAL CPLD SLD B 2
thousands
of basic
advanced thousands logic
The content of a simple programmable fuse-link sequential of basic gates and
32 arrays logic logic advanced D 1
logic device (PLD) consists of:
functions gates sequential
logic
functions
its its
it cannot outputs outputs its logic
be
33 Once a PAL has been programmed:
reprogram are only are only capacity A 1
med. active active is lost
HIGHs LOWs
field- a global
a
The complex programmable logic program AND/OR interconne language
34 arrays ction
C 2
device (CPLD) contains several PLD mable compiler
matrix
blocks and: switches
35 PLAs, CPLDs, and FPGAs are all which SLD PLD EPROM SRAM B 1
type of device?
the PLA the PAL
has a has a
programm programm
able OR able OR
plane and plane and the PAL
a a has more
PALs and
programm programm possible
PLAs are
36 The difference between a PLA and a PAL is: able AND able AND product
the same
A 2
plane, plane, terms
thing.
while the while the than the
PAL only PLA only PLA
has a has a
programm programm
able AND able AND
plane plane
nonexist
ent;
program there is
37 The OR array in a PAL is ________.
fixed floating A 2
mable no OR
array in a
PAL
NOT, NAND,
The basic programmable logic array (PLA) NOT, OR, NOR,
38 contains a set of _____ gates, _____ gates,
NAND, AND, B 2
AND, OR AND
and ______ gates OR NOR
There are five steps in the PLD prototyping
39 process.
TRUE FALSE A 1
SLDs and PLDs are digital logic ICs that
40 can have their function changed TRUE FALSE B 1
through programming.
41 Both the AND and OR arrays in a PAL are TRUE FALSE B 1

programmable.
CAD software can be used to create a
42 detailed logic circuit that will perform like an TRUE FALSE A 1
actual PLD.
A FPGA is an array of programmable
43 logic blocks that are interconnected by TRUE FALSE B 1
OR gates.
The inputs in the PLD is given through NAND OR gates NOR AND
44 D 2
____________ gates gates gates
Program Program Program Program
mable mable mable mable
45 PAL refers to ____________ C 2
Array Logic Array AND
Loaded Array Logic Logic
Outputs of the AND gate in PLD is known as Input Output Strobe Control
46 ____________
B 1
lines lines lines lines
AND and NAND NOT and
NOR and
47 PLA contains ____________ OR and OR AND OR arrays A 2
arrays arrays arrays
A
A A simple
complex
PLA is used to implement complex A simple combinat
48 sequential combinat C 1
____________ sequenti circuit ional
ional
al circuit circuit
circuit
It hasn’t It doesn’
It hasn’t
It hasn’t capabilit t provide
capabilit
A PLA is similar to a ROM in concept capabilit y to read full
49 except that ____________
y to C 2
y to read or write decoding
write
only operatio to the
only
n variables
For programmable logic functions, which
50 type of PLD should be used?
PLA PAL CPLD SLD B 1
51 Which type of device FPGA are? SLD SROM EPROM PLD D 1
First Field
First Field
program Program
Program Program
52 The FPGA refers to ____________ mable mable B 1
Gate Gate
Gate Gate
Array Array
Array Array
Configur PAL All of the
Registere
53 Applications of PLAs are _____________ able program Mention D 2
d PALs
PALs ming ed
PLD contains a large number of All of the
54 Flip-flops Gates Registers Mentioned D 2
_________
Non Low
Fast All of the
destructi power
55 The advantages of RAMs are __________ operatin Mention D 2
ve read dissipati
g speed ed
out on
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
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90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
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119
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121
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123
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127
128
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130
131
132
133
DELD MCQ Unit V Logic Families
Sr No. Question Correct

A B C D Answer Marks
1 The commercially available 8-input multiplexer integrated circuit in the 7495 74153 74154 74151 B 2
TTL family is
2 The logic 0 level of a CMOS logic device is approximately 1.2 volts 0.4 volts 0volts 5volts C 2
3 Which ofthe following is a universal logic gate? OR XOR AND NAND D 1
4 How is the noise margin of a logic family defi ned? VOH – greater
VOL of VDD – smaller
VOH andofVOL
VIL – GND
VOL and VOH
VIH––VIH
VIL. C 2
5 What parameter causes the main limit on fan-out of CMOS logic in high-speed applications?
d.c. input output input power supply voltage.
A 2
current current capacitance
6 The number of standard loads that the output of the gate can drive with out impairment Fan-in Fan-Out noise-margin
power- dissipiatio n B 2
of its normal operation is
7 A NAND gate is called a universal logic element because itall

is the
usedminization
by any
techniques
logic are applicable for optimum
many NAND gate
B realization
2
everybody function can digital
be realized by computers
NAND gates use NAND
alone gates.
8 Measure of power consumed by the gate when fully driven by all its inputs is Fan-in Fan-Out noise-margin
power- dissipiatio n D 2
9 Fan-out is specified in terms of voltage current watt unit load D 2

10 Which of the following logic family has highest fan-out DTL CMOS RTL TTL B 2
11 Which of following consume minimum power TTL RTL DTL CMOS D 1
12 Among the logic families, low power dissipation is in DTL CMOS RTL TTL B 1
13 The temperature in which the performance of the IC is effective Operating Fan-Out Normal power- A 1
14 The nominal value of the dc supply voltage for TTL (transistor-transistor 0v 5v 10v 15v B 1
logic) devices is
15 The average transition delay time for the signal to propagate from Propogation Fan-Out noise-margin
power- dissipiatio n A 2
input to output when the signals change in value. It is expressed in ns is Delay
16 the number of inputs connected to the gate without any degradation in the Propogation Fan-Out Fan- in power- dissipiatioC 2
Delay
17 Which of the following logic gives the complementary outputs? ECL TTL CMOS PMOS A 2
18 The maximum noise voltage added to an input signal of a digital circuit Fan-in Fan-Out noise-margin power- C 2
19 Among the logic families, Slowest logic family is TTL RTL DTL CMOS D 1
20 Operating temperature of the IC vary from 0 to70 celsius 0to35celsius 0to 50celsius 0to70celsi A 1
21 1. Open collector output 2. Totem-Pole Output 3. Tri-state output are the TTL LOGIC RTL LOGIC CMOS LOGIC None of A 1
type of this
22 If the channel is initially doped lightly with p-type impurity a conducting Depletion Enhancemen Both Mode None of A 1
23 If the region beneath the gate is left initially uncharged the gate field must induce aDepletion mode operationEnhancemen
MOS Both Mode None of B 2
channel before current can flow. Thus the gate voltage enhances the t mode this
channel current and sucha device is said to operate in the operation of
MOS
24 The n- channel MOS conducts when its gate- to- source voltage
gate- to- sourcegate- to- source None of this A 2
25 The p- channel MOS conducts when its gate- to- gate- to- gate- to- None of C 2
26 The fan-out of a MOS-logic gate is higher than that of TTL gates because of its low input high input low output high output D 2
impedance impedance impedance impedance
27 Which factor does not affect CMOS loading? Charging time associated
Discharging time
Output capacitance
Input capacitanc C 2
28 Logic gates are the basic elements that make a Analog system Basic System gating system digital system D 1
29 Which of the following gate is a two-level logic gate OR gate NAND gate EXCLUSIVE OR gate
NOT C 1
30 Among the logic families, the family which can be used at very high frequency greater thanTTLAS
100 MHz in a 4 bit
CMOS ECL TTLLS C 1
31 NAND. gates are preferred over others because these have lower can be consume
used to least
provide
electronic
maximum
powerdensity in aBchip. 2
fabrication area make any
gate
32 The fan Out of a 7400 NAND gate is 2TTL 5TTL 8TTL 10TTL D 2
33 Which transistor element is used in CMOS logic? FET MOSFET Bipolar Unijunctio n B 2
34 CMOS circuits are extensively used for ON-chip computers mainly because of their low power high noise large packing density.
low cost. C 2
extremely dissipation. immunity.
35 Which equation is correct? VNL = VIL(max) VNH = VOH VNL = VOH VNH = VOH D 2
+ VOL(max) (min) + VIH (min) – VIH (min)
(min) (min) – VIH(min)
36 The greater the propagation delay, the lower the higher the maximum minimum A 2
maximum maximum frequency is frequency
frequency frequency unaffected is
unaffected
37 For a CMOS gate, which is the best speed-power product? 1.4 Pj 1.6 pJ 2.4 pJ 3.3 pJ A 2
38 In a TTL circuit, if an excessive number of load gate inputs are connected, VOH(min) VOH drops VOH exceeds VOH and B 2
drops below below VOH VOH(min) VOH(min)
VOH (min) are
unaffected
39 Which is not a MOSFET terminal? Gate Drain Source Base D 2

40 An open-drain gate is the CMOS counterpart of an open- collector TTL gate
a tristatea bipolar junction
an emitter-
transistor
coupled logic gate
A 2
TTL gate
41 The active switching element used in all TTL circuits is the bipolar junction
metal-oxide
field-effect
semiconduct or field- effectunijunctio
transistor (MOSFET
A 2
transistor (BJT transistor n transistor
(FET (UJ)
42 One output structure of a TTL gate is often referred to as a diode JBT totem-pole
base, emitter, collector arrangeme
C nt 2
arrangement arrangement
43 An open-collector output requires a pull-down resistor

a pull-up resistor
no output resistor
an output resistorB 2
44 Which is not an output state for tristate logic? HIGH LOW High-Z Low-Z D 2
45 TTL is alive and well, particularly in industrial millitary educational
commercia lapplicatio nsC 2
applications applications applications
46 A TTL NAND gate with IIL(max) of –1.6 mA per input drives eight TTL –12.8 Ma –8 mA –1.6 mA –25.6 mA A 4
inputs. How much current does the drive output sink?
47 A standard TTL circuit with a totem-pole output can sink, in the LOW 16 Ma 20 mA 24 Ma 28mA A 4
state (IOL(max)),
48 It is best not to leave unused TTL inputs unconnected (open) because of noise sensitivity low-currentopen- collector outputs
tristate constructi on A 2
TTL's requirement
49 Which logic family combines the advantages of CMOS and TTL? BiCMOS TTL/CMOS ECL TTL/MOS A 2
50 Which is not part of emitter-coupled logic (ECL)? Differential Bias circuitEmitter- follower circuit
Totem- D 2
amplifier pole circuit
51 PMOS and NMOS circuits are used largely in MSI functions LSI functions diode functions TTL B 2
functions
52 The nominal value of the dc supply voltage for TTL and CMOS is 3V 5V 10 V 12 V B 2
53 If ICCH is specified as 1.1 mA when VCC is 5 V and if the gate is in a static (noncharging) HIGH
5.5 Mw
output state, the
5mWpower dissipation
5.5 W (PD) of the1.1mW
gate is A 4
54 The switching speed of CMOS is now competitive three times slower than twice that A 2
with TTL that of TT TTL of TTL
55 One advantage TTL has over CMOS is that TTL is less expensive
not sensitive to electrostaticfaster
discharge more B 2
widely
available
56 TTL operates from a 9-volt suppl 3-volt supply 12-volt supply 5-volt supply D 1
57 A CMOS IC operating from a 3-volt supply will consume the same power as a TTL
less power than more power no IC
power A 2
a TTL IC than a TTL IC at all
58 CMOS IC packages are available in DIP SOIC DIP and SOIC None of C 2
configuration configuration configuration this
s
59 The terms "low speed" and "high speed," applied to logic circuits, refer to the rise time fall time propagation clock speed C 2
delay time
60 The power dissipation, PD, of a logic gate is the product of the dc supply dc supply ac supply ac supply B 2
voltage and voltage and voltage and voltage
61 How many different logic level ranges for TTL 1 2 3 4 D 1
62 Metal-oxide semiconductor field-effect transistors (MOSFETs) are the active switching elements
CMOS in
circuits TTL ECL circuits PMOS A 2
circuits
63 ECL IC technology is……………….than TTL technology. faster slower equal none of this A 1
64 A major advantage of ECL logic over TTL and CMOS is low power high speed both low neither low B 1
dissipation power power
dissipation dissipation
and high nor high
speed speed
65 Digital technologies being used now-a-days are DTL and EMOS

TTL, ECL, CMOSTTL,
and ECL,
RTL CMOS
TTL,
andECL,
DTLCMOS and DTLB 2
66 Which of the following is the fastest logic TTL ECL CMOS PMOS B 2
67 Which TTL logic gate is used for wired ANDing Open collector Totem Pole Tri state ECL gates A 2
output output
68 CMOS circuits consume power Equal to TTL Less than Twice of TTL Thrice of B 1
TTL TTL
69 CMOS circuits are extensively used for ON-chip computers mainly because of their low power high noise large packing density
low cost. C 2
extremely dissipation immunity
70 The MSI chip 7474 is Dual edge Dual edge Dual edge Dual edge C 2
triggered JK triggered D triggered D triggered
flip-flop (TTL). flip-flop flip-flop JK flip-flop
(CMOS). (TTL). (CMOS).
71 The logic 0 level of a CMOS logic device is approximately 1.2 volts 0.4 volts 5 volts 0 volts D 2
72 What is unique about TTL devices such as the 74SXX? These devices The gate The S denotes The S A 4
use Schottky transistors the fact that a denotes a
transistors and are silicon single gate is slow
diodes to (S), and the present in the version of
prevent them gates IC rather than the device,
from going into therefore the usual which is a
saturation; this have lower package of consequen
results in faster values of 2–6 gates. ce of its
turn-on and leakage higher
turn-off times, current. power
which rating.
translates into
higher
frequency
operation.
73 Which of the following logic families has the shortest propagation delay? CMOS BiCMOS ECL 74SXX C 1
74 Why must CMOS devices be handled with care? so they don’t

because
get because
they can
they
be damaged by staticall
electricity
of abovedischarge
C 2
dirty break easily
75 What should be done to unused inputs on TTL gates? They should be All unused All unused Unused D 2
left gates should inputs should AND and
disconnected so be be NAND
as not to connected connected to inputs
produce a load together and an unused should be
on any of the tied to V output; this tied to VCC
other circuits through a 1 will ensure through a
and to minimize k resistor. compatible 1k
power loading loading on resistor;
on the voltage both the unused OR
source. unused inputs and NOR
and unused inputs
outputs. should be
grounded.
76 Assume that a particular IC has a supply voltage (Vcc) equal to +5 V and ICCH = 10 mA and50
ICCL
Mw= 23 mA. What
82.5ismW
the power115
dissipation
mW for the
165chip?
mW B 4
77 Can a 74HCMOS logic gate directly connect to a 74ALSTTL gate? YES No A 1

78 What is the major advantage of ECL logic? very highwide
speedrange of operating very
voltage
low cost very high A 2
power
79 As a general rule, the lower the value of the speed–power product, the better the device long long Both none of B 2
because of its: propagation propagation above
delay and high delay and low
power power
consumption consumption
80 What is the difference between the 54XX and 74XX series of TTL logic gates? 54XX is faster. 54XX is 54XX has a 54XX has a C 2
slower. wider power narrower
supply and power
expanded supply and
temperature contracted
range.
temperatu
re range.
81 What is the range of invalid TTL output voltage? 0.0–0.4 V 0.4–2.4 V 2.4–5.0 V 0.0–5.0 V B 2
82 An open collector output can current, but it cannot . sink, source source, sink sink, sourcesource, sink voltage A 2
current current voltage
83 Why is a decoupling capacitor needed for TTL ICs and where should it be connected to block
to reduce
dc, the to
effects
reduce
of noise, connect between
NONE
power
OFsupply and
C ground 2
connect to input noise, connect ABOVE
pins to input pins
84 Which of the following summarizes the important features of emitter- coupled logic low noise good noise low poor noise A 2
(ECL)? margin, low immunity, propagation immunity,
output voltage negative logic, time, high- positive
swing, negative high- frequency supply
voltage frequency response, low voltage
operation, fast, capability, power operation,
and high power low power consumption, good low-
consumption dissipation, and high frequency
and short output voltage operation,
propagation swings and low
time power
85 Why is a pull-up resistor needed for an open collector gate? to provide Vcc
to provide ground
to provide
for the IC
the HIGH
to provide
voltage
the LOW voltage
C 2
for the IC
86 Why is a pull-up resistor needed when connecting TTL logic to CMOS to increase the to decrease to increase
to decrease the output HIGH voltage
C 2
logic? output LOW the output the output
voltage LOW voltage HIGH voltage
87 The word "interfacing" as applied to digital electronics usually means: a conditioning a circuit any gate that any TTL B 2
circuit connected is a TTL circuit that
connected between the operational is an input
between a driver and amplifier buffer stage
standard TTL load to designed to
NAND gate condition a condition
and a standard signal so signals
TTL OR gate that it is between
compatible NMOS
with the load transistors
88 The rise time (tr) is the time it takes for a pulse to rise from its point up to its 10%, 90%, 90%, 10%, 20%, 80%, 10%, A 4
point. The fall time (tf) is the length of time it takes to fall from the to the 90%, 10% 10%, 90% 80%, 20% 70.7%,
point. 70.7%,
10%
89 The term buffer/driver signifies the ability to provide low output currents to drive light loads.
TRUE FALSE B 2
90 PMOS and NMOS . represent are represent None of the A 4

MOSFET devices enhancement positive and above
utilizing either -type CMOS negative MOS-
P-channel or N- devices used type devices,
channel devices to produce a which can be
exclusively series of operated from
within a given high-speed differential
gate logic known power
as 74HC supplies and
are
compatible
with
operational
amplifiers
91 Why is the operating frequency for CMOS devices critical for determining power At low At high At high At high C 2
dissipation? frequencies, At frequencies, frequencies, frequencie
low frequencies, the gate will charging and s, the gate
power only be able discharging will only
dissipation to deliver the gate be able to
increases. 70.7 % of capacitance deliver
rated power. will draw a 70.7 % of
heavy rated
current from power and
the power charging
supply and and
thus increase dischargin
power g the gate
dissipation. capacitanc
e will
draw a
heavy
current
from the
power
supply and
thus
increase
power
dissipation
.
92 Ten TTL loads per TTL driver is known as: noise immunity fan-out power dissipation
propagatio n delayB 2
93 The problem of different current requirements when CMOS logic circuitsa are
CMOSdriving
inverting bilateral
a TTL tristate
switch
a CMOS
inverting
between
noninverting
buffer
the stages
between
bilateral
theswitch
stagesabetween
CMOS the stages
D 4
TTL logic circuits can usually be overcome by the addition of: buffer or
inverting
buffer
94 Totem-pole outputs be connected because cannot,
. together, if the outputscan,
are in parallel,
opposite
can, states
together,
excessively
togethershould,
high
theycurrents
can
in handle
canlarger
damageload
one
currents
orBbothand
devices
higher
4 output voltages
sometimes series, certain
higher current applications
is required may require
higher output
voltage
95 The high input impedance of MOSFETs: allows

reduces
faster
input current and power
prevents
dissipation creates B 2
switching dense packing low-noise
reactions
96 The output current capability of a single 7400 NAND gate when HIGH is called source current sink current IOH source current of IOH A 2
97 The time needed for an output to change from the result of an input change is known as: noise immunity fan-out propagation delay
rise time C 2
98 The problem of interfacing IC logic families that have different supply voltages (VCC's) canLevel-shifter
be solved by usingtristate
a: shifter decoupling capacitor
pull-down resistorA 2
99 What is the advantage of using low-power Schottky (LS) over standard more power dissipation
less power dissipation
cost is less cost is more B 2
TTL logic?
100 When is a level-shifter circuit needed in interfacing logic? A level shifter is A level shifter when
when
thethe supply voltages are different
D 2
always needed. is never supply
needed. voltages are
the same
101 A TTL totem-pole circuit is designed so that the output transistors: are alwaysprovide
on linear phase
provide
splitting
voltage regulation
are never on together D 2
together
102 The most common TTL series ICs are: E-MOSFET 7400 QUAD AC00 B 1
103 Which family of devices has the characteristic of preventing saturation during operation? TTL ECL MOS IIL B 2
104 How many 74LSTTL logic gates can be driven from a 74TTL gate? 10 20 30 40 B 2
105 What is the difference between the 74HC00 series and the 74HCT00 series of CMOS The HCT The HCT he HCT series The HCT C 4
logic? series is faster. series is is input and series is
slower. output voltage not input
compatible and output
with TTL. voltage
compatible
with TTL.
106 Why are the maximum value of VOL and the minimum value of VOH used to determine theThese
noise are
margin rather
These
than
are
the typical
Thesevalues
are for these
It doesn't
parameters? A 2
worst-case normal best-case matter
conditions. conditions. conditions. what
values are
used.
107 What is the standard TTL noise margin? 5.0 V 0.0 V 0.8 V 0.4 V D 2
108 Which logic family is characterized by a multiemitter transistor on the input? ECL CMOS TTL None of the aboveC 2
109 he problem of the VOH(min) of a TTL IC being too low to drive a CMOS circuit and meet adding a fixed avoiding this adding an adding an D 4
the CMOS requirement of VIH(min) is usually easily overcome by: voltage- divider condition and external pull- external
bias resistive only using down pull-up
network at the TTL to drive resistor to resistor to
output of the TTL ground VCC
TTL device
110 How does the 4000 series of CMOS logic compare in terms of speed and power more power more power less power less power D 2
dissipation to the standard family of TTL logic? dissipation and dissipation dissipation dissipation
slower speed and faster and faster and
speed speed slower
speed
111 What should be done with unused inputs to a TTL NAND gate? let them float tie them tie them None of the aboveC 2
LOW HIGH
112 Which of the following logic families has the highest maximum clock frequency? S-TTL AS-TTL HS-TTL HCMOS B 2
113 Why is the fan-out of CMOS gates frequency dependent? Each CMOS When the The higher the The input D 4
input gate has a frequency number of gates of the
specific reaches the gates attached FETs are
propagation critical value, to the output, predomina
time and this the gate will the more ntly
limits the only be frequently capacitive,
number of capable of they will have and as the
different gates delivering to be serviced, signal
that can be 70% of the thus reducing frequency
connected to normal the frequency increases
the output of a output at which each the
CMOS gate. voltage and will be capacitive
consequently serviced loading
the output with an input also
power will signal. increases,
be one-half of thereby
normal; this limiting the
defines the number of
upper loads that
operating may be
frequency. attached
to the
output of
the driving
gate.
114 What must be done to interface TTL to CMOS? A dropping As long as the A 5 V Zener A pull-up D 2
resistor must be CMOS supply diode must be resistor
used on the voltage is 5 placed across must be
CMOS 12 V V, they can be the inputs of used
supply to interfaced; the TTL gates between
reduce it to 5 however, the in order to the TTL
V for the TTL. fan-out of the protect them output-
TTL is limited from the CMOS input
to five CMOS higher node and
gates. output Vcc; the
voltages of the value of RP
CMOS gates. will
depend on
the number
of CMOS
gates
connected
to the node.
115 What causes low-power Schottky TTL to use less power than the 74XX The Schottky- Nothing. The A larger value Using C 2
series TTL? clamped 74XX series resistor NAND
transistor uses less gates
power.
116 What are the major differences between the 5400 and 7400 series of The 5400 series The 5400 The 7400 The 7400 B 2
ICs? are military series are series are an series was
grade and military grade improvement originally
require tighter and allow for over the developed
supply voltages a wider range original by Texas
and of supply 5400s. Instrumen
temperatures. voltages and ts. The
temperature 5400 series
s. was
brought out
by National
Semicondu
ctors after
TI's
patents
expired, as
a second
supply
source.
117 Which of the following statements apply to CMOS devices? The
Thedevices Allbe
devices should tools, testand shipped in antistatic
stored All of the
tubes or conductive
D foam.
2
should not be equipment, above.
inserted into and metal
circuits with the workbenches
power on. should be
tied to earth
ground.
118 Which of the logic families listed below allows the highest operating frequency? 74AS ECL HCMOS 54S B 2
119 What is the increase in switching speed between 74LS series TTL and 5 10 50 100 B 2
74HC/HCT (High-Speed CMOS)?
120 What does ECL stand for? electron- emitter- coupled logic;
energy- NONE OF B 2
coupled logic; coupled logic; ABOVE
121 What is unique about TTL devices such as the 74S00? The gate The S denotes The S denotes The devices D 4
transistors are the fact that a a slow version use
silicon (S), and single gate is of the device, Schottky
the gates present in the which is a transistors
therefore have IC rather than consequence and
lower values of the usual of its higher diodes to
leakage current. package of power rating. prevent
2–6 gates. them from
going into
saturation;
this
results in
faster turn
on and
turn off
times,
which
translates
into higher
frequency
operation.
122 he bipolar TTL logic family that was developed to increase switching speed by emitter- current- transistor- emitter- D 2
preventing transistor saturation is: coupled logic mode logic transistor coupled
(ECL). (CML). logic (TTL). logic (ECL)
and
transistor-
transistor
logic
(TTL).
123 In TTL the noise margin is between 0.4 V and 0.8 V. 0.0 V and 0.4 0.0 V and 0.5 0.0V and A 2
V. V. 0.8 V.
124 What is the transitive voltage for the voltage input of a CMOS operating from 10V supply 1V 5V 10V 15V B 2
125 The highest noise margin is offered by CMOS TTL ECL BICMOS B 2
126 What is the transitive voltage for the voltage input of a CMOS operating from 10V supply ? 1V 5V 10V 20V B 2
127 The digital logic family which has the lowest propagation delay time is ECL TTL CMOS PMOS A 2
128 In a positive logic system, logic state 1 corresponds to Positive voltage Higher Zero voltageLower voltage level B 2
voltage level level
129 Which of the following logic families is well suited for high-speed operations ? TTL ECL MOS CMOS B 2
130 Which of the following is the fastest logic? ECL TTL MOS CMOS A 1
131 he digital logic family which has the lowest propagation delay time is ECL TTL CMOS PMOS c 2
132 A binary digit is called a Bit Byte Number Character A 1

133
134 Which of the following statements is wrong ? Propagation Noise Fan-in of a Operating C 4
delay is the time immunity is gate is always speed is the
required for a the amount of equal to fan- maximum
gate to noise out of frequency
change its state which can be the same gate at which
applied to the digital data
input of a gate can
without be applied
causing the to a gate
gate to
change state
135 Which table shows the logical state of a digital circuit output for every possible combination
Function
of logical
table
statesTruth
in thetable
inputs ? Routing table ASCII B 1
table
136 The digital logic family which has minimum power dissipation is TTL ECL MOS CMOS D 1
Unit 6 DELD
S.r No Question A B C D Answer
register control all of the

1 Major components of processor are ALU D
array unit above
2 to the
2 to the
power of
Number power of
Memory supported by processor is calculated Number of number
2 of data number B
by----- address lines of
lines of data
address
lines
lines
arithmat
arithmat
In ALU IC when asserted, Cin=L , performes arithmat ic with
3 logical ic with C
operation------ ic with
no carry
carry
In ALU which of the lines suggests operation Output Operatio Select
4 Input Lines D
to be performed Lines nal lines lines
Both
Arithmat
Logical None of
Arithmatic ic and
5 M=0, in ALU chip indicates---- Operatio the A
Operation logical
n above
operatio
ns
6 IC number of ALU is------- 74180 8086 80186 74181 D
Data lines that provide a path for moving
data among system modules all of the
7 8 bit 16 bit 32 bit d
May consist of ---------- according to procesor above
type.
ALU,
memory, decoder
decodes None of
The microprocessor or CPU reads each decodes it and
8 it and the A
instruction from the ------------- and executes execute
executes avove
it. it.
it.
Bidirecti Multidir
Unidirection None of
The address bus of microproceesor is noal, ectional,
9 al, the A
_______ and data bus _________ Unidirec Multidir
Bidirectional above
tional ectional
If Processor provides 32 address and 32 data
10 lines , How much memory is 1GB 2GB 4GB 16GB C
supported________
11 Which of the following is not 32 bit register? EAX R15D ECX EDX B
12 Which of the following is not 64bit register? RAX RBX R8 RCX C
13 Which of the following is not 16 bit register? AX BX R8W DX C
14 Which of the following is not 8 bit register? AL SIL BL CL B
None of
15 Which of the following is not 32 bit register? EAX R15 ECX B
these
None of
16 Which of the following is not 64 bit register? RAX R15D RCX B
these
None of
17 Which of the following is not 16 bit register? R15D AX BX A
these
None of
18 Which of the following is not 8 bit register? AL CL R10W C
these
B. It is
fabricate
d on a
small
chip
capable
of
19 performi C. It also d
ng ALU commun
Microproces (Arithme icate
sor is a tic with the
controlling Logical other
unit of a Unit) devices D. All of
micro- operatio connect the
What is true about microprocessor? computer ns ed to it. above
The __________ controls the flow of data register accumul
20 a
and instructions within the comput . control unit array ator ALU
D. Low
B. C. Low Power
21 c
Which of the following is not a features of a Reliabilit Bandwid Consum
Microprocessor? Versatility y th ption
D. None
22 The microprocessor ___________ those B. C. of the a
instructions from the memory Fetch Decode Execute above
D. All of
23 An 8-bit microprocessor can process _____ the b
data at a time. A. 4-bit B. 8-bit C. 16-bit above
D.
B. failure
A. The micropr rate of
microprocess ocessor C. an IC in
24 a
or is of small chips are micropr micropr
size chip, available ocessors ocessors
hence is not at low are is very
What is false about microprocessor? portable. prices versatile low
The devices that provide the means for a none of
25 computer to communicate with the user or CPU ALU I/O the c
other computers are referred to as above
26
27
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32
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DELD All Units MCQ

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S.

r No Question A B C D Answer Marks

S.r No Question A B C D Answer Marks

22 How many illegitimate states has synchronous mod-6 counter ? 3 2 1 6 A 1

A ring counter is same as up-down parallel- shift register

The dynamic hazard problem occurs in Combinational circuit

74L5138 chip functions as Decoder/demu Encoder Multiplexer Demultiple A

A shift register can be used for Digital delay

34 To build a mod-19 counter the number of flip-flops required is 3 5 7 9 B 2

The master slave JK lip-flop is effectively a combination of A SR flip-flop and

A stable multivibrator is used as Comparator Demultiplexe

How many flip-flop are needed to divide the input frequency by 64 ? 2 5 6 8 C

54 The number of flip-flops required in a decade counter is 3 4 8 10 B 1

65 A Nibble consists of bits 2 4 8 16 B 1

LUT is acronym for Look Up Table Local User Least Upper

How many flip-flops are required to produce a divide-by-32 device? 2 5 6 4 B

The characteristic equation of a JK flip flop is Qn+1=J.Qn+K.Q Qn+1=J.Q’n+ Qn+1=QnJ.K Qn+1=(J+K B

5-BIT JOHNSON COUNTER SEQUENCES THROUGH STATES 7 10 32 25 B

A synchronous decade counter will have flip-flops 3 4 7 10 B

Flip flops are also called Bi-stable Bi-stable Bi-stable Bi-stable C

A particular half adder has 2 INPUTS AND 2 INPUTS 3 INPUTS 3 INPUTS B

The input overrides the input Asynchronous, Synchronous, Preset

Flip flops are also called Bi-stable Bi-stable Bi-stable multivibrator

A frequency counter Counts pulse Counts

41 Both the AND and OR arrays in a PAL are TRUE FALSE B 1

Sr No. Question Correct

7 A NAND gate is called a universal logic element because itall

9 Fan-out is specified in terms of voltage current watt unit load D 2

39 Which is not a MOSFET terminal? Gate Drain Source Base D 2

43 An open-collector output requires a pull-down resistor

65 Digital technologies being used now-a-days are DTL and EMOS

74 Why must CMOS devices be handled with care? so they don’t

77 Can a 74HCMOS logic gate directly connect to a 74ALSTTL gate? YES No A 1

90 PMOS and NMOS . represent are represent None of the A 4

95 The high input impedance of MOSFETs: allows

132 A binary digit is called a Bit Byte Number Character A 1

register control all of the

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