College Code: 4013

College Name: K.K. Wagh Institute of Engineering Education and Research , Nashik
Department of Computer Engineering
Class: SE Computer:
Subject: Digital Electronics and Logic Design

First 42 Unit 1 and 2

Sr.No Unit No. Question Option A Option B
A table that shows result of logical operations
1 1 conducted is called_____. logic table truth table
How many NAND gates are contained in a
2 1 7400 NAND IC? 1 2

When grouping cells within a K-map, the cells

3 1 must be combined in groups of ________. 2s only 1,2,4,8
can be found in can be used to
The NAND or NOR gates are referred to as almost all build all the other
4 1 "universal" gates because either digital circuits types of gates
In circuits the output at any
instant of time is dependent only on the inputs
5 1 present at that instant of time combinational sequential
Which among the following is not the output
6 1 of comparator? A>=B A=B
The result of BCD adder is corrected by
7 1 adding . 5 7
A binary code that progresses such that only nine's
one bit changes between two successive codes complement alpha-numeric
8 1 is_____. code code
How many select lines would be required for
9 1 16: 1 multiplexer? 3 4
coded
information non-coded
into non coded information into
10 1 A decoder means form coded form
________is a correction combination for an data=11011011, data=00010101,
11 1 odd parity data transmission system parity=1 parity=1

12 1 The Excess-3 code word is obtained by adding (2)10 (5)10

Which among the following is 8:1 multiplexer
13 1 IC? 74153 74158
Each individual term in canonical SOP form is
14 1 called as______. minterm maxterm

For SOP form are entered

corresponding to the input variables which
15 1 produce high output for don’t care conditions. 0's x
 Which among the following is not a weighted
16 1 code? binary 8421
17 1 In BCD are valid BCD. 0000 to 1001 0000 to 1010
code is known as cyclic
18 1 code. Excess-3 Gray
is a 4-bit magnitude comparator
19 1 IC. 7481 7455
The octal to binary encoder has ________
20 1 input lines and output lines. 8,2 8,3
The addition of three bit operation is
performed by using
a ______ adder.
21 1 half full
If multiplexer has m input data and n controls
inputs and y Outputs then ____.
22 1 2n =m 2m =n
23 1 A BCD number cannot be greater than_____. 7 8
one data input
and a number
of selection
inputs, and they
have several one input and one
24 1 A demultiplexer has ________. outputs output
Which of the following is not a weighted binary-coded
25 1 value positional numbering system: hexadecimal decimal

Two half adders

26 1 A full adder consist of_____. Two nand gates cascaded together
Which of the following combinations cannot Corners in the Corners in the
27 1 be combined into K-map groups? same row same column
Which is not present in Quine Mc Cluskey
28 1 technique? PI EPI

SOP can be
converted to POS can be
29 1 Which is not true among the following? POS converted to SOP
30 1 0110 represents which minterm? ABCD ABCD
31 1 Find the equivalent of ∑m(2,4,7). ∑M(0,1,3,5,6) ∏M(0,1,3,5,6)
4 bit binary 4 bit binary
32 1 IC74LS83 is __________. adder subtractor
33 1 In Half Subtractor (A,B) the Difference = ? A EXOR B A
34 1 In Look Ahead Carry , Carry Generate =? AiBi Ai EXOR Bi

Half Adder adds

Full Adder can two single bit
be designed numbers without
using Half considering
35 1 Which among the following is not true? Adder Carry.
 Look Ahead Carry eliminates the problem due interstage carry
36 1 to _____ . delay borrow delay

The Pi in Look Ahead Carry is called

37 1 as_____. Carry Produced Carry Propogate
A Combinational Circuit in BCD Adder is
38 1 used to check if Sum is ____ or Carry= ____. less than 9 ,0 less than 9 ,1
In Half Subtractor Circuit , for the inputs 0 , 1
39 1 the Difference= ____ and Borrow=____. 0,0 1,1
Difference,
40 1 IC 7483 is having ___ and ___ as its outputs. Borrow Sum, Carry

41 1 Which are the Parity Inputs of IC 74180? A to H EVEN

What is the Expression for the output A>B in
42 1 1 bit Binary Comparator? AB AB'

An Edge-triggered flip-flop can change states The trigger is The D input is

51 2 only when HIGH HIGH

The advantage of J-K flip-flop over an S-R FF It has fewer It has only one
52 2 is that gates output
53 2 How is a J-K flip-flop made to toggle? J=0, K=0 J=1, K=0
On a J-K flip-flop when is the flip-flop in a
54 2 hold condition? J=0, K=0 J=1, K=0
For an S-R flip-flop to be set or reset the installed with in parallel with a
55 2 respective input must be---. steering diodes limiting resistor
The decimal equivalent of the largest number
that can be stored in a 4-bit binary counter
56 2 is____. 8 15
Asynchronous counters are often
57 2 called_____counters. toggle ripple
How many JK flip-flops are required to
58 2 construct a decade counter? 10 8
The terminal count of a typical modulus-10
59 2 binary counter is______. 1111 1010
An asynchronous 4-bit binary down counter
changes from count 2 to count 3. How many
60 2 transitional states are required? 3 1
A 4-bit up/down binary counter is in the
DOWN mode and in the 1100 state. To what
state does the counter go on the next clock
61 2 pulse? 1101 1011
Asynchronous Asynchronous
events do not events are
occur at the independent of
62 2 Which of the following statement is true? same time each other
Which of the following groups of logic Five flip-flop
devices would be the minimum required for a three AND Seven flip-flop
63 2 MOD-64 synchronous counter? gates five AND gates
 Up count is Up count is active
active –HIGH –LOW the down
The designation (up/~DOWN) means that the down count count is active-
64 2 the--- is active-LOW HIGH

The flip-flops The flip-flops

Why can a synchronous counter operate at a changes one changes at the
65 2 higher frequency than a ripple counter? after the other same time
Which IC is divided by 2 and divided by 5
66 2 counters? 74191 74193
67 2 _______consists of JK flip-flops 7474 7473
The output of a sequential circuit depends on present inputs
68 2 ____ only past outputs only
What type of register would have a complete
binary number shifted in one bit at a time and
have all the stored bits shifted out one at a Parallel-In - Parallel -In -
69 2 time? Parallel-Out Serial-Out
What is the preset condition for a ring shift All flip flops All flip flops
70 2 counter? set to 1 cleared to 0
Serial-In - Parallel -In -
71 2 Which is not characteristic of a shift register? Parallel In Serial-Out
In a 4-bit Johnson counter sequence there are
72 2 a total of how many states, or bit patterns? 1 2
73 2 ______consists of MS-JK flip-flops 7474 7473
Up- down
74 2 A ring counter is same as_____. counter Parallel-counter

75 2 In general a sequential logic consists of ---- only flip flops only gates
The state table gives relation between -----,---- input, present
76 2 and output state next state, input
In state assignment the assignment number is
77 2 represented by using----- Gray code Binary code
To design a sequence detector using Mealy
machine of sequence 100,--- number of states
78 2 are required 4 3
A J-K flip-flop has two control inputs. What is Q toggles to the
79 2 Q ,if J= 0 and K=1 ? Q=1 other state
In synchronous counter all flip flops are clocked not clocked
80 2 _______________ simultaneously simultaneously
combinational
81 2 A flip flop is a _____________ . circuit. memory element.
In which register there is no interconnection
between successive flip-flops and no serial
82 2 shifting is required ? SISO PISO
condition
83 2 If S=1 and R=1 then ____. Q=1 prohibited
A J-K flip-flop has two control inputs. What is Q toggles to the
84 2 Q , if J= 1 and K=0 ? Q=1 other state
 85 2 Which shifting method is faster ? serial parallel
Johnson's counter is also called as ___ ring
86 2 counter. twisted rounded

87 2 Johnson's counter is ___ counter. asynchronous synchronous

88 2 IC 7495 is _____. counter flip flop
A shift register which can shift the data in
both the directions is called as a _____ shift
89 2 register unidirectional bidirectional
A shift register which can shift the data only
in one direction is called as a _____ shift
90 2 register unidirectional bidirectional
A shift register which can shift the data in
both the directions as well as load it parallely
91 2 called as a _____ shift register unidirectional bidirectional
J K flip flop can be converted to D flip flop
92 2 using____ gate in between J and K. and not
Programmable Programmable
93 4 PLD stands for _____. Large Device Logic Device
The AND matrix in PLA is used to implement
94 4 ___ terms in SOP form. Sum Product
95 4 ____ are inputs to AND matrix in PLA. Input Buffers Product Terms
96 4 In PLA , OR matrix is having ___ as input. Input Buffers Product Terms
In PLA , Invert/Non Invert matrix is having
97 4 ___ as input. Input Buffers Product Terms
Programmable Programmable
98 4 PLA stands for ______. Logic Array Large Array
The OR matrix in PLA is used to implement
99 4 ___ terms in SOP form. Sum Product

PLD can not be PLD can be

programmed by programmed by
100 4 Which among the following is true? the user the user
Field
Programmable Field Portable
101 4 FPGA stands for________. Gate Array Gate Array
Simple
Simple Portable Programmable
102 4 SPLD stands for _______. Logic Device Logic Device
Complex Complex
Portable Logic Programmable
103 4 CPLD stands for _________. Device Logic Device
Programmable Programmable
104 4 PAL stands for _________. Array Logic Array Large
105 4 Identify odd man out of following? CPLD FPGA
Which among the following is not type of
106 4 PLD? RAM ROM
Which among the following is not type of
107 4 PLD? PLA PAL
108 4 In PAL ___ is fixed. AND matrix OR matrix

109 4 In PAL ___ is programmable. AND matrix OR matrix

110 4 In PAL , OR matrix is having ___ as input. Input Buffers Product Terms
111 4 ____ are inputs to AND matrix in PAL. Input Buffers Product Terms
112 3 Control sequence state is indicated by state box decision box
An ASM chart is composed of basic
113 3 elements 1 2
In ASM, if a system is not performing any
114 3 function then it is in _____. clear state initial state
115 3 ASM chart is similar to _____. map data
An ASM block has entrance and
116 3 number of exit paths 2,6 1,6
An oval shaped box in ASM is known as
117 3 box______ Conditional state
Difference in conventional flowchart and timing
118 3 ASM chart lies in clock pulse relationship
119 3 Change of state in ASM chart is performed in processor metadata
Rounded corners of conditional box
120 3 differentiate it from decision box conditional box
Second level of design with mux in ASM has
121 3 register holding ______. present state input
Design with multiplexers controller method ,
122 3 is consisting of _____. 1 level 2 levels
123 3 ASM chart takes entire block as 1 unit 2 unit
negative edge negative level
124 3 In ASM design flip-flops are considered to be triggered triggered
Hardware
High definition Description
125 3 HDL stands for language Language
Which VHDL data type can only have value
126 3 of '1' or '0'? signal bit
Library
127 3 Which is not the fundamental unit of VHDL? declarations ENTITY
In VHDL,how many modes are available for
128 3 ports? 3 4
The block of code which defines the
relationship between input, output and internal
signals or variables in a VHDL design is
129 3 the_____ . architecture entity
Synthesis and
Synthesis and documentation
130 3 VHDL can be used for simulation only only
Which statement can be used to check for Concurrent Sequential
131 3 error conditions? Statement Statement
In VHDL,which statement is used to jump
132 3 out of loop statement currently in execution? GOTO EXIT
 SIGNAL X:INTEGER RANGE -127 TO X is an 8-bit X is an 8-bit
133 3 127;In this statement X means? Signed number unsigned number
STD_LOGIC_1164 is a in VHDL
134 3 IEEE library. module package
Architecture Entity represents
Which one of the following statements is true represents the the
135 3 about VHDL? interface implementation
Which symbol is used for signal assignment
136 3 statements? = ==
variable
Which one is not the type of sequential assignment
137 3 statement? statements abort statements
How many modeling styles are there in
138 3 VHDL? 4 3

Architecture
may contain
declarations of
types,signals,co Single entity can
Which one is not true about architecture nstants,subprog have several
139 3 declaration? rams architectures
140 3 Which are the possible modes of a port? only IN,OUT IN,OUT,INOUT
Which among the following is not the type of
141 3 modeling style in VHDL? Structural Behavioral
Which among the following is not the type of STD_LOGIC_
142 3 signal used in VHDL? VECTOR STD_LOGIC
BIT and BIT_VECTOR are defined in VHDL
143 3 standard____. IEEE 1164 IEEE 1614
___ modeling style in VHDL is any
combination of behavior, data flow and
144 3 structural modeling. Combined Mixed
______ modeling has a set of interconnected
145 3 components. Structural Behavioral
______ modeling has a set of concurrent
146 3 assignment statements. Structural Behavioral

It is used for only

Which among the following is not true about It has 4 combinational
147 3 VHDL? modeling styles circuits
______ modeling style consist of sequential
148 3 program statements. Structural Behavioral
Identify odd man out of following in VHDL
149 3 statements? If Switch
Which among the following is not type of
150 3 sequential statements? If Switch
Identify odd man out of following in VHDL
151 3 statements? If Loop
Option C Option D Marks Correct Option

gate table system table 1B

4 8 1C

4s only 3s only 1B
were the first
are used in all gates to be
circuits integrated 2B

adder multiplexer 1A

A<B A>B 1A

9 6 1D

gray code Excess-3 code 2C

2 8 1B

conversion from conversion from

high to low low to high 2A
data=10101111, data=11011011,
parity=0 parity=0 2A

(3)10 (6)10 1C

74157 74151 1D

binary variable 1A

1's 11 1C
2421 Excess-3 code 1D
0000 to 1000 0000 to 1100 1A

BCD ASCII 1B

7404 7485 1D

8,4 8,1 2B

look ahead n bit 1B

mn =2 m2 =n 2A
9 10 1C

several inputs
and several several inputs
outputs and one output 1A

binary octal 1B

Two half adders Two half adders

and one And gate and one Or gate 1D
Overlapping
Diagonal corners combinations 1C

Minterms I 1D
SOP and POS
SOP and POS are always
are not related to logically
each other equivalent 2C
ABCD ABCD 1C
∑m(0,1,3,5,6) ∏m(0,1,3,5,6) 1B
8 4 bit binary 8 bit binary
adder subtractor 1A
B AB 1A
Ai Bi 1A
Full Adder can
not be used as Full Adder adds
basic building two single bit
block for 4 bit numbers and
BCD Adder IC also considers
such as 7483 carry. 2C
subtraction delay inputs 1A
Carry
Propogation
Delay Carry Problem 1B

greater than 9 ,0 greater than 9 ,1 2D

1,0 0,1 2B
Difference,
Sum, Borrow Carry 2B
EVEN and
ODD ODD 1A

AB+AB' A'B 2B
The trigger
The trigger is input changes
LOW level 1D
It does not 1
It has no invalid require a clock
states input C
J=0, K=1 J=1, K=1 1 D

J=0, K=1 J=1, K=1 1A

low high 1D

16 32 1B

binary race 1B

5 4 1D

1000 1001 1D

2 15 2D

1111 1100 1B
Synchronous Only
events do not asynchronous
need a clock to events need a
control them control clock 2A

Four flip-flop ten Six flip-flop

AND gates four AND gates 2D
Up and down Up and down
counts are both counts are both
active-LOW active -HIGH 1A
A synchronous
counter cannot
operate at higher A ripple counter
frequencies is faster 2B

7490 7483 1C
7476 7478 2B
both present and present outputs
past inputs only 1C

Serial -In - Serial -In -

Parallel-Out Serial-Out 1C
A single 0, the A single 1, the
rest 1 rest 0 1D
Serial -In - Serial -In -
Parallel-Out Serial-Out 1A

4 8 1D
7476 7478 2C
Ripple carry
Shift register counter 1C
only flip flops and
combinational combinational
logic circuits logic circuits 1D
present state,
next state input, next state 1C

ASCII code BCD code 1B

2 1 2B
Q remains
Q=0 unchanged 1C

initially clocked finally clocked 1A

arithmetic memory or
element arithmetic 1A

SIPO PIPO 1D
Q remains
Q=0 unchanged 1B
Q remains
Q=0 unchanged 1A
sequential random 1B

circular ms 1A
Ripple carry
register counter 1B
Shift register generator 1C

directional universal 1B

directional universal 1A

directional universal 2D

or nand 1B
Portable Logic Portable Large
Device Device 1B

Not Ex-OR 1B
Sum Terms Not Terms 1A
Sum Terms Not Terms 1B

Sum Terms Not Terms 1C

Portable Logic Portable Large
Array Array 1A

Not Ex-OR 1A
PLD cannot be
programmed as
PLD is fixed per user
function requirement 2B
Fine
Programmable Fine Portable
Gate Array Gate Array 1A
Simple
Programmable Simple Portable
Large Device Large Device 1B
Complex Complex
Programmable Portable Large
Large Device Device 1B
Portable Array Portable Array
Logic Large 1A
PLA PLG 1D

SPLD CPLD 1A

PAG FPGA 1C
Inver/Non Invert
buffer Output buffer 1B
Inver/Non Invert
buffer Output buffer 1A
Sum Terms Not Terms 1B
Sum Terms Not Terms 1A
data box conditional box 1A

3 4 1C

set state reset state 2B

flowchart structure chart 1C

1,8 1,any 2D

data decision 1A

conditions decision 1B
control logic condition logic 1C

data box state box 1D

output next state 1A

3 levels 4 levels 1C
3unit 6 unit 1A
positive edge positive level
triggered triggered 2C
Hardware Hardware
Definition database
Language Language 1B

integer std_logic 1D
ARCHITECTUR
E FORMAT 1D

5 6 1C

package library 1A
Simulation,
Synthesis and
documentation Programming 2A
Assertion Decision
Statement Statement 1C

NEXT END 1B
 X is an 4-bit
X is an 4-bit unsigned
Signed number number 1A

function procedure 1B
Architecture is
Entity represents written inside
the interface the entity 2D

<= := 1C
signal
assignment
statements next statements 1B

5 2 1A
Concurrent
statements in the
architecture
body define the
Architecture can relationship
be used without between inputs
an entity and outputs 2C
IN,CLK OUT,CLK 1B

Dataflow Combined 1D
BIT_LOGIC_V
BIT_VECTOR ECTOR 1D

IEEE 1416 IEEE 1146 2A

Total In all 2B

Dataflow Combined 1A

Dataflow Combined 1C
It is used for
combinational
and sequential It contains
circuits Foreign attribute 2B

Dataflow Combined 1B

Case Process 1B

Case Loop 1B

Case Function 1D