SEMICONDUCTOR TECHNICAL DATA

 
# #"  "
 #$  !  "!  
The UB Series logic gates are constructed with P and N channel # #"  "
enhancement mode devices in a single monolithic structure (Complemen-
tary MOS). Their primary use is where low power dissipation and/or high
noise immunity is desired. The UB set of CMOS gates are inverting
 
non–buffered functions. # #"   "
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Linear and Oscillator Applications  
• Capable of Driving Two Low–power TTL Loads or One Low–power # #"   "
Schottky TTL Load Over the Rated Temperature Range
• Double Diode Protection on All Inputs
• Pin–for–Pin Replacements for Corresponding CD4000 Series UB Suffix
 
Devices   #"   "

 
LOGIC DIAGRAMS   #"  "
MC14001UB MC14002UB MC14011UB
Quad 2–Input Dual 4–Input Quad 2–Input
NOR Gate NOR Gate NAND Gate
L SUFFIX
1 2 1
3 3 CERAMIC
2 3 2 CASE 632
1
5 4 5
4 4
6 5 6
8 9 8
10 10 P SUFFIX
9 10 9
13 PLASTIC
12 11 12
11 11 CASE 646
13 12 13
NC = 6, 8

D SUFFIX
MC14012UB MC14023UB MC14025UB
SOIC
Dual 4–Input Triple 3–Input Triple 3–Input
CASE 751A
NAND Gate NAND Gate NOR Gate
1 1 ORDERING INFORMATION
2 2 9
2 9 MC14XXXUBCP Plastic
3
1 8 8 MC14XXXUBCL Ceramic
4 3 3 MC14XXXUBD SOIC
5
4 6 4 6 TA = – 55° to 125°C for all packages.
9
5 5
10
13 11 11
11
12 10 12 10 This device contains protection circuitry to
12
NC = 6, 8 13 13 guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
VDD = PIN 14 any voltage higher than maximum rated volt-
VSS = PIN 7 ages to this high–impedance circuit. For proper
operation, Vin and Vout should be constrained
v v
FOR ALL DEVICES
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.

REV 3
1/94

MC14001UB
Motorola, Inc. 1995 MOTOROLA CMOS LOGIC DATA
18
 PIN ASSIGNMENTS

MC14001UB MC14002UB MC14011UB

Quad 2–Input NOR Gate Dual 4–Input NOR Gate Quad 2–Input NAND Gate

IN 1A 1 14 VDD OUTA 1 14 VDD IN 1A 1 14 VDD

IN 2A 2 13 IN 2D IN 1A 2 13 OUTB IN 2A 2 13 IN 2D
OUTA 3 12 IN 1D IN 2A 3 12 IN 4B OUTA 3 12 IN 1D
OUTB 4 11 OUTD IN 3A 4 11 IN 3B OUTB 4 11 OUTD
IN 1B 5 10 OUTC IN 4A 5 10 IN 2B IN 1B 5 10 OUTC
IN 2B 6 9 IN 2C NC 6 9 IN 1B IN 2B 6 9 IN 2C
VSS 7 8 IN 1C VSS 7 8 NC VSS 7 8 IN 1C

MC14012UB MC14023UB MC14025UB

Dual 4–Input NAND Gate Triple 3–Input NAND Gate Triple 3–Input NOR Gate

OUTA 1 14 VDD IN 1A 1 14 VDD IN 1A 1 14 VDD

IN 1A 2 13 OUTB IN 2A 2 13 IN 3C IN 2A 2 13 IN 3C
IN 2A 3 12 IN 4B IN 1B 3 12 IN 2C IN 1B 3 12 IN 2C
IN 3A 4 11 IN 3B IN 2B 4 11 IN 1C IN 2B 4 11 IN 1C
IN 4A 5 10 IN 2B IN 3B 5 10 OUTC IN 3B 5 10 OUTC
NC 6 9 IN 1B OUTB 6 9 OUTA OUTB 6 9 OUTA
VSS 7 8 NC VSS 7 8 IN 3A VSS 7 8 IN 3A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ NC = NO CONNECTION

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol Parameter Value Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VDD DC Supply Voltage – 0.5 to + 18.0 V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
lin, lout Input or Output Current (DC or Transient), ± 10 mA
per Pin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
PD Power Dissipation, per Package† 500 mW

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Tstg Storage Temperature – 65 to + 150 _C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TL Lead Temperature (8–Second Soldering) 260
* Maximum Ratings are those values beyond which damage to the device may occur.
_C

†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

MOTOROLA CMOS LOGIC DATA MC14001UB

19
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vin = 0 or VDD “1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Input Voltage “0” Level VIL Vdc
(VO = 4.5 Vdc) 5.0 — 1.0 — 2.25 1.0 — 1.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(VO = 9.0 Vdc) 10 — 2.0 — 4.50 2.0 — 2.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(VO = 13.5 Vdc) 15 — 2.5 — 6.75 2.5 — 2.5

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(VO = 0.5 Vdc) “1” Level IIH 5.0 4.0 — 4.0 2.75 — 4.0 — Vdc
(VO = 1.0 Vdc) 10 8.0 — 8.0 5.50 — 8.0 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(VO = 1.5 Vdc) 15 12.5 — 12.5 8.25 — 12.5 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Drive Current IOH mAdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 1.2 — – 1.0 – 1.7 — – 0.7 —
(VOH = 4.6 Vdc) 5.0 – 0.25 — – 0.2 – 0.36 — – 0.14 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(VOH = 9.5 Vdc) 10 – 0.62 — – 0.5 – 0.9 — – 0.35 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(VOH = 13.5 Vdc) 15 – 1.8 — – 1.5 – 3.5 — – 1.1 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Input Capacitance Cin — — — — 5.0 7.5 — — pF

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Vin = 0)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Quiescent Current IDD 5.0 — 0.25 — 0.0005 0.25 — 7.5 µAdc
(Per Package) 10 — 0.5 — 0.0010 0.5 — 15

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 1.0 — 0.0015 1.0 — 30

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Total Supply Current**† IT 5.0 IT = (0.3 µA/kHz) f + IDD/N µAdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Dynamic plus Quiescent, 10 IT = (0.6 µA/kHz) f + IDD/N
Per Gate CL = 50 pF) 15 IT = (0.8 µA/kHz) f + IDD/N
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µH (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates per
package.

MC14001UB MOTOROLA CMOS LOGIC DATA

20
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VDD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol Vdc Min Typ # Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise Time tTLH ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH = (3.0 ns/pF) CL + 30 ns 5.0 — 180 360
tTLH = (1.5 ns/pF) CL + 15 ns 10 — 90 180

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH = (1.1 ns/pF) CL + 10 ns 15 — 65 130

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Fall Time tTHL ns
tTHL = (1.5 ns/pF) CL + 25 ns 5.0 — 100 200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time tPLH, tPHL ns
tPLH, tPHL = (1.7 ns/pF) CL + 30 ns 5.0 — 90 180

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 22 ns 10 — 50 100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.50 ns/pF) CL + 15 ns 15 — 40 80
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

20 ns 20 ns
VDD
14 INPUT VDD
90%
50%
PULSE INPUT OUTPUT 10% 0V
GENERATOR tPHL tPLH
* CL 90% VOH
OUTPUT 50%
INVERTING
10% VOL
7 VSS
* All unused inputs of AND, NAND gates must be tTHL tTLH
connected to VDD.
All unused inputs of OR, NOR gates must be
connected to VSS.

Figure 1. Switching Time Test Circuit and Waveforms

MC14001UB CIRCUIT SCHEMATIC MC14002UB CIRCUIT SCHEMATIC

(1/2 of Device Shown)
VDD VDD 14
3 14 10 2, 9

1 8 3, 10

2 9 4, 11

5, 12

1, 13

6 13

5 12
VSS 7

4 7 11
VSS

MOTOROLA CMOS LOGIC DATA MC14001UB

21
 MC14011UB CIRCUIT SCHEMATIC MC14012UB CIRCUIT SCHEMATIC MC14023UB CIRCUIT SCHEMATIC
(1/4 of Device Shown) (1/2 of Device Shown) (1/3 of Device Shown)

14 VDD
14 VDD 14 VDD

3, 4, 10, 11 1, 13
6, 9, 10
1, 6, 8, 13 2, 9
5, 1, 11
2, 5, 9, 12 3, 10

7 VSS 4, 11 4, 2, 12

5, 12
3, 8, 13
7 VSS
7 VSS

MC14025UB CIRCUIT SCHEMATIC 16 16

VDD = 15 Vdc TA = + 25°C VDD = 15 Vdc Unused input
(1/3 of Device Shown) 14 Unused input 14 connected to
b
Vout , OUTPUT VOLTAGE (Vdc)

Vout , OUTPUT VOLTAGE (Vdc)

connected to a VSS.

I D, DRAIN CURRENT (mAdc)

14 VDD 12 12
VSS.
10 Vdc a One input only 10 Vdc a TA = + 125°C
1, 3, 11 10 b Both inputs 10
b TA = – 55°C
2, 4, 12 8.0 8.0 8.0
b a a b
8, 5, 13
6.0 6.0 6.0
9, 6, 10 5.0 Vdc 5.0 Vdc
15 Vdc
4.0 b a 4.0 4.0
a 10 Vdc a b
b
2.0 2.0 2.0
7 VSS 0 0 0
0 2.0 4.0 6.0 8.0 10 12 14 16 0 2.0 4.0 6.0 8.0 10 12 14 16
Vin, INPUT VOLTAGE (Vdc) Vin, INPUT VOLTAGE (Vdc)

Figure 2. Typical Voltage and Figure 3. Typical Voltage Transfer

Current Transfer Characteristics Characteristics versus
Temperature

0 10
c a 15 Vdc
b a
VGS = – 5.0 Vdc c
– 2.0 8.0
I D, DRAIN CURRENT (mAdc)

b VGS = 10 Vdc
I D, DRAIN CURRENT (mAdc)

a b
a TA = – 55°C
b TA = + 25°C c
– 4.0 6.0
c TA = + 125°C
a TA = – 55°C
c b TA = + 25°C
– 6.0 4.0 c TA = + 125°C
– 10 Vdc b
c a
– 8.0 b – 15 Vdc 2.0
b 5.0 Vdc
c
a a
– 10 0
– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0 2.0 4.0 6.0 8.0 10
VDS, DRAIN VOLTAGE (Vdc) VDS, DRAIN VOLTAGE (Vdc)

Figure 4. Typical Output Source Figure 5. Typical Output Sink

Characteristics Characteristics

MC14001UB MOTOROLA CMOS LOGIC DATA

22
 OUTLINE DIMENSIONS

L SUFFIX
CERAMIC DIP PACKAGE
CASE 632–08
ISSUE Y
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
14 9 Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
–B– 3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
1 7 4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
C L BODY.

INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 0.750 0.785 19.05 19.94
B 0.245 0.280 6.23 7.11
–T– C 0.155 0.200 3.94 5.08
SEATING
K D 0.015 0.020 0.39 0.50
PLANE F 0.055 0.065 1.40 1.65
G 0.100 BSC 2.54 BSC
F G N M J 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31
D 14 PL J 14 PL L 0.300 BSC 7.62 BSC
M 0_ 15_ 0_ 15_
0.25 (0.010) M T A S
0.25 (0.010) M T B S N 0.020 0.040 0.51 1.01

P SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06 NOTES:
ISSUE L 1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
14 8 MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
B FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
1 7 FLASH.
4. ROUNDED CORNERS OPTIONAL.
INCHES MILLIMETERS
A DIM MIN MAX MIN MAX
A 0.715 0.770 18.16 19.56
F L B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
C G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
J J 0.008 0.015 0.20 0.38
N K 0.115 0.135 2.92 3.43
L 0.300 BSC 7.62 BSC
SEATING
PLANE K M 0_ 10_ 0_ 10_
H G D M N 0.015 0.039 0.39 1.01

MOTOROLA CMOS LOGIC DATA MC14001UB

23
 OUTLINE DIMENSIONS

D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
–A– Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
14 8 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
–B– P 7 PL 5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
1 7
0.25 (0.010) M B M PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
MILLIMETERS INCHES
G R X 45 _ F DIM MIN MAX MIN MAX
C A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
–T– F 0.40 1.25 0.016 0.049
K M J G 1.27 BSC 0.050 BSC
SEATING D 14 PL
PLANE J 0.19 0.25 0.008 0.009
0.25 (0.010) M T B S A S K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided
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including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent
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*MC14001UB/D*
MC14001UB ◊ MOTOROLA CMOSMC14001UB/D
LOGIC DATA
24
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