5 Study unit 5

5 Combinational logic circuits

Overview of this study unit

When logic gates are connected together to produce a specified output for certain speci-
fied combinations of input variables, and no storage is involved, the resulting circuit
falls in the category of combinational logic. In combinational logic, the output level is
at all times dependent on the combination of input levels. This study unit covers the
analysis of combinational logic.

Learning outcome for this study unit

After completing this study unit, you should be able to

•• design basic combinational logic circuits

Assessment criteria for this study unit

•• Basic combinational circuits are designed from wording.
•• Truth tables are used in the design process and also to verify the logic.
•• The diagrams of combinational logic are implemented from the truth tables.
5.1 Implementation of NAND gates
1.  he NAND gate in figure 5.1 is wired in a particular manner that causes it to
T
behave like a NOT gate.

A A A A

Figure 5.1

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 2. The arrangement in figure 5.2 works like an AND gate.

A A
A.B A.B
B B

FIGurE 5.2

3. The arrangement in figure 5.3 behaves like an OR gate.

A+B A A+B
B

FIGurE 5.3

4 The arrangement in figure 5.4 behaves like a NOR gate.

A A
=A+B

A.B A.B

B
B

A
A+B
B

FIGurE 5.4

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5.2 Implementation of NOR gates

1. Figure 5.5 also behaves like a NOT gate.

A A A A

Figure 5.5

2. Figure 5.6 behaves like an OR gate.

A A
A+B A+B

B B

Figure 5.6

3. Figure 5.7 behaves like an AND gate.

A A

A
A.B A.B

B B

Figure 5.7

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4. Figure 5.8 behaves like a NAND gate.

A A

A.B A.B

B B

A
A.B

Figure 5.8

Example 27
Convert the following expression to NAND gates only:

Place a double bar

Applying De Morgan’s theorem:

AB.CD

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This can be implemented in figure 5.9 with NAND gates only.

A
A.B

B B

AB DC

C C

D.C

Figure 5.9

ACTIVITY 5.1
Write the output expression for the circuit in figure 5.10 below.

C X

Figure 5.10

ACTIVITY 5.2
Implement the logic circuit in the figure above using only NAND gates.

myUnisa activity
Log on to myUnisa, go to “Announcements”, and select the announcement that is
study unit 5. Answer the question given there. (This is a self-assessment activity – do
not submit it to the University.)

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Reference
Refer to the chapter “Combinational logic analysis” in the prescribed book, Digital
fundamentals, by Floyd.

Experiment
Objective:

To demonstrate how basic gates can be used to implement any logic function, and to
show how Boolean algebra and Karnaugh maps can be used to reduce logic circuits
to their minimum configuration.

Procedure:

Show how the expression below can be constructed using NAND gates only.

F = A.B + C.D + (Ā+C)

Write the modified expression below:

F = _________________________

Results of experiment

On the breadboard below, draw a wiring diagram to show how you built the circuit.

(Work in pencil in case you make a mistake.)

F = _________________________

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Complete the truth table below:

A B C D F

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

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