1.

1 System architecture

1.1.1 Architecture of the CPU

Homework
The Fetch–Execute cycle

Time: 15 mins

1 What are the four steps of the fetch phase?

Step 1 Copy PC to MAR

Step 2a Copy data from the RAM addressed by the MAR into the MDR

Step 2b Increment the pc by 1

Step 3 Copy contents of the MDR to the CIR

Control
CPU Bus

Arithmetic Logic Control unit RAM

Unit (ALU) (CU) ADDR DATA
00 LDA FF
01 ADD 7
02 SUB 4
ACC CIR MDR
Data
03 STA FE

Bus

FE 2
PC MAR
FF 0
Address
00
Bus

© Hodder & Stoughton Limited 2020 OCR GCSE Computer Science

 1.1 System architecture

2 On the attached sheet complete the table to show the steps of the program
shown above. For each instruction you will need to show the steps needed to
complete first the fetch, then the execute phases. The first one has been
completed for you.
The steps for the fetch phase are shown for you and the execute phase for the
first two operations. You need to work out what the steps for the execute phase
will be for the final two instructions.

© Hodder & Stoughton Limited 2020 OCR GCSE Computer Science

 1.1 Systems architecture

Program CPU Primary Storage

Instructio
PC ACC CIR MAR MDR 00 01 02 03 --- FE FF
Step
n
00 LDA FE ADD 7 SUB 4 STA FF --- 2 0
Fetch 1 00 00 LDA FF SUB 4 ADD 2 STA FE --- 2 0
Fetch 2a LDA FF ---
LDA FE

Fetch 2b 01 ---
Fetch 3 LDA FF
Operand to
FE
MAR
RAM to MDR 2

MDR to ACC 2 ---

Fetch 1 01 ---
ADD 7

Fetch 2a ADD 7 ---

Fetch 2b 02 ---
Fetch 3 ADD 7
Add operand
to ACC
9 ---

Fetch 1 02 ---
SUB 4

Fetch 2a SUB 4 ---

Fetch 2b 03 ---
Fetch 3 SUB 4

5 ---

Fetch 1 03 ---
Fetch 2a STA FF ---
STA FF

Fetch 2b 04 ---
Fetch 3 STA FF

FF

--- 5

© Hodder & Stoughton Limited 2020 OCR GCSE Computer Science