Digital Integrated Circuits

Ref: Digital Electroics – Morris Mano

Digital Systems: Principles and Applications –Tocci, Widmer & Moss

Analog and Digital Signal:

Analog signal 1 means continuous changes in some physical quantity. It has infinite values in the range of
minimum and maximum values. For example, our domestic line-voltage is 220V ac. It means the domestic
line voltage can take any values between +220V and -220V. If we focus on a given value, say, 180V,
someone may measure it 180.1V or, 180.08V or, 180.089V or, 179.99996V depending on the precision of
the measuring device.

Digital signal is consisted of a given number of defined values. It can take any one of these finite pre-defined
values. For example, if a signal is consisted of only two values 0V and +5V then it is a digital signal. Since
this signal can take any one of the two pre-defined values, it is known as binary signal. By the use of these
two values, binary signal can represent any values like analog signal.

Fig: Analog versus digital signal

Fig: Representation of a sinusoidal signal by digital signal

Comparison chart:

Issue Analog Digital

Signal Analog signal is a continuous signal which Digital signals are discrete time signals
represents physical measurements. generated by digital modulation.
Example: Human voice, our movements, Example: Digital devices computers,
tide in river/sea, atmospheric pressure, etc. digital clocks, etc.
Mathematical Uses discrete or discontinuous values to
Representation Uses continuous range of values to represent information. For example, in
represent information. binary system information uses only two
values – 0 and 1.
Graphical Commonly represented by sine/cosine Usually denoted by square waveforms or
representation waves. pulses.

1
Signal means some sort of information; means of communication.
 Noise Less affected since noises are analong in
Easily affected by noise. So, analog signal
immunity nature. Furthermore, noise can be
quality deteriorates easily during data
eliminated easily from the transmitted
transmission.
signal.
Bandwidth
There is no guarantee that digital signal
Analog signal processing can be done in processing can be done in real time and
real time and consumes less bandwidth consumes more bandwidth to carry out
the same information.
Memory
Stored in the form of wave signal. Stored in the form of binary bit.
Power
Digital instrument draws only negligible
Analog instrument draws large power.
power.
Errors Analog instruments usually have a scale Digital instruments are free from
which is cramped at lower end and give observational errors like parallax and
considerable observational errors. approximation errors.

Pulse shape:

Ideally a pulse sharply transits from the low level to the high level or vice-versa. In reality a pulse needs
some time to transit. The time required to make transition from the low level to its high level is called rise
time. It is measured by the time needed for the transition from 10% to 90% of the high level voltage.
Similarly, fall time is measured by the time needed for the pulse to fall from 90% to 10% of the voltage.
Duration/period of a pulse is defined as the time between the points when the leading and trailing edges are
at 50% of the high level voltage.

Fig: Non-ideal pulse (+ve pulse or active-HIGH pulse) and its characteristics

For an active-HIGH pulse, on-time is the time during which a pulse remains in the high level and the time
during which the pulse remains in the low level is called off-time. Pulse duration is the sum of these two
times. Duty cycle is the called the fraction of pulse period during which the pulse remains in the high level.
For a symmetrical waveform, duty cycle is 50%.

Fig: Duty cycle

IC:
IC stands for Integrated Circuit. ICs are electronic circuits consisted of resistors, diodes and transistors.
These circuits are fabricated on a single piece of semiconductor material, usually silicon, called substrate.
ICs are commonly called as chips. The chip is enclosed in a protective plastic or ceramic package from
which some metal pins come out for the connection in the circuit. One of the common types of package is
the DIP. It has two parallel rows of pins. These pins are numbered counterclockwise when viewed from the
top of the package with respect to an identifying notch or dot at one end of the package. ICs with many
functions demand more pins. Consequently, different surface mount packages (such as, QFP) have been
developed. A QFP or Quad Flat Package is a surface mount integrated circuit package with "gull wing"
leads extending from each of the four sides. Intel’s i7 core uses LGA (Land Grid Array) socket package.

Fig: DIP (dual-in-line package) IC Fig: QFP IC

Fig: LGA 1150 Socket Fig: Intel Core i7 Processor

IC Fabrication Technology:

Digital ICs are often categorized according to their circuit complexity as measured by the number of
equivalent logic gates on the substrate.

Name Year Transistors per chip Gates per chip

SSI (small-scale integration) 1964 1 to 10 1 to 12

MSI (medium-scale integration) 1968 10 to 500 13 to 99
LSI (large-scale integration) 1971 500 to 20,000 100 to 9,999
VLSI (very-large-scale integration) 1980 20,000 to 1,000,000 10,000 to 99,999
ULSI (ultra-large-scale integration) 1984 1,000,000 and more 100,000 and more

Wafer-scale integration (WSI) is a means of building very large integrated circuits that uses an entire
silicon wafer to produce a single "super-chip".
A system-on-a-chip (SoC or SOC) is an integrated circuit in which all the components needed for a
computer or other system are included on a single chip.

A three-dimensional integrated circuit (3D-IC) has two or more layers of active electronic components
that are integrated both vertically and horizontally into a single circuit. Communication between layers uses
on-die signaling, so power consumption is much lower than in equivalent separate circuits. Judicious use of
short vertical wires can substantially reduce overall wire length for faster operation.

Programmable logic devices (PLDs) are logic ICs whose functions can be programmed.

IC Logic Family:

 RTL (Resistor – Transistor Logic): This form of logic used resistors and transistors. It was first
introduced around 1962.

 DTL (Diode – Transistor Logic): This logic family or series used diodes on the inputs to create
functions such as AND and OR gates and then had transistors on the output.

 ECL (Emitter coupled logic): Also known as current-mode logic. The first ECL logic family to be
available in integrated circuits was introduced by Motorola as MECL in 1962.

 TTL (Transistor – transistor logic): Transistor–transistor logic uses bipolar transistors to form its
integrated circuits. Texas Instruments introduced 7400 Series TTL family in 1964. It became an
industry standard.

 PMOS (P-type metal–oxide–semiconductor logic): P-type metal-oxide-semiconductor logic uses

p-channel metal-oxide-semiconductor field effect transistors (MOSFETs) to implement logic gates
and other digital circuits. PMOS transistors operate by creating an inversion layer in an n-type
transistor body. This inversion layer, called the p-channel, can conduct holes between p-type
"source" and "drain" terminals.

 NMOS (N-type metal–oxide–semiconductor logic): N-type metal-oxide-semiconductor logic uses

n-type field effect transistors (MOSFETs) to implement logic gates and other digital circuits. These
nMOS transistors operate by creating an inversion layer in a p-type transistor body. This inversion
layer, called the n-channel, can conduct electrons between n-type "source" and "drain" terminals. The
n-channel is created by applying voltage to the third terminal, called the gate.

 CMOS (Complementary metal–oxide–semiconductor logic): CMOS logic gates use

complementary arrangements of enhancement-mode N-channel and P-channel Field effect transistor.
Since the initial devices used oxide-isolated metal gates, they were called CMOS (complementary
metal–oxide–semiconductor logic). In contrast to TTL, CMOS uses almost no power in the static
state (that is, when inputs are not changing). A CMOS gate draws no current other than leakage when
in a steady 1 or 0 state. When the gate switches states, current is drawn from the power supply to
charge the capacitance at the output of the gate. This means that the current draw of CMOS devices
increases with switching rate (controlled by clock speed, typically). The first CMOS family of logic
integrated circuits was introduced by RCA (Radio Corporation of America) as CD4000 COS/MOS,
the 4000 series, in 1968.

 BiCMOS (Bipolar complementary metal–oxide–semiconductor logic): It combines TTL and

CMOS logic families into one family.

Of these families, only ECL, TTL, NMOS, CMOS, and BiCMOS are currently still in widespread use. ECL
is used for very high-speed applications because of its price and power demands, while NMOS logic is
mainly used in VLSI circuits applications such as CPUs and memory chips.
TTL Logic Family (7400 series) 2:

Transistor–transistor logic (TTL) is a class of digital circuits built from bipolar junction transistors (BJT) and
resistors. It is called transistor–transistor logic because both the logic gating function (e.g., AND) and the
amplifying function are performed by transistors (contrast with resistor–transistor logic (RTL) and diode–
transistor logic (DTL)).

 Standard TTL3 chips require 𝑉𝐶𝐶 = + 5𝑉.

 A logic "1" is usually defined any voltage from 2 to 5V.
 A logic "0" is usually defined any voltage from 0 to 0.8V.
 A floating TTL (unconnected) input acts just like a logic 1 4.

TTL family has a number of subfamilies. The main differences in the subfamilies depend on the power
dissipation and switching speed.

 74 – Standard TTL: The original logic family had no letters between the "74" and the
part number. 10 ns gate delay, 10 mW dissipation, 4.75–5.25 V,
released in 1966.

 74L – Low-power TTL: Larger resistors allowed 1 mW dissipation at the cost of a very
slow 33 ns gate delay. Obsolete, replaced by 74LS or CMOS
technology. Introduced 1971.

 74H – High-speed TTL: 6 ns gate delay but 22 mW power dissipation. Used in 1970s era
supercomputers. Still produced but generally superseded by the
74S series. Introduced in 1971.

 74S – High-speed Schottky: Implemented with Schottky diode clamps at the inputs to prevent
charge storage, this provides faster operation than the 74 and 74H
series at the cost of increased power consumption and cost. 3 ns
gate delay, 20 mW dissipation, released in 1971.

 74LS – Low-power Schottky: Implemented using the same technology as 74S but with reduced
power consumption and switching speed. Typical 10 ns gate
delay, a remarkable (for the time) 2 mW dissipation, 4.75–5.25 V.

 74AS – Advanced Schottky: The next iteration of the 74S series with greater speed and fan-out
despite lower power consumption. Implemented using the 74S's
technology with "miller killer" circuitry to speed up the low-to-
high transition. 1.7 ns gate delay, 8 mW, 4.5–5.5 V.

 74ALS – Advanced low-power Schottky: Same technology as 74AS but with the speed/power
tradeoff of the 74LS. 4 ns, 1.2 mW, 4.5–5.5 V.

 74F– Fast TTL: Fairchild's version of TI's 74AS. 3.4 ns, 6 mW, 4.5–5.5 V.
Introduced in 1978.
2
TTL logic levels are different from those of CMOS – generally a TTL output does not rise high enough to be reliably recognized
as a logic 1 by a CMOS input. This problem was solved by the invention of the 74HCT family of devices that uses CMOS
technology but TTL input logic levels. These devices only work with a 5V power supply. They form a replacement for TTL,
although HCT is slower than original TTL (HC logic has about the same speed as original TTL).
3
For CMOS, VDD may range from +3 to +18V, although +5V is most often used when CMOS ICs are used with TTL ICs.
4
It does not mean that a given input should be left unconnected; it must be connected to the logic HIGH. Floating input may pick
up noise signal that could affect adversely the device’s performance. If a CMOS input is left floating, it may have disastrous
results. The IC may become overheated and eventually destroy itself.
7400 series IC numbering:

The most widely used is the 7400 series and all its derivatives. The derivation of these IC numbers is given
below:

It can be seen that this IC part number consists of a number of elements:

Manufacturer This code normally consists of two letters and is a code normally used by a
given manufacturer. SM is one used by Texas Instruments.

Temperature This is indicated by these two figures. 74 indicates (0°C to 70°C commercial and
54 military (-55°C to +125°C).

Logic series This is the sub-family. 7400 for example is the basic series, but there are many
others as defined above.

Device This indicates the device function / type. For example devices with 04 are hex
inverters, etc. They are the common across all sub-families.

Package code This is the package suffix. It is necessary to refer to the manufacturers datasheets
as these codes vary between manufacturers.

Nomenclature of Digital ICs:

 Voltage and Current parameters:

VIH(min): It symbolizes the HIGH Level Input Voltage. It means the minimum voltage for the
input to be at logical 1 state. For TTL family, it is 2.0V.

VIL(max): It stands for the LOW Level Input Voltage. It means the maximum voltage for the input
to be at logical 0 state. For TTL family, it is 0.8V.

VOH(min): It symbolizes the HIGH Level Output Voltage. It means the minimum voltage for the
output to be at logical 1 state. For TTL family, it is 2.4V.

VOL(max): It stands for the LOW Level Output Voltage. It means the maximum voltage for the
output to be at logical 0 state. For TTL family, it is 0.4V.

IIH: It symbolizes the HIGH Level Input Current. The current that flows into an input when
a specified HIGH-level voltage is applied to that input.

IIL: It stands for the LOW Level Input Current. The current that flows into an input when a
specified LOW-level voltage is applied to that input.

IOH: It symbolizes the HIGH Level Output Current. The current that flows out from an
output in the logical 1 sate under specified load conditions.
 IOL: It stands for the LOW Level Output Current. The current that flows out from an output
in the logical 0 sate under specified load conditions.

Fig: Convention of voltage and current in logic gates

 Fan-out:

The fan-out (also called loading factor) is defined as the maximum number of logic inputs that an
output can drive reliably. For example, a logic gate that is specified to have a fan-out of 10 can drive
10 logic inputs. If this number is exceeded, the output logic-level voltages cannot be guaranteed.

It is calculated from the output current (IOH or, IOL) of an IC and the input current (I IH or, I IL) of the
other IC which is going to be driven by the first IC. It is calculated by either of the following
equations, whichone is smaller:
𝐼𝑂𝐻
𝐹𝑎𝑛 𝑜𝑢𝑡 =
𝐼𝐼𝐻

𝐼𝑂𝐿
𝐹𝑎𝑛 𝑜𝑢𝑡 =
𝐼𝐼𝐿

Fig: Combination of Logic gates – Fan out.

For standard TTL gates, 𝐼𝑂𝐻 = 400 𝜇𝐴, 𝐼𝐼𝐻 = 40 𝜇𝐴, 𝐼𝑂𝐿 = 16 𝜇𝐴, 𝐼𝐼𝐿 = 1.6 𝜇𝐴

𝐼𝑂𝐻 400
𝐹𝑎𝑛 𝑜𝑢𝑡 = = = 10
𝐼𝐼𝐻 40

𝐼𝑂𝐿 16
𝐹𝑎𝑛 𝑜𝑢𝑡 = = = 10
𝐼𝐼𝐿 1.6

 Propagation Delays:

A logic signal always experiences a delay in going through a circuit. There are two delay times
which are defined as follows:
 tPLH: Propagation delay time LOW to HIGH is the delay time in going form logical 0 to 1 state.

tPHL: Propagation delay time HIGH to LOW is the delay time in going form logical 1 to 0 state.

These delay times are measured by the time between 50% points on the input and output transitions.
These two delay times may not be equal to each other. These delay times are a measure of relative
speed of logic circuits. For example, a logic circuits with delay time 10 ns is faster than the circuits
with delay time 20 ns.

Fig: Propagation delay.

 Power Dissipation/Requirement:

IC is an active device and so, it needs electrical power to drive itself. This power is supplied through
the power pins labeled by VCC for TTL and VDD for MOS ICs. Power dissipated for an IC is given by

𝑃𝐷 = 𝐼𝐶𝐶 × 𝑉𝐶𝐶

Here, ICC (or, IDD) is the current drawn from the VCC (or, VDD) supply. For many ICs, the current
drawn from the supply varies depending on the logic states of the circuits. For example, if all the
outputs are HIGH, the current drawn from the VCC supply is ICCH and it is ICCL if all the outputs are
LOW. Then, the average of these two currents is used in the calculation of the power dissipation.

1
𝐼𝐶𝐶 (𝑎𝑣𝑔) = (𝐼 + 𝐼𝐶𝐶𝐿 )
2 𝐶𝐶𝐻

Fig: ICCH and ICCL

 Noise Immunity:
 Stray electric andmagnetic fields can induce voltages on the connecting wires between logic circuits.
These unwanted, spurious signals are called noise. This noise may cause the voltage at the input to
drop below VIH(min) or rise above VIL(max), which could produce unpredictable operation. The
Noise immunity refers to the circuit’s ability to tolerate the noise without causing spurious changes
in the output voltage. A quantitative measure of noise immunity is called noise margin.

Fig: dc Noise Margins

The HIGH-state noise margin VNH is defined as

𝑉𝑁𝐻 = 𝑉𝑂𝐻 min − 𝑉𝐼𝐻 (min)

The LOW-state noise margin VNL is defined as

𝑉𝑁𝐿 = 𝑉𝐼𝐿 max − 𝑉𝑂𝐿 (max)

For standard TTL ICs, 𝑉𝑂𝐻 (min) = 2.4𝑉, 𝑉𝐼𝐻 (min) = 2.0 𝑉, 𝑉𝑂𝐿 (max) = 0.4𝑉, 𝑉𝐼𝐿 (max) =
0.8𝑉
𝑉𝑁𝐻 = 𝑉𝑂𝐻 min − 𝑉𝐼𝐻 min = 2.4𝑉 − 2.0𝑉 = 0.4𝑉

𝑉𝑁𝐿 = 𝑉𝐼𝐿 max − 𝑉𝑂𝐿 max = 0.8𝑉 − 0.4𝑉 = 0.4𝑉

 Current-Sourcing and Current-Sinking Action:

Logic families can be described by how current flows between the output of one logic circuit and the
input of another. As shown in the figure below, when the output of gate-1 is HIGH, it supplies
current I IH to the input of gate-2, which acts essentially as a resistance to ground. Thus, the output of
gate-1 is acting as a source of current for the gate-2 input. This is called the current-sourcing action.

Fig: Current-sourcing action

Current-sinking action is illustrated in the figure below. Input circuitry of gate-2 is represented as a
resistance tied to +VCC — the positive terminal of a power supply. When gate-1 output goes LOW,
current will flow from the input circuit of gate-2 back through the output resistance of gate-1, to
ground. In other words, in the LOW state, the circuit output that drives the input of gate-2 must be
able to sink a current, I IL , coming from that input.
 Fig: Current-sinking action

Bipolar Transistor Characteristics 5:

Fig: npn transistor CE configuration

Table: Typical npn silicon transistor parameters

BE - Junction Region VBE VCE Current

IB = 0
Reverse biased Cut-off <0.6 V Open circuit
IC = 0
IB  hfe/IC
Saturation 0.7 – 0.8 V 0.2 V
IC = VCC/RC
Forward biased
IC = hfe I B
Active 0.6 – 0.7 V 0.8 V – VCC
hfe  50

Circuit Construction and Operation of NAND Gate 6:

The below figure shows the basic construction of a standard TTL NAND gate. A multiple-emitter transistor
(Q1) is used for the inputs of the NAND gate. Usually a totem-pole arrangement of two transistors (Q 3 and
Q4) is used for the output.

5
Most TTL transistors are silicon-made npn transistors.
6
Standard TTL NAND and AND gates use multiple-emitter transistor or multiple diode junction at the inputs and NOR and OR
gates use separate input transistors.
 Fig-(a): Equivalent operation of Q1 transistor Fig-(b): Standard TTL NAND gate with totem-pole output

Circuit operation of NAND gate: Case – LOW output

The NAND gate has LOW output when all the inputs are HIGH. Input transistor Q 1 acts as the isolate diodes
as shown in the above figure-(a). Diodes D2 and D3 represent the two BE-junctions of Q1, and D4 is the
base-collector BC-junction. When both the inputs are at HIGH (i.e., +5V), the diodes D 2 and D3 become
reverse-biased7 and the diode D4 become forward-biased. So, the power supply VCC causes a current flow
into the base of Q2 through R1 and D4. Transistor Q2 starts to conduct current and becomes in saturation very
soon. So, a collector current flows from VCC to the emitter of Q2 through R2. This current turns on Q4 and so,
the VCE of Q4 becomes very low8 (0.4V).

Fig: Circuit’s state for LOW output

7
Alternatively, we can show that the diodes D2 and D3 are reverse-biased when inputs are at HIGH. We know that when both
inputs are at HIGH, then D4, BE junctions of Q2 and Q3 become forward-biased. Then, forward voltage across each of D4, BE
junctions of Q2 and Q3 is 0.7V. So, the voltage at point Y becomes 30.7V=2.1V relative to ground. Minimum input voltage at
HIGH state is 2.4V. So, the diodes D2 and D3 become reverse-biased when inputs are at HIGH.
8
Q4’s ON-state resistance is low (1 to 25).
Q2’s emitter is at 0.7V relative to ground due to Q 4’s BE forward voltage. Again, Q2’s collector is at 0.1V
relative to its emitter because of saturation of Q 2 . So, Q2’s collector is at 0.8V relative to ground. This
voltage is not enough to make Q3 and D1 forward-biased. In fact, D1 is used to keep Q3 OFF in this situation.

With Q3 OFF, there is no current in the output terminal ―X‖ from the power supply VCC through R4. So, the
VCE of Q4 becomes the output ―X‖ and it is a very low voltage.

Circuit operation of NAND gate: Case – HIGH output

The NAND gate has HIGH output when, at least, one of the inputs is LOW. Let the input B is at LOW. Then
the diode D3 becomes forward-biased and so, a current flows from VCC to ground through R1 and D3. The
forward voltage across D3 makes the point ―Y‖ at 0.7V with respect to ground. This voltage is not enough to
make forward-bias D4 and the BE junction of Q2 sufficiently for conduction. Since Q 2 is OFF, there is no
base current for Q4 and so, Q4 also becomes OFF.

Again, there is no collector current through R2 because of Q2 OFF. So, the voltage at the base of Q 3 becomes
sufficiently large to forward-bias Q3 and D1, so that Q3 will conduct current. This current depends on the
load at the output ―X‖. Actually, Q 3 acts as an emitter follower because output terminal ―X‖ is essentially at
its emitter. With no-load at ―X‖, upper part of the forward-biased D1 is at 0.7V relative to its lower end and
the base of Q3 is also at 0.7V relative to emitter. So, voltage at ―X‖ with no-load becomes (5 – 0.7 – 0.7)V or
3.6V, approximately. With load this voltage decreases but should remain larger than 2.4V9.

Fig: Circuit’s state for HIGH output

Totem-Pole10:

A totem pole consists of a PNP and NPN transistor arranged emitter to emitter, with their bases coupled
together. The output signal is taken from where the emitter of the NPN transistor and the collector of the
PNP transistor meet.

9
With load this voltage decreases because the load draws emitter current from Q 3, which draws base current through R 2, thereby
increasing the voltage drop across R2.
10
Totem poles are monumental sculptures carved on poles, posts, or pillars with symbols or figures made from large trees, mostly
western red cedar, by indigenous peoples of the Pacific Northwest coast of North America (northwestern United States and
Canada's western province, British Columbia).
A push–pull output is a type of electronic circuit that uses a pair of active devices that alternately supply
current to, or absorb current from, a connected load. Push–pull outputs are present in TTL and CMOS digital
logic circuits and in some types of amplifiers, and are usually realized as a complementary pair of
transistors, one dissipating or sinking current from the load to ground or a negative power supply, and the
other supplying or sourcing current to the load from a positive power supply.

Fig: Circuit’s state for HIGH output

Advantage of Totem-Pole Output:

NAND gate can be constructed without using the transistor Q 3 and the diode D1; in such case the resistor R4
should be connected directly with the collector of Q 4. With this arrangement, there will be very high current
(5V/13040mA) in the saturation state of Q4. With Q3 in the circuit, there will be no current through
R4=130. So, totem-pole configuration keeps the circuit power dissipation low in the LOW output state.

In the case of HIGH output state, Q 3 acts as an emitter follower with its low output impedance (typically
10). This low impedance provides low time constant for charging up any capacitive load at the output. This
active pull-up provides very first rise-time waveforms at TTL outputs.

Transition times from cut-off to saturation are not same for Q 3 and Q4; Q 4 turns off more slowly than Q3
turns on. So, there is a period of a few nanoseconds during which both the transistors are conducting and a
relatively large current (30 to 40 mA) is drawn from the VCC power supply.

Current-Sinking action of TTL NAND gate:

A TTL output acts as a current sink in the LOW state because it
receives current from the input of the gate that it is driving. In
the LOW output state, Q4 of the driving gate is ON and
essentially ―shorts‖ point X to ground. The LOW voltage at X
forward-biases the emitter–base junction of Q1 and a current
flows back from the power supply of the load gate to ground
through Q4. Thus, Q4 performs the current-sinking action; it
draws current from the input current (I IL) of the load gate. So,
Q4 is called the current-sinking transistor or the pull-down
transistor because it brings the output voltage down to its low
state.

Fig: Current-sinking action

Current-Sourcing action of TTL NAND gate:

A TTL output acts as a current source in the HIGH state.

Transistor Q 3 supplies the input current (I IH) required
by Q1 of the load gate. This current is a small reverse-bias
leakage current (typically 10A). Q3 is often called the
current-sourcing or pull-up transistor. In more modern TTL
series, the pull-up circuit is madeup of two transistors.

Fig: Current-sourcing action

Open Collector output TTL NAND gate:

Fig: Open collector TTL NAND gate

In the open-collector output arrangement, there is no resistor (R4 ) between the power supply VCC and the
collector of the output transistor Q 4.

When all the inputs are HIGH, then Q 4 becomes in saturation and so, the output becomes LOW (0.4V). But
for the conduction of saturation current, a load resistance (R L) should be connected between the power
supply VCC and the collector of the output transistor Q 4.

When anyone of the inputs is LOW, then Q 4 becomes cut-off. So, the output becomes open circuit if any
external resistor is not connected between the power supply VCC and the collector of the output transistor Q 4.
If an external resistor (R L) is connected, then the output voltage becomes HIGH equal to VCC.

MOSFET:

MOSFET11 stands for Metal Oxide Semiconductor Field Effect Transistor. It is also known as the Insulated
Gate FET (IGFET) because the Gate of this type FETs is insulated by silicone dioxide (glass) from the main
semiconductor body. Isolation of the Gate makes the input resistance of MOSFET extremely high – in the
region of Mega-Ohms. As the Gate terminal is isolated from the main current carrying channel ―NO current
flows into the gate‖.

Similar to the JFET, the MOSFET also acts like a voltage controlled resistor i.e., the current flowing through
the main channel between the Drain and Source is proportional to the input voltage (in the Ohmic region).
Also like the JFET, the MOSFETs very high input resistance can easily accumulate large amounts of static
charge resulting in the MOSFET becoming easily damaged unless carefully handled or protected.

Fig: N-Channel MOSFET

The construction of the Metal Oxide Semiconductor FET is very different to that of the Junction FET. Both
the Depletion and Enhancement type MOSFETs use an electrical field produced by a gate voltage to alter the
flow of charge carriers, electrons for n-channel or holes for P-channel, through the semiconductive drain-
source channel. The gate electrode is placed on top of a very thin insulating layer and there are a pair of
small n-type regions just under the drain and source electrodes.

11
The MOSFET is a voltage controlled field effect transistor that differs from a JFET in that it has a ―Metal Oxide‖ Gate
electrode which is electrically insulated from the main semiconductor n-channel or p-channel by a very thin layer of insulating
material usually silicon dioxide (SiO2 ; 𝜌 = 1013 Ω𝑚 𝑎𝑡 20°𝐶 ), commonly known as glass.
The JFET must be biased in such a way as to reverse-bias the Gate-Source pn-junction. With an insulated
gate MOSFET device no such limitations apply so it is possible to bias the gate of a MOSFET in either
polarity, positive (+ve) or negative (-ve).

This makes the MOSFET device especially valuable as electronic switches or to make logic gates because
with no bias they are normally non-conducting and this high gate input resistance means that very little or no
control current is needed as MOSFETs are voltage controlled devices. Both the p-channel (PMOS) and the
n-channel (NMOS) MOSFETs are available in two basic forms – the Enhancement type and the Depletion
type.

 Depletion Type – the transistor requires the Gate-Source voltage, (VGS) to switch the device ―OFF‖.
The depletion mode MOSFET is equivalent to a ―Normally Closed‖ switch.
 Enhancement Type – the transistor requires a Gate-Source voltage, (VGS) to switch the device
―ON‖. The enhancement mode MOSFET is equivalent to a ―Normally Open‖ switch.

The four MOSFET symbols above show an additional terminal called the Substrate and is not normally used
as either an input or an output connection but instead it is used for grounding the substrate. It connects to the
main semiconductive channel through a diode junction to the body or metal tab of the MOSFET. Usually in
discrete type MOSFETs, this substrate lead is connected internally to the source terminal. When this is the
case, it is omitted from the symbol for clarification.

The line between the drain and source connections represents the semiconductive channel. If this is a solid
unbroken line then this represents a ―Depletion‖ (normally-ON) type MOSFET as drain current can flow
with zero gate potential. If the channel line is shown dotted or broken it is an ―Enhancement‖ (normally-
OFF) type MOSFET as zero drain current flows with zero gate potential. The direction of the arrow
indicates whether the conductive channel is a p-type or an n-type semiconductor device.

Enhancement MOSFET:

The more common Enhancement-mode MOSFET or eMOSFET, is the reverse of the depletion-mode type.
Here the conducting channel is lightly doped or even undoped making it non-conductive. This results in the
device being normally ―OFF‖ (non-conducting) when the gate bias voltage, VGS is equal to zero. The circuit
symbol shown above for an enhancement MOS transistor uses a broken channel line to signify a normally
open non-conducting channel.

For the n-channel enhancement MOS transistor a drain current will only flow when a gate voltage ( VGS ) is
applied to the gate terminal greater than the threshold voltage ( VTH ) level in which conductance takes place
making it a transconductance device.

The application of a positive (+ve) gate voltage to a n-type eMOSFET attracts more electrons towards the
oxide layer around the gate thereby increasing or enhancing (hence its name) the thickness of the channel
allowing more current to flow. This is why this kind of transistor is called an enhancement mode device as
the application of a gate voltage enhances the channel.

Increasing this positive gate voltage will cause the channel resistance to decrease further causing an increase
in the drain current, ID through the channel. In other words, for an n-channel enhancement mode MOSFET:
+VGS turns the transistor ―ON‖, while a zero or -VGS turns the transistor ―OFF‖. Then, the enhancement-
mode MOSFET is equivalent to a ―normally-open‖ switch.

The reverse is true for the p-channel enhancement MOS transistor. When VGS = 0 the device is ―OFF‖ and
the channel is open. The application of a negative (-ve) gate voltage to the p-type eMOSFET enhances the
channels conductivity turning it ―ON‖. Then for an p-channel enhancement mode MOSFET: +VGS turns the
transistor ―OFF‖, while -VGS turns the transistor ―ON‖.
Enhancement-mode MOSFETs make excellent electronics switches due to their low ―ON‖ resistance and
extremely high ―OFF‖ resistance as well as their infinitely high input resistance due to their isolated gate.
Enhancement-mode MOSFETs are used in integrated circuits to produce CMOS type Logic Gates and
power switching circuits in the form of as PMOS (P-channel) and NMOS (N-channel) gates. CMOS actually
stands for Complementary MOS meaning that the logic device has both PMOS and NMOS within its design.

MOSFET VGS < 0 VGS = 0 VGS > 0

P-Channel ON ON OFF
Depletion
N-Channel OFF ON ON
P-Channel ON OFF OFF
Enhancement
N-Channel OFF OFF ON

MOSFET Switch:

NMOS: Enhancement type N-Channel MOSFET or NMOS normally acts as an OPEN switch i.e., the
device is OFF. So, if VGS = 0V, the drain to source channel behaves as an open circuit due to very high (
1010 ) channel resistance. As VGS is made positive (gate positive relative to source) and above than a
threshold voltage (VTH; typically it is +1.5V), the NMOS begins to conduct. If VGS > +2V, NMOS operates
in the saturation region, known as ON mode. Then the maximum drain current I D flows from drain to source.
The channel resistance also drops to low R DS(ON)  1k and it appears as a closed switch. Then the output
voltage becomes very low VDS(ON)  0.2 V. Thus, NMOS act as a switch.

VGS NMOS
0V OFF
+5V ON
 Fig: NMOS Switching Action

PMOS: Similar to NMOS, Enhancement type P-Channel MOSFET or PMOS normally acts as an OPEN
switch i.e., the device is OFF. So, if VGS = 0V, then PMOS becomes OFF.

In PMOS, the Gate should be negative with respect to the Source i.e., V GS < 0. This is accomplished by
maintaining the Source at a fixed positive voltage (+5V, for example) and the Drain at 0V (ground). And, the
input voltage is applied between the Gate (positive with respect to drain) and the Drain (ground) as shown in
the figure below.

VGD VGS NMOS

+5V 0V OFF
0V -5V ON
 Fig: PMOS Switching Action

CMOS 12 Inverter:

Fig: Enhancement type CMOS Inverter (squares labeled by P and N denote PMOS and NMOS,
respectively)

12
CMOS stands for Complementary MOSFET. CMOS is consisted of PMOS and NMOS. Although CMOSs are more complex
than NMOS or PMOS, they are faster and so, preferred to fabricate the ICs.
The CMOS Inverter has two MOSFETs in series. Source of the PMOS is connected to VDD and Source of the
NMOS is connected to ground (VSS = 0V with respect to ground). Gates of the two devices are connected
together as a common input. Drains are also tied together as the common output.

Input HIGH:

Input voltage is Vin = +VDD . Gate of Q1 (PMOS) is at 0V with respect to its Source. So, Q 1 acts as OPEN
circuit from its source and to drain. On the other hand, Gate of Q2 (NMOS) is at +VDD with respect to its
Source. So, Q2 acts as CLOSED circuit from its source and to drain. Output VOUT is equal to VDS of Q2 ;
which is very low voltage.

Input LOW:

Input voltage is Vin = 0V. Gate of Q1 (PMOS) is at –VDD with respect to its Source. So, Q1 acts as CLOSED
circuit from its source and to drain. On the other hand, Gate of Q 2 (NMOS) is at 0V with respect to its
Source. So, Q2 acts as OPEN circuit from its source and to drain. Output V OUT is equal to VDD – VDS of Q1;
which is approximately equal to +VDD because VDS of Q1 is less than 0.2V.

Important to remember:

Input PMOS NMOS

LOW ON OFF
HIGH OFF ON

CMOS NAND Gate:

Q1 Q2

Q3

Q4

Fig: Enhancement type CMOS NAND Gate (squares labeled by P and N denote PMOS and
NMOS, respectively)

NAND gate has HIGH output if anyone of its inputs is LOW and LOW output if all the inputs are HIGH.
LOW output:

A NAND gate has LOW output if all the inputs are HIGH. Let’s consider that input voltage is Vin = +VDD at
the both inputs A and B. Gates of Q1 and Q2 PMOSs are at 0V with respect to their Sources. So, Q1 and Q2
act as OPEN circuit from its source and to drain. On the other hand, Gates of Q3 and Q4 are at +VDD with
respect to their Sources. So, Q3 and Q4 act as CLOSED circuit from its source and to drain. Output VOUT is
equal to sum of the voltages VDS of Q3 and Q4; which is very low voltage.

Q1 Q2
OFF OFF

Q3
ON

Q4
ON

Fig: Enhancement type CMOS NAND Gate (squares labeled by P and N denote PMOS and
NMOS, respectively)

HIGH output:

NAND gate has HIGH output if at least anyone of its inputs is LOW. Let’s consider that the input voltages
are Vin = +VDD at A and Vin = 0V at B. Gates of Q1 (PMOS) and Q 4 (NMOS) are at 0V with respect to their
Sources. So, Q1 and Q4 act as OPEN circuit from its source and to drain. On the other hand, Gates of Q 2
(PMOS) and Q3 (NMOS) are at -VDD and +VDD with respect to their Sources. So, Q2 and Q4 act as CLOSED
circuit from its source and to drain. Output VOUT is equal to the voltage VDD , approximately; which is HIGH
voltage.
 Q1 Q2
OFF ON

Q3
ON

Q4
OFF

Fig: Enhancement type CMOS NAND Gate (squares labeled by P and N denote PMOS and
NMOS, respectively)

CMOS NOR Gate:

Q1

Q2

Q3 Q4

Fig: Enhancement type CMOS NOR Gate (squares labeled by P and N denote PMOS and
NMOS, respectively)

HIGH output:

A NOR gate has HIGH output if all the inputs are LOW. Let’s consider that input voltage is Vin = +VDD at
the both inputs A and B. Gates of Q 1 and Q2 PMOSs are at -VDD with respect to their Sources. So, Q1 and Q2
act as CLOSED circuit from its source and to drain. On the other hand, Gates of Q 3 and Q4 are at 0V with
respect to their Sources. So, Q3 and Q4 act as OPEN circuit from its source and to drain. Output VOUT is
equal to the voltage VDD - VDS(ON) Q1 - VDS(ON) Q2  VDD because VDS(ON)  0.2V for each Q1 and Q2.

Q1
ON
LOW

Q2
ON
LOW

Q3 Q4
OFF OFF

Fig: Enhancement type CMOS NOR Gate (squares labeled by P and N denote PMOS and
NMOS, respectively)

LOW output:

A NOR gate has LOW output if at least one of the inputs are HIGH. Let’s consider that the input voltages
are Vin = +VDD at A and Vin = 0V at B. Gates of Q1 (PMOS) and Q 4 (NMOS) are at 0V with respect to their
Sources. So, Q1 and Q4 act as OPEN circuit from its source and to drain. On the other hand, Gates of Q 2
(PMOS) and Q3 (NMOS) are at -VDD and +VDD with respect to their Sources. So, Q2 and Q4 act as CLOSED
circuit from its source and to drain. Output VOUT is equal to the voltage VDS of the ON Q3 ; approximately
equal to 0.2V. So, VOUT is LOW.
 Q1
OFF
HIGH

Q2
ON
LOW

Q3 Q4
ON OFF

Fig: Enhancement type CMOS NOR Gate (squares labeled by P and N denote PMOS and
NMOS, respectively)

Advantages of MOS over TTL:

 Fabrication technology is relatively simple and inexpensive.

 Size of MOS devices is small than that of TTL devices.
 MOS devices can be used as resistors. Conventional resistors take huge space in IC. So, MOS
resistors save a lot of space in a IC.
 MOS devices consume very little power.

So, MOS ICs can accommodate a much larger number of circuit elements on a single chip than bipolar ICs.
As a result, LSI and VLSI technology dominantly use MOS ICs.

The principle disadvantage of MOS devices is their susceptibility to static-electric damage.