UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER

PROJECT OBJECTIVE:

Design and implementation of UART, which is used

for serial data communication

PIN DIAGRAM:

clk

BR_clk
dtr
rst
rts
cs
wr Txd_
u
rd intr
3
add 8 Dout_u
cts
dsr UART
Rxd_
u_
Din_u 8
PIN DESCRIPTION :

PIN PIN PINDESCRIPTION

IRECTION
Clk In System clock may equal or greater
than br_clk
Br_clk In Baud rate generator clock
Rst In Asynchronous reset, active high
Cs In Chip select ,active high
Wr In Write control from the processor(data
&control information)
Rd In Read control from the processor(data
&status information)
Add In(2:0) To select the control and status
registers to read the status
Cts In CLEAR TO SEND (active high)Is
aknowldgement from the serial
device
‘1’- the serial device is ready to
recive the data
‘0’- the serial devece is not redy to
receive the data
Dsr In DATA SET READY (active high)
‘1’- the serial device is ready to start
communicate
‘0’- the seril deveice is not ready to
communicate
Rxd_u In Serial receive data from the serial
devece
Din_u In(7:0) Is the data or control information
from the processot
Rts Out REQUEST TO SEND(active high)
to the seroal device
‘1’- transmitter is ready to send the
data
‘0’- transmitter is not ready to send
the data
 Dtr Out DATA TREMINAL READY (active
high)
‘1’- pc is ready to communicate
‘0’-pc is not ready to communicate
Intr Out Interrupt line to the pc depending on
the status of the receiver and
transmitter
Txd_u Out Serial transmitt data
Dout_u Out(7:0) Is data or status information to the
processor

PIN DIAGRAM OF THE TRANSMITTER:

bclk
rst
Clk_en txd
Data_ready
Parity_en
busy
Odd_even
Stop_b TRANSMITTER

Num_bits 2

din 8

PIN DESCRIPTION OF TRANSMITTER:

 PIN PIN DIRECTION PIN DESCRIPTION

Bclk In The clock equal to the baud rate

Rst In Asynchronous reset, active high
Clk_en In A Clock enable
Data_ready In Data ready is connected to the
inversion of TRANSMITTER
FIFO empty pin
Parity_en In Parity enable
Odd_even ‘1’- parity generated is even parity
‘0’- parity generated is odd parity
Stop_b in ‘0’- one stop bit will sent with the
data
‘1’- two stop bits will sent with
data
Num_bits In (1:0) The number of data transfer will
be
5,6,7,or 8 when 00,01,10,11
respectively
Din In (7:0) Input data which is to transmit
TX Out Serial transmit data

Busy Out ‘1’- when transmitting

‘0’-when idle

PIN DIAGRAM OF RECEIVER:

Bclk16
Data_rcvd
rst
Frame_err
Clk_en
Par_en Par_err
RECEIVER
Odd_even
Num_bits 8 D_out
Stop_b
PIN DESCRIPTION OF RECEIVER:
PIN PIN PIN DIRECTION
DIRECTION
Bclk16 In Clock equal to the 16Xbaud rate
generator
Rst In Asynchronous reset, active high
Clk_en In A clock enable
Par_en In Parity enable
Odd_even In ‘1’- parity need to check for
even parity
‘0’- parity need to check for odd
parity
Stop_b In ‘0’- stop bits to receive is one
‘1’ –stop bits need to receive is
two
Num_bits In(1:0) The number of data transfer will
be
5,6,7,or 8 when 00,01,10,11
respectively
Data_rcvd Out Received data byte ready line
Frame_err ‘1’- the received stop bit is
wrong
‘0’- the received stop bit is right
Par_err Out The received parity bit is wrong
Dout_u Out (7:0) The output data

BASIC UART DATA PACKET:

T

Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop Stop

‘0’ BIT(1) bit2(1)

Ts

T – 1 / baud rate.
 Ts – T/16. Sampling incoming data
Bit center.
BLOCK DESCRIPTION:

Divisible Baud rate Clk

latch generator
Registers Rst

Bclkx
8

Receiver
Line status control
register logic

Line
control
register

Serial to Rxd
parallel
Rx_FIFO converter

Transmitter
FIFO control
control logic
register bclk

txd
Parallel to
TX FIFO serial
converter
 Interrupt
enable IntR
register

Interrupt
control
Interrupt logic
identificati
on register

RTS
Modem
status DSR
register
DTR

Modem CTS
signal logic

Modem
control
register

The UART is a universal asynchronous receiver and transmitter. The UART

consists of four mail blocks.

• Baud rate generator

• Transmitter block
• Receiver block
• Register set

BAUD RATE GENERATOR:

The baud rate generator takes the baud rate clock (BR_clk) from
crystal. And produces the clocks for the transmitter (Bclk) and receiver (BclkX16)
by dividing the baud rate clock by divisor values which depending on the desired
baud rate.
 Baud rate divisor value = freq of baud rate clk(BR_clk)/ desired baud rate X 16

Transmitter clock = desired baud rate

Receiver clock = desired baud rate X 16

TRANSMITTER BLOCK:

The transmitter block consists of

1. BUFFR (TX_FIFO), 2. PISO,

3. PARITY GENERATOR, 4. TRANSMITTER CONTROL LOGIC.

The input clock to the transmitter is equal to the baud rate (Bclk). The TX will transmit the
data at desired baud rate. First the transmitter is in the idle state. In the idle state it will
send the 1’s. When the serial device is ready to receive the data the processor send the
data to the buffer at its frequency. When at least one byte is available in the buffer it makes
the data ready high, first it sends the start bit, after the byte goes to the parallel to shift
register. the shift register shifts the data out at baud rate. If the parity enable bit is high, the
parity bit is also transmits after the MSB of data depending on the odd –or-even control.
After the parity one or two stop bits will transmit. When the buffer is empty it will send the
interrupt by making making the status register bit 0 high.

RECEIVER BLOCK:

The receiver block consists of

1. BUFFER (RX_FIFO), 2. SIPO

3. PARITY CHECKER, 4. RECEIVER CONTROL LOGIC

The input clock to the receiver is equal to the baud rate X

16(BclkX16). The receiver receives the data at the rate equal to the transmitter
baud rate. But receiver samples the every data, parity and stop bits at the baud
rate X 16. When the receiver detects the start bit when the transmission from
logic 1 to logic 0. Once the start-bit is detected, the next data bit’s "center" can be
assured to be 24 ticks later. From then on, every next data bit center is 16 clock
ticks later. Once the start bit is detected, the subsequent data bits are assembled
in a serial in parallel out shift register. The par_err and frame err conditions
maybe generated if the parity/stop bits are incorrect or missing.

When the one byte received completely it makes the data_rcvd output high. And
then this byte will go to the Rx buffer and simultaneously the status of par_err
and frame _err will store in the MSB bits of the Rx buffer. If the Rx buffer is
 already full the byte in the shift register will overwrite by the next byte. This is the
overrun error.

REGISTERS DESCRIPTION:

REGISTER ADRESS DECODING:

A2 A1 A0 READ MODE WRITE MODE

0 0 0 RX_FIFO RX_FIFO

0 0 1 IER

0 1 0 IIR FCR

0 1 1 LCR

1 0 0 MCR

1 0 1 LSR

1 1 0 MSR

INTERNAL REGISTERS BITS FUNCTIONS:

 REGISTER BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 7 BIT 8

IER Enable Enable Enable Enable 0 0 0 0

Receive Txmit Receive Modem
data FIFO line status
available empty status interrupt
interrupt interrupt interrupt

IIR Interrupt Interrupt Interrupt Interrupt 0 0 0 0

status priority priority priority

FCR Enable Receive Transmit 0 0 0 Fifo’s Fifo’s

fifo’s FIFO FIFO trigger trigger
reset reset levels level
(MSB) (LSB)
LCR Word Word No. Of Parity Even 0 0 0
length length Stop bits enable or
select select selection odd
(MSB) (LSB) parity

MCR To DTR To RTS 0 0 0 0 0 0

LSR Data ready Over Parity Framing 0 Transmitter Transmitter 0

rx_fifo run error error FIFO is empty
empty=’0’; error empty
MSR
CTS has
changed 0 0
its state DSR 0 0 0
has 0
changed
its state

1.INTERRUPT ENABLE REGISTER:

This register is used to enable or disable the interrupts (rx_fifo, tx_fifo, line
status, modem status interrupts) at the start of communication. The interrupts
will generate when the corresponding interrupt enable bit in this register
high.
2. INTERRUPT IDENTIFICATION REGISTER:

This register will tell about interrupts status and interrupt

prioritization. BIT0 indicates about interrupt in pending or UN pending. The
next three bits shows prioritization. The next bits are ignored. Whenever
there is a high on interrupt, the processor will read this register contents and
after depending on the interrupt priority the processor will read the line or
modem status registers.

3. FIFO CONTROL REGISTER:

This registers contents set by the processor at the time of start of

communication. This tells about FIFO’s trigger levels and reset conditions.
The first bit is always high, it is enabling bit for FIFO’s. The FIFO’s are
always enabled. The FIFO’s are always ready to receive the data.

4.LINE CONTROL REGISTER:

This register is used to set the format for communication at the start of
communication. This will set by the processor. It will tell about how data
width that will be decided by the num_bits, the parity is enabled or not, if
enabled it is even parity or odd parity and how many stop bots need to
transmits depending on the stop_b bit.

5.MODEM CONTROL REGISTER:

This register is used to enable the communication. At the start of

communication the processor will set this register contents. When the BIT0
(DTR) =’1’ the processor is ready to communicate. When the BIT (1)(RTS)
=’1’ the UART will send the request to the serial device.
6.LINE STATUS REGISTER:

This register contents indicates the status of communication line.

Whenever there is a high on the interrupt, the processor will read this
register contents after reading the contents of interrupt identification register.
This register consists of parity error, frame error, over run error, transmitter
FIFO empty interrupts.
7.MODEM STATUS REGISTER:

This register contents indicates the status of handshake signals. Whenever

there is any change on any handshake signals the UART will generate
interrupt. BIT (0) is high whenever there is an any change on the CLEAR
TO SEND handshake signal. BIT (10 is high when ever there is an any
change on the DATA SET READY hand shake signal.

TEST STRATEGY:

In the test bench loop back is provided from the transmitter serial
output to the receiver serial Input. For the testing the system clock and
baud rate generator clock are same.

Step 1.
Assert the reset (RST) and system clock (CLK) and baud rate clock
(BR_CLK),
• Initialize the all registers to specific contents.
• Reset the contents of TX & Rx FIFO’s.
• Disable the all interrupts.

REGISTERS RESET STATE

IER 0 0 0 0 0 0 0 0(LSB)
IIR 00000001
FCR 00000000
LCR 00000000
MCR 00000000
LSR 01100000
MSR 00000000

Step 2.

Deassert the RST to for proper operation of uart (RST=’0’) and WR=’1’.
 • Set the ADD =”011”set the contents of LCR for specific communication
format.
• Set the ADD=”001”Enable the interrupts by making the IER contents to
high.
• Set the ADD=”100”Set the contents of MCR to enable the
communication by asserting DTR and RTS.
• Set the ADD=”010”Set the FIFO trigger level by initializing the FCR.

Step 3.

Assert the serial device hand shake signals to start the communication
CTS<=‘1’, DSR<=’1’;
Whenever the TX FIFO is empty, set the ADD=”000” for writing the data
to TX_FIFO.

Step 4.

Assert the RD=’1’ and ADD=”000”to read the contents of RX_FIFO

whenever there is at least one byte is available in the RX_FIFO.

Step 5.

Whenever there is high on the interrupt set the ADD=”010” to read the
contents of IIR.
And set the ADD=”101” to read the contents of LSR.

Step 6:

Take proper action according to corresponding interrupt.

SYNTHESIS REPORT:

DEVICE UTILIZATION:
*******************************************************

Cell: uart_top View: uart_top_a Library: work

*******************************************************

Cell Library References Total Area

BUFG xcv2 2 x 1 2 BUFG

BUFGP xcv2 2 x 1 2 BUFGP
FDC xcv2 43 x 1 43 Dffs or Latches
FDCE xcv2 72 x 1 72 Dffs or Latches
FDP xcv2 4 x 1 4 Dffs or Latches
FDPE xcv2 3 x 1 3 Dffs or Latches
GND xcv2 1 x 1 1 GND
IBUF xcv2 18 x 1 18 IBUF
LD xcv2 2 x 1 2 Dffs or Latches
LUT1 xcv2 7 x 1 7 Function
Generators
LUT2 xcv2 17 x 1 17 Function
Generators
LUT2_L xcv2 6 x 1 6 Function
Generators
LUT3 xcv2 48 x 1 48 Function
Generators
LUT4 xcv2 98 x 1 98 Function
Generators
MUXCY_L xcv2 5 x 1 5 MUX CARRYs
MUXF5 xcv2 36 x 1 36 MUXF5
MUXF6 xcv2 2 x 1 2 MUXF6
OBUF xcv2 12 x 1 12 OBUF
VCC xcv2 1 x 1 1 VCC
XORCY xcv2 6 x 1 6 XORCY
rx_asyncfifo work 1 x 1 1 rx_asyncfifo
tx_asyncfifo work 1 x 1 1 tx_asyncfifo

Number of ports : 32
Number of nets : 428
Number of instances : 387
Number of references to this view : 0

Total accumulated area :

Number of BUFG : 2
Number of BUFGP : 2
Number of Dffs or Latches : 124
Number of Function Generators : 176
Number of GND : 1
Number of IBUF : 18
Number of MUX CARRYs : 5
Number of MUXF5 : 36
Number of MUXF6 : 2
Number of OBUF : 12
Number of VCC : 1
Number of XORCY : 6
 Number of gates : 176
Black Box rx_asyncfifo : 1
Black Box tx_asyncfifo : 1

***********************************************
Device Utilization for 2V250fg256
***********************************************
Resource Used Avail Utilization
-----------------------------------------------
IOs 32 172 18.60%
Function Generators 176 3072 5.73%
CLB Slices 88 1536 5.73%
Dffs or Latches 124 3588 3.46%

-----------------------------------------------

TIMING REPORT:

Clock Frequency Report

Clock : Frequency
------------------------------------

clk : 103.3 MHz

br_clk1 : 107.6 MHz

Critical Path Report

Critical path #1, (unconstrained path)

NAME GATE
ARRIVAL LOAD
-----------------------------------------------------------------------
--------------------
clock information not specified
delay thru clock network 3.61
(worst case)

rx_cnt8_cnt(1)/Q FDCE 0.00 5.47

up 2.73
nx2135/I3 LUT4 0.00 5.47
up 2.23
nx2135/O LUT4 1.19 6.65
up 2.23
ix2185/I0 MUXF5 0.00 6.65
up 0.00
ix2185/O MUXF5 0.79 7.44
up 2.35
nx2136/I2 LUT4 0.00 7.44
up 2.23
nx2136/O LUT4 1.19 8.63
up 2.23
ix2168/I0 MUXF5 0.00 8.63
up 0.00
ix2168/O MUXF5 0.90 9.53
up 2.73
rx_cnt8_cnt_nx11/I2 LUT3 0.00 9.53
up 2.23
rx_cnt8_cnt_nx11/O LUT3 1.19 10.72
up 2.23
rx_cnt8_cnt(1)/D FDCE 0.00 10.72
up 0.00
data arrival time 10.72

data required time not

specified
-----------------------------------------------------------------------
--------------------
data required time not
specified
data arrival time 10.72
--------
--
unconstrain
ed path
-----------------------------------------------------------------------
--------------------