Design of 16 TO 1 Multiplexer
Md. Arafat Hossain
ID: 1802127
Dept: EEE
Chittagong University of Engineering and Technology
&Technology
Abstract-Multiplexing is the process of combining one or
more signals and transmitting on a single channel. The
device which is responsible for Multiplexing is known as
Multiplexer. Multiplexer are used for both Analog and
Digital signals. Multiplexer or Mux is a digital switch also
called as data selector. It is a combinational Logic Circuit
with more than one input line and one output line and more
than one select line. It accepts the information from several
input lines or sources and depending on the set of select
lines, a particular input line is routed onto a single output
line. If the number of input lines is equal to 2 m, then m
selection lines are required to select one of n (consider 2 m =
n) input lines. Some of the most frequently used
multiplexers include 2-to-1, 4-to-1, 8-to-1 and 16-to-1
multiplexers. Multiplexer can be made with the help of Mos
technology in VLSI. We can design a multiplexer in cadence
software. In the design process we used pmos and nmos. In
the designing process we use static logic design. In the total
designing process we designed basic gates like AND gate,
OR gate and NOT gate. Combining all these gates we have
designed the 16 to 1 MUX.
Keywords- MULTIPLEXING, VLSI, CADENCE, BASIC-
GATES
INTRODUCTION
The modern world is floating above technology. And
communication is the heart of modern technology. Today
communication system becomes very upgraded. It is done
with the help of electrical and electronic devices. Now-a-days
these devices become very tiny in size. For this all the circuit
also become small. All this can happen with the help of VLSI
technology. VLSI stands for very large scale integration. With
this technology very small size devices can be made. In
modern communication multiplexing is very important. Its
because with the increasing of people, communication also
Fahim Faisal
ID: 1802128
Dept: EEE
Chittagong University of Engineering
increases. And if the communication medium also increases,
there will be redundancy and everything will become
complex. The solution of this situation is the multiplexing
process. Multiplexer mainly works as a switch. It combines
many inputs lines but the output line is just a single one. This
is really a great solution. So the importance of designing a
multiplexer is very concerning. In designing a multiplexer
logic circuit mainly uses. So before implementing all the
circuit we need to design it, simulate it and make sure it works
properly. Today the modern multiplexer becomes very small
in size. So designing this sized device is very challenging.
Here VLSI technology comes as a blessing. With the help of
MOS technology any electric and electronic device can design
perfectly. So our aim is to design multiplexer with the help of
cadence software.
LITERATURE REVIEW
A Multiplexer plays very impact role in modern technology.
These are found in many digital system applications such as
data selection and data routing, logic function generators,
digital counters with multiplexed displays, telephone network,
communication systems, waveform generator. Multiplexer are
various types. Most frequently include 2-to-1, 4-to-1, 8-to-1
and 16-to-1 multiplexers are used. All these indicates the input
lines and output. A 16-to-1 multiplexer has 16 input lines and
one output line. This multiplexer can be designed with cmos
technology.
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 Fig: 16 to 1 multiplexer A. All Basic gates and 16to1 Mux design
Here AND, OR, NOT gate has designed and finally 16 to 1
We can observe the truth table of the 16 to 1 multiplexer mux is designed. For schematic design we have to use pmos
circuit. In the truth table we can see that output is always and nmos transistor. In the design we used static logic circuit
active high. The four switching pin woks as input. Different design.
combination of the switching inputs select the input. That’s
why output is always active high. From the circuit diagram of
multiplexer we can see that final output comes across the OR
gate. As the or gate works as addition operation, whenever
any of the input is on, output becomes active.

Figure 1: NOT gate schematic design

Fig: Truth table of 16to1 MUX

METHODOLOGY
To design a 16-to-1 mux, several gates design, schematic
design, symbol creation, layout design, DRC testing, LVS
testing, Extracted viewing, tape-out need to be designed and
checked . A list of the designing is given below:
 System design with functional and architecture
analysis.
 Gate level schematic design and symbol creation.
 Transistor level design and cell layout.
 Top level layout placement and LVS check.
 Clearing all DRC errors.
 Extracted viewing.
 Tape-out.
Figure 2 AND gate schematic design

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 B. Symbol design of all basic gates and 16 to 1 mux
We have designed all the symbol and also used them as
library file in schematic design.

Figure 5: Symbol of AND gate

Figure 3: OR gate schematic design

Figure 6: Symbol of AND gate

Figure 4 16 to 1 mux schematic design

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 C. Output waveform of 16 to 1 MUX

Figure 9: Output waveform of 16 to 1 MUX

Figure 7: Symbol of OR gate

D. Layout design of all basic gates and 16to1 mux

Here all the layout has designed. In layout design we use both
manual design criteria and also auto generation from
schematic.

Figure 8: Symbol of 16 to 1 MUX

Figure 10: NOT gate layout design

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Figure 11: AND gate layout design

Figure 13: 16 to 1 mux layout design

E. DRC test of all basic gates and 16to1 MUX

DRC test stands for design rule check. It is done weather

layout design maintains all the rule. Here no DRC error has
found.

Figure 12: OR gate layout design

Figure 14: NOT gate DRC test

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Figure 15: AND gate DRC test

Figure 17: 16 to 1 mux DRC test

F. LVS of all basic gates and 16to1 MUX

LVS stands for layout vs schematic. It is also an important test

to check.

Figure 16: OR gate DRC test Figure 18: NOT gate LVS test

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 G. Reasons for 16 to 1 MUX LVS warning:
In final LVS test we have found 1 nets mismatch and 1 pin
mismatch. Here nets problem occurs because in schematic
total 9 wire came out from switch S0 where for layout we
have used 34 wires. Its because of our need. That’s why we
cannot solve this problem.

Figure 19: AND gate LVS test

H. Top level layout placement and routing

It is done to see the extraction view. The resistor and capacitor
are shown in extraction view.

Figure 20: OR gate LVS test

Figure 22: Top level layout placement of 16 to1 mux

Figure 21: 16 to 1 MUX gate LVS test

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 Figure 23: Top level layout placement and routing of 16 to1 mux

I. Tape-out

Figure 24: Tape-out

CONCLUSION
In this project, we try to design the 16-to-1 Multiplexer. Here
we first design the schematic circuit of all the basic gate
needed. We mainly use static logic circuit to design the
schematic circuits. We have also designed the symbol. The
layout design was also performed for all gates and finally the
multiplexer. After that the DRC test was performed and the
LVS test was also performed. After clearing all the DRC error
we taped out.

ACKNOWLEDGEMENT
We thank Mohammad Mahmudul Hasan Tareq, Assistant
Professor, Department of Electrical and Electronic
Engineering, Chittagong University of Engineering and
Technology (CUET) for the help, valuable advice,
discussions, constant encouragement and support.