EEE415 Week09 GPIO

DRAFT 8/11/2023
EEE 415 - Microprocessors and Embedded Systems
EEE General Purpose Input

Output (GPIO)
415 Week 09
Dr. Sajid Muhaimin Choudhury, Assistant Professor

Department of Electrical and Electronics Engineering
Bangladesh University of Engineering and Technology

Output (GPIO)
415 Lecture 9.1

Week 09

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Topics Covered from
Dr. Sajid Muhaimin Choudhury 3

EEE 415 - Department of EEE, BUET Yifeng Zhu Embedded Systems with ARM Cortex-M Microcontrollers © 2015
Arm Processor Families
• The Cortex-M family includes Cortex-MO, Cortex-MO+, Cortex-Ml, Cortex-M3, CortexM4, and Cortex-M7. The former
three are Von Neumann architecture, and the latter three are Harvard architecture. Moreover, Cortex-MO/MO+/Ml
are ARMv6-M, and CortexM3/M4/M7 are ARMv7-M.
• Cortex-M processors are backward compatible, and Figure 3-2 compares the instructions supported by each
processor group. For example, a binary program compiled for CortexM3 can run on Cortex-M4 without any
modification
EEE 415 - Department of EEE, BUET Dr. Sajid Muhaimin Choudhury 4
source: from referred textbook Yifeng Zhu Embedded Systems with ARM Cortex-M Microcontrollers © 2015
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Computer Architectures
Von-Neumann Harvard
Instructions and data are stored in Data and instructions are stored into
the same memory. separate memories.
N.B. multi cycle processor we discussed earlier N.B. single cycle and pipelined processors we
was based on this architecture discussed earlier were based on this architecture
EEE 415 - Department of EEE, BUET Dr. Sajid Muhaimin Choudhury 5 5
source: from slides prepared by Dr. Yifeng Zhu Yifeng Zhu Embedded Systems with ARM Cortex-M Microcontrollers © 2015
Von-Neumann vs Harvard Architecture

Advantages of Von-Neumann Architecture Advantages Of Harvard Architecture
• Simplified design of the control unit: Same control unit • Being accessed by separate sets of buses,
fetches instruction and data from one memory unit. both Program and Data can easily be
• Increased Memory Access Efficiency: Data from simultaneously accessed, therefore
memory and from devices are accessed the same way. improving the performance.
Therefore increasing efficiency • The implementation of Pipelining is
• Programmers’ control of memory organisation streamlined and decreases CPU stalls and
so effectively increasing the efficiency of the
Disadvantages of Von-Neumann Architecture pipeline.
• Parallel execution of program are not allowed due to
serial instruction processing Disadvantages Of Harvard Architecture
• Neumann Bottleneck: Only one “bus” can be accessed • 2 Sets of buses are needed and therefore
at a time. This results in the CPU being idle (as it’s faster relatively complex bus structure.
than a data bus) • Does not allow sizes of Data and Program
• Memory Management If a defective program fails to to be adjusted flexibly and dynamically,
release memory when they don’t require it (or finish with they are stored in different Memory spaces
it), it may cause the computer to crash, as a result of physically.
insufficient memory available
• Unintentional rewriting of instruction and data can https://www.electricalonline360.com/2021/05/harvard-
EEE
occur,, due415 - Department
to program of EEE,
error, resulting in BUET
data loss architecture-definition.html
Yifeng Zhu Embedded Systems with ARM Cortex-M Microcontrollers © 2015
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ARM Cortex-M Series Family

Von-Neumann Harvard
Instructions and data are stored in Data and instructions are stored into
the same memory. separate memories.
ARM ARM ARM ARM

Cortex-M0 Cortex-M0+ Cortex-M3 Cortex-M4
ARMv6-M ARMv6-M ARMv7-M ARMv7E-M
ARM ARM ARM ARM

Cortex-M1 Cortex-M23 Cortex-M7 Cortex-M33
ARMv6-M ARMv8-M ARMv7E-M ARMv8-M
EEE 415 - Department of EEE, BUET Dr. Sajid Muhaimin Choudhury 7 7

Arm Cortex M4

EEE 415 - Department of EEE, BUET
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An in-circuit debugger is a
hardware device, connected
between a PC and the target
microcontroller test system,
and is used to debug real-
time applications.

EEE 416 – STM32F446RE
STM32 Morpho Connector with all Pin

access
• So, textbook might refer to some

features that are not available in
your lab kits
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STM32L4 – Ultra Low Power
 Part Number: STM32L476RGT6

 Total number of pins: 64
 Total number of I/O pins: 51
 Maximum clock frequency: 80MHz
 Program memory size: 1 MB
 Operating supply voltage: 1.71V to 3.6V
 I/O voltage: 3.3V
Analog supply voltage: 3.3V
EEE 415 - Department of EEE, BUET from st.com Dr. Sajid Muhaimin Choudhury 11 11
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STM32F4 – High Performance
 Part Number: STM32F446RE

 Total number of pins: 64
 Total number of I/O pins: 51
 Maximum clock frequency: 180MHz
 Program memory size: 512 kB
 Operating supply voltage: 1.71V to 3.6V
 I/O voltage: 1.7-3.6V
 Analog supply voltage: 1.7-3.6V

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Word of Caution
• For the theory course, we will just talk about STM32L4
architecture
• For lab-sheet, we use STM32L4. we will highlight

differences between STM32F4 and L4 (if any)

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In real world applications: you need to always follow the

documentation of the specific architecture!

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STM32L4
• An ARM Cortex-M processor chip consists of a Cortex-M core licensed by ARM, on-chip peripheral devices
implemented by chip manufacturers, and buses and bridges for the communication between the core and
peripheral devices.

source: from referred textbook
15
• Fundamental components of a Cortex-M processor core include the arithmetic logic unit
(ALU), the processor control unit, the interrupt controller (NVIC), the instruction fetching
and decoding unit, and the interfaces for memory and debug.
• The interrupt controller (NVIC) allows the processor core to stop the execution of
the current task and immediately respond to special events or signals generated by
software or by peripheral devices.
• The instruction fetching and decoding unit reads one machine instruction from the
instruction memory address pointed by the program counter and decodes the
instruction to figure out what operations the processor core should perform.
• The processor control unit then generates corresponding control signals based on
the decoding result.
• The memory interface supports the access to memory devices (SRAM, flash).
• The debug interface allows a programmer to use a host computer to start or stop a
software program on a Cortex-M processor, and monitor or modify processor
registers, peripheral registers, and memory in real-time.
• Cortex-M4 supports digital signal processing (DSP) and can optionally have a single-
precision floating processing unit (FPU).
• Cortex-MO/MO+/Ml/M3 has no support to DSP and FPU. Compared with Cortex-M4, the
optional FPU on CortexM7 can support both single-precision and double-precision
operations.
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• Examples of peripheral devices integrated into a Cortex-M chip are:

• LCD controllers,
• serial communication (PC, SPI, and USART), USB,
• digital-to-analog converters (DAC), and analog-to-digital converters (ADC)
• Different manufacturers may add various peripheral devices to the chip Dr. Sajid Muhaimin Choudhury 17
17
• The core processor communicates with the flash memory (typically used as instruction memory), SRAM
(generally used as data memory), Direct Memory Access (DMA) controller, and general-purpose input/output
(GPIO) ports via a bus matrix (also called crossbar switch)
• Peripheral devices are connected to the bus matrix via the bus bridges that links the advanced high-performance
bus (AHB) and the advanced peripheral bus (APB) Dr. Sajid Muhaimin Choudhury 18
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• Each GPIO pin has multiple functions usually. Software can change its function, even at runtime.
• We can use a GPIO pin simply for digital input or digital output, or we can use it for more advanced functions
such as analog-to-digital conversion (ADC), serial communication, timer functions, and so on.
• Different SoC chips may have different GPIO functions, depending on the chip manufacturers
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General Purpose
Input/Output (GPIO) of
ARM Microcontroller

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Importance and Functionality of GPIO

• The number of pins available on a processor is usually limited. A processor pin
that can be configured by software at runtime to perform various functions is
called a general-purpose I/O (GPIO) pin.
• GPIO provides high flexibility of use and enormous convenience of system
design, though the flexibility comes with a price tag that the software must perform
a sophisticated initialization.
• Software can program a GPIO pin as one of the following four different
functions:
• Digital input that detects whether an external voltage signal is higher or lower
than a predetermined threshold
• Digital output that controls the voltage on the pin
• Analog functions that perform digital-to-analog or analog-to-digital conversion
Called • Other complex functions such as PWM output, LCD driver, timer-based input
Alternate
Functions (AF) capture, external interrupt, and interface of USART, SPI, PC and USB
communication
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Functionality of GPIO
• A GPIO port consists of a group of GPIO pins, typically 8 or 16, which share the
same data and control registers.
• All GPIO pins in a GPIO port can be configured as input or output independently
• When a GPIO pin i is set as a digital input, the binary data read from this pin of
this GPIO group is saved at bit i in the input data register (IDR). Each bit in IDR
holds the digital input of the corresponding pin.
• When a GPIO pin i is configured as a digital output, bit i in the output data register
(ODR) holds the output of this pin. Therefore, when changing the output of a
GPIO pin, the programmer should only alter the value of the corresponding bit of
ODR, without affecting the other bits in ODR.

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Port-mapped vs Memory-mapped I/O

• I/O refers to data communication between the processor core and a peripheral
device. There are two complementary approaches to performing I/0 operations:
port-mapped I/0, and memory-mapped I/0
• Port-mapped I/O uses special machine instructions, which are designed specifically for I/O
operations. The memory address space and the I/O device address space are independent of
each other.
• Each device is assigned one or more unique port numbers.
• For example, Intel x86 processors use IN and OUT instructions to read from or write to a port.

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Port-mapped vs Memory-mapped I/O

• Memory-mapped I/O does not need any
special instructions. The memory and the
I/O devices share the same address space.
• Each peripheral register or data buffer is
assigned to a memory address in the
memory address space of the
microprocessor.
• Memory-mapped I/O is performed by the
native load and store (e.g. LDR/STR)
instructions of the processor. Therefore,
memory-mapped I/0 is a more convenient
way to interface I/O devices.
• The most significant disadvantage is that
memory-mapped I/O has a more complex
address decoding unit than port-mapped I/0
• Most CPUs (including Cortex M4) these
days do I/O via memory mapped I/O Dr. Sajid Muhaimin Choudhury 24
EEE 415 - Department
of EEE, BUET Yifeng Zhu Embedded Systems with ARM Cortex-M Microcontrollers © 2015
24
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Memory Map of Cortex-M4 (STM32L4)

0xFFFFFFFF
• All peripheral registers on NVIC, System Timer, SCB,
0.5 GB System
STM32L4 are mapped to vendor-specific memory
0xE0000000
a small memory region
starting at 0x40000000.
This region includes the 1 GB External Device Such as SD card
memory addresses of all
on-chip peripherals, such 0xA0000000
as GPIO, timers, UART,
SPI, and ADC. 1 GB External RAM 4 GB
Off-chip memory for data
• The memory address of
each peripheral register is 0x60000000
determined by chip 0.5 GB Peripheral AHB & APB, such as timers, GPIO
manufacturers, and 0x40000000
usually cannot be 0.5 GB SRAM On-chip RAM, for heap, stack, & code
changed by software. 0x20000000
0.5 GB Code On-chip Flash, for code & data
0x00000000

EEE 415 25
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EEE,
Byte (8 BUET
bits)
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Memory Map of STM32L4

0xFFFFFFFF
0.5 GB System
0xE0000000
1 GB External Device
0x60000000
0xA0000000
…
1 GB External RAM
0x48001000
GPIO D (1 KB)
0x60000000 0x48000C00
because 1024 bytes= 400 in
0.5 GB Peripheral GPIO C (1 KB) hexa, each byte in each memory
0x40000000 0x48000800 address
GPIO B (1 KB)
0.5 GB SRAM 0x48000400
0x20000000 GPIO A (1 KB)
0.5 GB Code 0x48000000
0x40000000
…
0x00000000

EEE 415 26
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One Byte (8BUET
bits)
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Output (GPIO)
415 Lecture 9.2

Week 09

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General Purpose Input/Output (GPIO)
• 8 GPIO Ports:
A, B, C, D, E, F, G, H
• Up to 16 pins in each port

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GPIO Memory Map

0x48000400
0x4800002C ASCR
0x48000028 BRR
0x48000024 AFR[1]
0x48000020 AFR[0]
0x48000400 0x4800001C LCKR
GPIO A (1 KB) 0x48000018 BSRR
0x48000000 48 bytes
0x48000014 ODR
0x48000010 IDR
0x4800000C PUPDR
0x48000008 OSPEEDR
0x48000004 OTYPER
0x48000000 MODER
• A peripheral register usually takes four bytes in memory. For example, the output
data register (ODR) of Port B on STM32L4 is mapped to memory addresses Each register has 4 bytes.
0x48000414 to 0x48000417, with the upper half-word being reserved. because after 16 bits are used by
EEE 415 - Department of EEE, BUET Dr.bits
16 registers, there remain 16 left Muhaimin Choudhury 29
Sajid
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Output Data Register (ODR)
0x48000017
ODR 1 word (i.e. 32 bits)
0x48000014
0x48000017
0x48000016
4 bytes
0x48000015
0x48000014
Little Endian
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Note that values stored in peripheral registers are in the format of little-endian

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GPIO Memory Map

0x48000400
Set pin A.13 to high

ASCR
0x4800002C
BRR
0x48000028
0x48000024
AFR[1]
AFR[0]
0x48000020
0x48000400 LCKR
0x4800001C
GPIO A (1 KB) BSRR
0x48000000 0x48000018 48 bytes
ODR
0x48000014
IDR
0x48000010
PUPDR
0x4800000C Set bit 13
OSPEEDR
0x48000008 of ODR
OTYPER
0x48000004 to high
MODER
0x48000000

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Output Data Register (ODR)

0x48000017
ODR 1 word (i.e. 32 bits)
0x48000014
0x48000017
0x48000016
4 bytes
0x48000015
0x48000014
Little Endian
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1
*((uint32_t *) 0x48000013) |= 1UL<<14;

Dereferencing a pointer Bitwise OR Systems with ARM Cortex-M Microcontrollers © 2015
Yifeng Zhu Embedded
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Casting a memory address to a pointer

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Why declare as Volatile?

• Typically, compilers minimize the number of memory accesses by
temporally storing the memory value in a register and then repeatedly
using it without accessing the memory.
• The volatile qualifier on a variable prevents the compiler from making such
optimization on this variable.
• When a variable is declared as volatile, the compiler is informed that even
though no statements in the program appear to change it, the value might
still change.
• Data and control registers of external devices are mapped to specific memory
addresses, and a program can use memory pointers to access these hardware
registers, such as the following C statement.
uint32_t *p = (uint32_t *) 0x60002400;
• To prevent the compiler from optimizing out these memory pointers incorrectly, software
must declare these pointers as volatile. The following example uses a memory pointer to
access a 32-bit hardware register mapped to the memory address 0x60002400.
volatile uint32_t *p = (uint32_t *) 0x60002400;
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Dereferencing to access the value stored in the

memory location pointed to by the pointer.
However, this C statement is difficult to read and
maintain.
Two better approaches (Methods 2 and 3),

which use a macro to
improve the code's readability.
• The macro in the second method
represents type-casting.
• The macro in the third method
represents both type-casting and
dereferencing

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These approaches are still

inconvenient for two reasons.
• First, we must define many
macros, one for each
peripheral register, even
though some peripherals
share the same register
layout.
• Second, if a function takes
a peripheral as input, it is
cumbersome to pass all
registers of this peripheral
as function arguments.
• A better approach is to use
structures and pointers.

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Casting the memory address to a GPIO structure pointer
• Because the memory address of

each register is word-aligned (i.e., is
a multiple of four), dummy bytes
are padded in the data structure to
correctly map the fixed physical
memory layout to the data
structure.
• In Figure 14-16, six bytes are
padded in the GPIO_TypeDef
structure, making its structure
members align properly with their
pre-defined memory addresses.

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• To conveniently access a set of

registers which are contiguous in
memory, we can cast the base
memory address of a GPIO port to a
pointer to a data structure
• If we want to set the output of

GPIO port B pin 6 to high, we can
use the following C statement.
• UL is an unsigned long integer with

a value of 1. Note the pins are
numbered 0 - 15, instead of 1 - 16.

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0x60000000
…
0x48001000
GPIO D (1 KB)
0x48000C00
GPIO C (1 KB)
0x48000800
GPIO B (1 KB)
0x48000400
GPIO A (1 KB)
0x48000000
0x40000000
…

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General Purpose Input/Output (GPIO)
D Bus
FLASH
ARM Cortex-M4 I Bus
AHB Bus
Matrix
SRAM
FPU S Bus
GPIO A
GPIO B APB Bus
GPIO C Matrix
GPIO D
GPIO E UART
GPIO F
GPIO G SPI
GPIO H
Timer
…
STM32L4

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A bit recap on C
programming: Bit
manipulation

41
Bit Manipulation: Set a Bit in C
a |= (1 << k)
or
a = a | (1 << k)
Example: k = 5
a a7 a6 a5 a4 a3 a2 a1 a0
1 << k 0 0 1 0 0 0 0 0
a | (1 << k) a7 a6 1 a4 a3 a2 a1 a0
The other bits should not be affected.

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Bit Manipulation: Set multiple Bits in C (2 bits)
a |= (3 << k)
or
a = a | (3 << k)
Example: k = 5
a a7 a6 a5 a4 a3 a2 a1 a0
1 << k 0 1 1 0 0 0 0 0
a | (1 << k) a7 1 1 a4 a3 a2 a1 a0

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Bit Manipulation: Set multiple Bits in C (3 bits)
a |= (7 << k)
or
a = a | (7 << k)
Example: k = 4
a a7 a6 a5 a4 a3 a2 a1 a0
1 << k 0 1 1 1 0 0 0 0
a | (1 << k) a7 1 1 1 a3 a2 a1 a0

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Bit Manipulation: Clear a Bit in C
a &= ~(1<<k)
Example: k = 5
a a7 a6 a5 a4 a3 a2 a1 a0
~(1 << k) 1 1 0 1 1 1 1 1
a & ~(1<<k) a7 a6 0 a4 a3 a2 a1 a0

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Bit Manipulation: Clear multiple Bits in C (2 bit)
a &= ~(3<<k)
Example: k = 5
a a7 a6 a5 a4 a3 a2 a1 a0
~(1 << k) 1 0 0 1 1 1 1 1
a & ~(1<<k) a7 0 0 a4 a3 a2 a1 a0

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Bit Manipulation: Clear multiple Bits in C (3 bit)
a &= ~(7<<k)
Example: k = 4
a a7 a6 a5 a4 a3 a2 a1 a0
~(1 << k) 1 0 0 0 1 1 1 1
a & ~(1<<k) a7 0 0 0 a3 a2 a1 a0

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Bit Manipulation: Toggle a Bit in C

Without knowing the initial value, a bit can be toggled by XORing it with a “1”
a ^= 1<<k
Example: k = 5
a a7 a6 a5 a4 a3 a2 a1 a0
1 << k 0 0 1 0 0 0 0 0
a ^ (1<<k) a7 a6 NOT(a5) a4 a3 a2 a1 a0
m n m⊕n
Truth table of 0 0 0
Exclusive OR 0 1 1
1 0 1
1 1 0
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Bit Manipulation: Toggle multiple Bits in C (3 bit)

Without knowing the initial value, a bit can be toggled by XORing it with a “1”
a ^= 7<<k
Example: k = 4
a a7 a6 a5 a4 a3 a2 a1 a0
1 << k 0 0 1 1 1 0 0 0
a ^ (1<<k) a7 a6 NOT(a5) NOT(a5) NOT(a5) a2 a1 a0
m n m⊕n
Truth table of 0 0 0
Exclusive OR 0 1 1
1 0 1
1 1 0
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Output (GPIO)
415 Lecture 9.3

Week 09

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Basic Structure of an I/O Port Bit

Input and Output
Schmitt
trigger

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Basic Structure of an I/O Port Bit: Output
GPIO Pull-up/Pull-down Register (PUPDR)

00 = No pull-up, pull-down 01 = Pull-up
10 = Pull-down 11 = Reserved
Output
Data Schmitt
trigger
Register GPIO Output Type Register (OTYPER)
0 = Output push-pull (default)
1 = Output open-drain
GPIO MODE Register

00 = Input, 01 = Output,
10 = AF, 11 = Analog (default)
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Flowchart for
GPIO Initialization Step 1:
Step 2:
Step 3:
Step 4:
Step 5:
Step 6:

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Step 1: Clock Enable

• First, it enables the clock of the GPIO port B via the RCC module. To save energy, every
peripheral's clock is turned off by default.
• We can enable the clock of a peripheral by setting the corresponding bit of the clock
control register defined in the reset and clock control (RCC) structure, as shown below.

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Step 1: Enable Clock

• AHB2 peripheral clock enable register (RCC_AHB2ENR)
SYSCLK Clock for Port B

1 GPIOEN
AND Gate
#define RCC_AHB2ENR_GPIOBEN ((uint32_t)0x00000002U)
RCC->AHB2ENR |= RCC_AHB2ENR_GPIOBEN;

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Step 2: GPIO Mode Register (MODER)

• 32 bits (16 pins, 2 bits per pin)
Pin 2 Pin 1 Pin 0
GPIOB->MODER &= ~(3UL<<4); // Clear bits 4 and 5 for Pin 2

GPIOB->MODER |= 1UL<<4; // Set bit 4, set Pin 2 as output

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Step 3: GPIO Output Type Register (OTYPE)

 16 bits reserved, 16 data bits, 1 bit for each pin
GPIOB->OTYPE &= ~(1UL<<2); // Clear bit 2

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Step 4: Setting Output Speed
• Output Speed:
• Speed of rising and falling Speed of Rising
• Four speeds: Low, Medium,
Low
Fast, High
• Tradeoff
• Higher GPIO speed increases Medium
EMI noise and power
consumption
Fast
• Configure based on peripheral
speed
– Low speed for toggling LEDs High
– High speed for SPI

source: from Dr. Yifeng Zhu’s slides Yifeng Zhu Embedded Systems with ARM Cortex-M Microcontrollers © 2015
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Step 5: GPIO Output: Push-Pull
GPIO Output = 1
Source current to external circuit

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Step 5: GPIO Output: Push-Pull
GPIO Output = 0
Drain current from external circuit

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Step 5: GPIO Output: Open-Drain
GPIO
Output Pin
GPIO
Output Bit
D
G
0/1 Controller NMOS
S
GPIO Output = 0
Drain current from external circuit

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Step 5: GPIO Output: Open-Drain
GPIO
Output Pin GPIO
Output Pin
Output is
GPIO GPIO Floating
Output Bit Output Bit
D 0
G
0/1 Controller NMOS 1 Controller NMOS
Output = 1
GPIO Pin has high-impedance to external circuit

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Slew Rate
Slew Rate
Maximum rate of change of the
output voltage
∆𝑉
𝑆𝑙𝑒𝑤 𝑅𝑎𝑡𝑒 = 𝑚𝑎𝑥
∆𝑡
A high slew rate allows the output

to be toggled at a fast speed.

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GPIO Output: Push-Pull vs Open-Drain
Output Bit Push-Pull Open-Drain

1 High HiZ
0 Low Low
Use push-pull output, instead of open-drain output!

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Step 6: GPIO Output Data Register (ODR)

• 16 bits reserved, 16 data bits, 1 bit for each pin
Pin 2
GPIOB->ODR |= 1UL << 2; // Set bit 2

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Putting it together: Light up a LED at PB.2
GPIO initialization code

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Basic Structure of an I/O Port Bit: Input
Schmitt • Reduce noise

trigger • Increase slew
rate
Input Data
Register (IDR)
Input is sampled into IDR
every AHB clock cycle!
GPIO Pull-up/Pull-down Register (PUPDR)
00 = No pull-up, pull-down 01 = Pull-up
10 = Pull-down 11 = Reserved

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Schmitt Trigger
V in
Threshold
Analog signals
• Noisy
• Rise and fall slowly (small slew rate)

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Schmitt Trigger
V in
Threshold

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Schmitt Trigger
Vout Vin
VTH
Vout
VTL
V in
Vout
VDD
V in
Vout
VDD
V in
Schmitt-trigger gives cleaner signal on input

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Flowchart for
GPIO Initialization Step 1:
Step 2:
Step 3:
Step 4:
Step 5:
Step 6:

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Step 1: Enable Clock

• AHB2 peripheral clock enable register (RCC_AHB2ENR)
SYSCLK Clock for Port A

1 GPIOAEN
AND Gate
#define RCC_AHB2ENR_GPIOAEN ((uint32_t)0x00000001U)
RCC->AHB2ENR |= RCC_AHB2ENR_GPIOAEN; // Enable clock of Port A

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Step 2: GPIO Mode Register (MODER)

• 32 bits (16 pins, 2 bits per pin)
Pin 2 Pin 1 Pin 0
// Set Pin 0 as input

GPIOA->MODER &= ~3UL; // Clear bits 1 and 2 for Pin 0

73
Step 5: GPIO Input: Pull Up and Pull Down

• A digital input can have three states: High, Low, and High-
Impedance (also called floating, tri-stated, HiZ)
Pull-Up Pull-Down
If external input is HiZ, the If external input is HiZ, the
input is read as a valid HIGH. input is read as a valid LOW.
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Step 5: GPIO Pull-up/Pull-down Register (PUPDR)

• 16 pins per port, 2 bits per pin
Pin 2 Pin 1 Pin 0
// No pull-up, pull-down
GPIOA->PUPDR &= ~3UL;

Pull-Up
EEE 415 - Department of EEE, BUETPull-Down Yifeng Zhu Embedded Systems with ARM Cortex-M Microcontrollers © 2015
75
Step 6: GPIO Input Data Register (IDR)

 16 bits reserved, 16 data bits (1 bit per pin)
// Demo of reading pin 7

uint32_t mask = 1UL<<7;
uint32_t input = (GPIOA->IDR & mask) == mask;
or
uint32_t input = (GPIOA->IDR & mask) >> 7;

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Read Input of Pin PA.0

uint32_t input;
RCC->AHB2ENR |= RCC_AHB2ENR_GPIOAEN; // Enable clock of Port A
GPIOA->MODER &= ~3UL; // Set PA.0 as digital input
GPIOA->PUPDR &= ~3UL; // No pull-up, no pull-down
// Read pin 0
input = (GPIOA->IDR & 1UL);
if (input == 0) {
// Center of joystick is not pressed
...
} else {
// Center of joystick is pressed
...
}
77
I/O Debouncing
• Example signal when a button is pressed
3
2.5
Voltage across push button
1.5
0.5
-0.5
-0.05 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
Time (microseconds)

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De-Bouncing
• Hardware De-bouncers
• Simple RC circuit as a low-pass filter
• Software De-bouncing
• Solution A: Read the switch after a sufficient delay to allow the
bounces to settle down
• Solution B: Reading periodically and use a counter as a filter
– Reset the counter when the signal is “unpressed”
– Counts up if “pressed”
– If counter > threshold, the contacts has stopped bouncing

79
Practice Problems
aC
aC
3. Write a C program that would light up an LED when a button is pressed in the STM32 board, and
turn off the LED when the button is released
Practice writing code by hand!!!!

80
40

EEE415 Week09 GPIO

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DRAFT 8/11/2023

EEE 415 - Microprocessors and Embedded Systems

EEE General Purpose Input

Dr. Sajid Muhaimin Choudhury, Assistant Professor

EEE 415 - Microprocessors and Embedded Systems

EEE General Purpose Input

415 Lecture 9.1

Dr. Sajid Muhaimin Choudhury, Assistant Professor

Topics Covered from

Dr. Sajid Muhaimin Choudhury 3

Arm Processor Families

Von-Neumann vs Harvard Architecture

ARM Cortex-M Series Family

ARM ARM ARM ARM

ARMv6-M ARMv6-M ARMv7-M ARMv7E-M

ARM ARM ARM ARM

ARMv6-M ARMv8-M ARMv7E-M ARMv8-M

EEE 415 - Department of EEE, BUET Dr. Sajid Muhaimin Choudhury 7 7

Dr. Sajid Muhaimin Choudhury 8

Dr. Sajid Muhaimin Choudhury 9

EEE 416 – STM32F446RE

STM32 Morpho Connector with all Pin

• So, textbook might refer to some

STM32L4 – Ultra Low Power

 Part Number: STM32L476RGT6

STM32F4 – High Performance

 Part Number: STM32F446RE

Dr. Sajid Muhaimin Choudhury 12

• For lab-sheet, we use STM32L4. we will highlight

Dr. Sajid Muhaimin Choudhury 13

In real world applications: you need to always follow the

Dr. Sajid Muhaimin Choudhury 14

Dr. Sajid Muhaimin Choudhury 15

• Examples of peripheral devices integrated into a Cortex-M chip are:

Dr. Sajid Muhaimin Choudhury 20

Importance and Functionality of GPIO

Dr. Sajid Muhaimin Choudhury 22

Port-mapped vs Memory-mapped I/O

Dr. Sajid Muhaimin Choudhury 23

Port-mapped vs Memory-mapped I/O

Memory Map of Cortex-M4 (STM32L4)

Dr. Sajid Muhaimin Choudhury 25

Memory Map of STM32L4

Dr. Sajid Muhaimin Choudhury 26

EEE 415 - Microprocessors and Embedded Systems

EEE General Purpose Input

415 Lecture 9.2

Dr. Sajid Muhaimin Choudhury, Assistant Professor

General Purpose Input/Output (GPIO)

• Up to 16 pins in each port

Dr. Sajid Muhaimin Choudhury 28

GPIO Memory Map

Output Data Register (ODR)

Dr. Sajid Muhaimin Choudhury 30

GPIO Memory Map

Set pin A.13 to high

Dr. Sajid Muhaimin Choudhury 31

Output Data Register (ODR)

*((uint32_t *) 0x48000013) |= 1UL<<14;

Dr. Sajid Muhaimin Choudhury 32

Casting a memory address to a pointer

Dr. Sajid Muhaimin Choudhury 33

Why declare as Volatile?

((uint32_t ) 0x48000013) |= 1UL<<14;