EEE415 Week10 Timer

DRAFT 8/14/2023
EEE 415 - Microprocessors and Embedded Systems
EEE General Purpose Timer
415 Lecture 10.1

Week 10
Dr. Sajid Muhaimin Choudhury, Assistant Professor

Department of Electrical and Electronics Engineering
Bangladesh University of Engineering and Technology
Topics Covered from
Dr. Sajid Muhaimin Choudhury 2

EEE 415 - Department of EEE, BUET Yifeng Zhu Embedded Systems with ARM Cortex-M Microcontrollers © 2015
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Week Plan
• Week 09: (3 lecture) GPIO
• Week 10: (2 lecture) General Purpose Timer – GPT, PWM
• Week 11: (5 lecture) Interrupts
• Week 12: (2 lecture) ADC/DAC
• Week 13: (3 lecture) Serial Comm
Slides of timer are prepared by Sadman Sakib Ahbab

Timer
• Free-run counter (independent of processor)
• A timer is a hardware component in ARM Cortex-M microprocessor. Each
timer has a special register, which is called the timer counter. The counter
runs freely.
• It is hardware, not software, which keeps repeatedly incrementing or
decrementing the counter value.
• Functions
• Input capture
• Output compare
• Pulse-width modulation (PWM) generation
• One-pulse mode output

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Block Diagram of a Timer

Auto-Reload Register (ARR)
Prescalar (PSC) Repetition Counter)
Counter (CNT)
Output Control (OCR)
Capture/Compare Register (CCR)

• The main block of the programmable advanced-control timer is a

16-bit counter with its related auto-reload register. The counter can
count up, down or both up and down.
• The counter clock can be divided by a prescaler. The counter, the

auto-reload register and the prescaler register can be written or read
by software. This is true even when the counter is running.

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• The time-base unit includes:

• Counter register (TIMx_CNT)
• Prescaler register (TIMx_PSC)
• Auto-reload register (TIMx_ARR)
• Repetition counter register (TIMx_RCR)
• Different type of Timers on STM32L4 –

• Advanced control timers (TIM1 & TIM8)
• General Purpose timers (TIM2~TIM5, TIM9~TIM14)
• Basic Timers (TIM6 & TIM7)

Glossary of Registers
• CR – Control Register
• CCMR – Capture/Compare Mode Register
• CCER – Capture/Compare Enable Register
• ARR – Auto Reload Register
• CNT - Counter
• PSC - Prescalar
• RCR – Repetition Counter Register
• CCR – Capture/Compare Register

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Basic timer function

• The prescaler divides the system clock to produce CK_CNT.
• Once enabled, the counter (CNT) counts up by one on every tick of
the clock (CK_CNT).
• The counter counts up to the value of the ARR.
• On the next CK_CNT tick:
• The counter is reset to zero.
• An update event occurs.

Timer: Clock (Pre-Scaler)

UIF: Update Interrupt Flag
Auto-Reload UIE: Update Interrupt Enable
Register (ARR)
Reload trigger
fCL_PSC TIMx_SR
fCL_CNT event
Timer
PSC UIF interrupt
Counter
&
clock Prescaler
Counter is UIE
incremented/decremented once TIMx_DIER
per cycle.
𝑓 _ The prescaler enables a tradeoff between timer

Frequency: 𝑓 _ = resolution and timer range. High timer resolution
𝑃𝑆𝐶 + 1
requires a high clock rate. However, high clock rates
Software can change the prescaler (PSC) to cause the timer to overflow or underflow more quickly.
allow the timer clocked at desired rate.
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Timer: Clock
Auto-Reload
Register (ARR)
Reload trigger
16MHz fCL_CNT TIMx_SR

PSC Timer event
UIF interrupt
15,999 Counter
&
clock Prescaler UIE
1KHz Counter is
incremented/decremented once TIMx_DIER
per cycle.
16 𝑀𝐻𝑧
𝑓 _ = = 1 𝐾𝐻𝑧
15999 + 1

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Counting modes & ARR

The hardware timer counter has three
different counting modes:
• up-counting: 0 to a constant and
then restarts from 0. Software sets
up the constant and stores it in a
special register called the auto-
reload register (ARR).
• down-counting: ARR to 0 then
restart from ARR
• center-aligned counting: performs
up-counting and down-counting
alternatively.

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Up-counting
ARR = 6,
clock
6 6 6 6
5 Counter
5 Counter
5 Counter
5
4 overflow 4 overflow 4 overflow 4
3 3 3 3
counter 2 2 2 2
1 1 1 1
0 0 0 0
Period = (1 + ARR) * Clock Period

= 7 * Clock Period
Clock Period = 1/fCNT fCNT = fSOURCE/(1 + PSC)

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Center-aligned Mode
ARR = 6
Clock
6 6
5 5 5 5
4 4 4 4
3 3 3 3
Counter 2 2 2 2
1 1 1 1
0 0 0
Counter Counter Counter Counter
overflow underflow overflow underflow
Update event (UEV)
Period = 2 * ARR * Clock Period

= 12 * Clock Period

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Timer: Output
Auto-Reload
Register (ARR)
Reload trigger
fCL_PSC fCL_CNT TIMx_SR

Timer event
PSC UIF interrupt
Counter
&
clock Prescaler UIE
TIMx_DIER
Timer Output
=
(OCREF)
Compare &
Capture
Register (CCR)
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CCR (compare and capture register)

• When a timer is configured to generate an output signal, hardware
constantly compares the freely-running counter, with a value stored
in the compare and capture register (CCR).
• The output of the timer, OCREF, can be high or low, depending on

the timer settings.
• Note that, when the function of a timer is output, the CCR register
is used only for compare.

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Input Capture (Will be discussed in Interrupt)

• A timer can also be used for input capture. When a specific
external event occurs, such as a rising edge of an external signal
on a G P I O pin, hardware automatically copies, the current value
of the timer counter, to the compare and capture register (CCR).
• We can use such an ability to measure the timing information of a
signal event, such as rising edge, or falling edge. By calculating the
difference between two recorded CCR values, we can measure the
period, or the pulse width of input signals. In this lecture, we will
focus only on the output function, instead of the input capture.
• Will be covered after covering interrupt.

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Timer: Input Capture

Auto-Reload
Register (ARR)
Reload trigger
fCL_PSC TIMx_SR
fCL_CNT event
Timer
PSC UIF interrupt
Counter
&
clock Prescaler UIE
TIMx_DIER
Compare &
Capture
Register (CCR)
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DRAFT 8/14/2023
Multi-Channel Outputs

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Multi-Channel Outputs
• Each timer has four channels.
• Each channel has its own Compare and Capture Register.
CCR1, CCR2, CCR3, CCR4.
• These four channels share the timer counter, and the auto-
reload register (ARR).
• Therefore, If we use these to generate PWM outputs, they
will have exactly the same period. However, their duty
cycle can be different, because the value of these CCR
registers can differ from each other. [details later]
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Output Compare
• When the timer counter (CNT) equals the compare value

(CCR), the output of a channel (OCREF) is programmable.
• The output can have different values, depending on the
outputcompare mode (OCM), as shown in Table (next slide).
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that means, active high signal e OCREF logic

Output Compare high hole OC w logic high hobe
 logic representation for the

output of each timer channel
independently by
programming the output
polarity bit in the control
register CCER.
 polarity bit is 0 -> Active

high. Otherwise, Active low
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OCM (Output Compare Mode)

 Where is this OCM located?
 In TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 1, 8)

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OCREF is not the actual output!

• A timer channel may have two outputs: main output OC and complementary
output OCN,
• these are the XOR between the channel reference output OCREF and its
corresponding polarity bit in the CCER register, as shown below.
• The CCP and CCNP bits in the CCER register are the polarity bit of OC and
OCN, respectively. [shown in next slide]

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CCER
OC1N polarity
OC1N enable
OC1 polarity
OC1 enable

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Toggling output every 1 sec

• Specific Timer’s Specific Channel (OC & OCN) are
connected to different GPIO Pin as alternate function.
• Each GPIO pin has 16 Alternate Function possibility. So, 4
bits are required to describe AF0 ~ AF15 of a single pin.
• For a 16 pin port, 4x16=64 bits required to describe Afs. So
2 32 bit AF Registers required – pin 0~7 are in AFR[0] &
8~15 in AFR[1].
• Which Timer’s which channel connected to which pins as
what AF no. --- described in the Datasheet.
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AF of GPIOA of the STM board in lab

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DRAFT 8/14/2023
Example of Toggling LED (Zhu 15.2.2)
 So, we use PE 8 in AF mode (MODER=10), use AF1 (AFR[1] = 0001), which

is timer 1, complementary output of channel 1(OC1N).

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• Suppose the system clock is 80 MHz and it is selected as the timer clock that
drives the timer 1.
• Lets Slow down the clock of the timer counter to 2 KHz by a prescaler
• To turn an LED on for 1 second and then off for 1 second repeatedly, counting
period = 2s. Fclock_CNT = 2KHz. So from formula, ARR = 1999.

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Class Plan for Rest of the Semester

• Aug 12th (Sat) – GPIO 1, 2
• Aug 16th (Wed) – GPIO 3, Timer 1
• Aug 19th (Sat) – NO CLASS
• Aug 23rd (Wed) – Timer 2, 3
• Aug 26th (Sat) – Interrupt 1,2
• Aug 30th (Wed) – CT3 + Interrupt 3, 4
• Sep 2rd (Sat) – Interrupt 5, ADC and DAC 1
• Sep 6th (Wed) – ADC and DAC 2, 3
• Sep 9th (Sat) – Serial Communication

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Class Plan for Rest of the Semester

• Aug 12th (Sat) – GPIO 1, 2
• Aug 16th (Wed) – GPIO 3, Timer 1
• Aug 19th (Sat) – NO CLASS
• Aug 23rd (Wed) – Timer 2, 3
• Aug 26th (Sat) – Interrupt 1,2
• Aug 30th (Wed) – CT3 + Interrupt 3, 4
• Sep 2rd (Sat) – Interrupt 5, ADC and DAC 1
• Sep 6th (Wed) – ADC and DAC 2, 3
• Sep 9th (Sat) – Serial Communication

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DRAFT 8/14/2023
EEE General Purpose Timer:

Initialization
415 Lecture 10.2

Week 10

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Flow chart
• Enable GPIOE clock
• Set pin 8 in AF (10) mode
• Select AF1 (0001)
• Set pin 8 output speed low (00)
• No Pullup No Pull down (00)

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Flow chart
• Enable TIM1 clock
• Set counting direction in Control Reg 1 (CR1)
• Load Pre-scaler PSC = 39999
• Load ARR = 1999
• Load CCR1 (Output compare value of Ch1) [any

value betn 0~ARR, since in toggle mode, doesn’t
matter]

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Flow chart
• Main Output Enable (MOE) in BDTR
reg
• Set output compare mode of ch1

(OCM1) to toggle (0011) in CCMR
• Set polarity of CH1N (OC1N) to active

high (CC1NP=0 in CCER)
because OCN and OCREF er value same, that means tader
• Enable CH1 complementary output relation active high
(OC1N) (CC1NE=1 in CCER)
• Enable Timer 1 in Control Reg 1 (CR1).
DO not do this before setting up all other options, because

many of them
EEE 415 - Department becomes
of EEE, BUETlocked once you enable the timer!!!!Dr. Sajid Muhaimin Choudhury 36
Yifeng Zhu Embedded Systems with ARM Cortex-M Microcontrollers © 2015
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DRAFT 8/14/2023
PE8 Output (Fig 15.7)
Possible Correction in Book. Since

Only OC1N is enabled, it should be,
OCN = OCREF xor (Polarity of OCN)
= OCREF

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Timer Update Events

• An update event (UEV) is generated
• on each overflow in up-counting,
• on each underflow in down-counting,
• on both overflow and underflow in center-counting.
• UEV events serve three purposes:
• Generate trigger output (TRGO) for other internal modules, such as timers, DMA, ADC,
and DAC.
• Make updates of registers ARR, PSC, and CCR take effect immediately if the buffering (also
called preload) mechanism is enabled. If the channel's preload enable bit (OCPE) in the
CCMRl register and the auto-reload preload enable bit (ARPE) in the CRl register are set,
the preload mechanism is enabled.
• Generate a timer interrupt request if the update interrupt flag bit (UIF) of the control
register CRl is set. Interrupt requests are sent to the interrupt controller (NVIC). In response,
the processor executes the corresponding interrupt handler. [Fig next slide]
• If RCR (Repition counter register) = N, then UEV event will occur every N+1 overflow (for
up counting), or underflow (for down counting), or overflow & underflow (center aligned)
[Fig next slide]

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CR1 & SR reg of TIM 1,8
Counting Direction
Enable Timer
If UEV is enabled in CR1,

(that is, UDIS=update
disable=0) then when an
UEV occur, the UIF bit in SR
(Status register) will
become 1.

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Counting Direction
Enable Timer
Also, interrupt request sent

to NVIC If Update Interrupt
is Enabled (UIE=1) in DIER
reg

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Repetition Counter Register (RCR)
If RCR (Repition counter register) = N, then UEV event will occur every N+1 overflow (for up
counting), or underflow (for down counting), or overflow & underflow (center aligned)
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Edge-aligned Mode (Up-counting)

ARR = 6, RCR = 0
clock
6 6 6 6
5 Counter
5 Counter
5 Counter
5
4 overflow 4 overflow 4 overflow 4
3 3 3 3
counter 2 2 2 2
1 1 1 1
0 0 0 0
Counter overflow
Update event (UEV)

= 7 * Clock Period
Clock Period = 1/fCNT fCNT = fSOURCE/(1 + PSC)

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Edge-aligned Mode (down-counting)

ARR = 6, RCR = 0
Clock
6 6 6 6
5 5 5 5
4 4 4 4
3 3 3 3
Counter 2 Counter 2 Counter 2 Counter 2
1 underflow 1 underflow 1 underflow 1
0 0 0 0
Counter underflow
Update event (UEV)

= 7 * Clock Period

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Center-aligned Mode
ARR = 6, RCR = 0
Clock
6 6
5 5 5 5
4 4 4 4
3 3 3 3
Counter 2 2 2 2
1 1 1 1
0 0 0
Counter Counter Counter Counter
overflow underflow overflow underflow
Update event (UEV)
Period = 2 * ARR * Clock Period

= 12 * Clock Period

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Hardware Precision Delay (TIM7- Basic Timer)
Wait until UEV occurs at

the end of counting and
UIF bit in SR becomes 1

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LED Blinking with Timer

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LED_Pin Initialization

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Timer Channel Initialization

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Music Generation with Timer Output

• We show a very basic application of Timer:
Generating music
• Music will be based on square wave output of the timer

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Some Fundamentals of Music Theory

• Rhythm (তাল) – Pulse of Music. Strong Repeating pattern
of strong and weak elements
• Tempo (লয়) – How quickly or slowly the music is played.

Measured in Beat Per Minute
• Pitch (সুর) – How sharp or mellow the sound is. Pitch is

directly related to frequency (C D E or সা র গা মা). bird
chirping is sharp, growling of dog is mellow.
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Octave
• Our ears are trained to detect change in pitch. Usually we can
detect the difference between the frequency between two sounds.
• The pitch difference is perceived as ratio of the pitch
• 220 to 440 Hz frequency change

• 440 to 880 Hz frequency change – both feels same amount
• Frequency difference of 1:2 is called an “Octave”

https://onlinetonegenerator.com/?waveform=square

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Scale
• For western musical scale, the interval between 2
frequencies of an octave is divided into 12 logarithmically
spaced frequency.
• Each frequency represents a note
• Standard practice is to take note A4 = 440Hz as reference
and calculate other notes. 4 represents the 4th octave. A3 =
220Hz, A5 = 880Hz
220 440

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Note A4 to B4 can be calculated by multiplying frequency

by 2(2/12) as they are 2 notes apart
*2(2/12)

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Making Music with sequence of notes – আমার ভাইেয়র রে

রা ােনা

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Reproducing the Notes

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EEE General Purpose Timer:

PWM
415 Lecture 10.3

Week 10

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PWM
• Pulse width modulation (PWM) is a simple digital technique to
control the value of an analog variable.
• PWM uses a rectangular waveform to quickly switch a voltage
source on and off to produce a desired average voltage output.
• The output is binary at any time instant, the average output
over a time span can be any value between 0 and the
maximum voltage.
• Specifically, the percentage of time in the on state within one
period is proportional to the mean value of the voltage output.
Consequently, when software changes the duration of the on
state, the output voltage is adjusted accordingly to emulate an
analog signal.

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• For a sawtooth carrier signal,

Avg value = duty cycle x max value

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Controlling PWM duty cycle by changing CCR

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PWM Mode
Mode Counter < Reference Counter ≥ Reference
PWM mode 1
Active Inactive
(Low True)
PWM mode 2
Inactive Active
(High True)

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PWM Mode 1 Mode 1

Timer Output (OCREF) =
High if counter < CCR
(Low-True) Low if counter ≥ CCR
Upcounting mode, ARR = 6, CCR = 3, RCR = 0
Clock
6 6 6 6
5 5 5 5
4 4 4 4
CCR = 3 3 3 3 3
Counter 2 2 2 2
1 1 1 1
0 0 0 0
OCREF
CCR
Duty Cycle = Period = (1 + ARR) * Clock Period
ARR + 1
= 7 * Clock Period
3
=
7
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PWM Mode 2 Mode 2

Low if counter < CCR
(High-True) High if counter ≥ CCR
Clock
6 6 6 6
5 5 5 5
4 4 4 4
CCR = 3 3 3 3 3
Counter 2 2 2 2
1 1 1 1
0 0 0 0
OCREF
CCR
Duty Cycle = 1 - Period = (1 + ARR) * Clock Period
ARR + 1
= 7 * Clock Period
4
=
7
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PWM Mode 2 Mode 2

Clock
6 6 6 6
CCR = 5 5 5 5 5
4 4 4 4
3 3 3 3
Counter 2 2 2 2
1 1 1 1
0 0 0 0
OCREF
CCR
Duty Cycle = 1 - Period = (1 + ARR) * Clock Period
ARR + 1
= 7 * Clock Period
2
=
7
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PWM Mode 2 Mode 2

Timer Output
Timer(OCREF)
Output==
Center-aligned mode, ARR = 6, CCR = 3, RCR = 0
Clock
6 6
5 5 5 5
4 4 4 4
CCR = 3 3 3 3 3
Counter 2 2 2 2
1 1 1 1
0 0 0
OCREF
CCR
Duty Cycle = 1 - Period = 2 * ARR * Clock Period
ARR
= 12 * Clock Period
1
=
2
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PWM Mode 2 Mode 2 Low if counter < CCR


Clock
6 6
5 5 5 5
4 4 4 4
3 3 3 3
Counter 2 2 2 2
1 1 1 1
CCR = 1 0 0 0
OCREF
CCR
Duty Cycle = 1 - Period = 2 * ARR * Clock Period
ARR
= 12 * Clock Period
5
=
6
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Auto-Reload Register (ARR) & Preload (ARPE)

• The auto-reload register (ARR) can be updated synchronously, or asynchronously.
• If the ARPE bit in the timer CR1 register is 1, ARR will be updated synchronously. An
update to ARR will be buffered in a register, named the pre load register. The contents
of the pre load register, are transferred into ARR, when the next update event occurs.
This update mechanism is synchronous to timer’s input clock, and timer’s output
period. It prevents software from updating the output frequency or period, when the
timer is still performing comparison operations.
• On the other hand, if ARPE = 0, any updates to ARR will immediately take effect. This
update mechanism is asynchronous, because the update does not take the clock
timing information into considerations.
Counting Direction
Enable Timer
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Auto-Reload Register (ARR) & Preload (ARPE)
• Auto-Reload Preload Enable (ARPE) bit in TIMx_CR1
ARPE = 1 (Syn Update)

Write to ARR Preload Auto-reload
Read from ARR Register Register (ARR) If UDIS bit in TIMx_CR1 is 1,
UEV event is disabled.
Triggered by Update Event (UEV)
ARPE = 0 (Asyn Update)

Write to ARR Auto-reload
Read from ARR Register (ARR)

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PWM Output Polarity
Mode Counter < CCR Counter ≥ CCR

PWM mode 1
Active Inactive
(Low True)
PWM mode 2
Inactive Active
(High True)
Output Polarity:
• Software can program the CCxP bit in the TIMx_CCER register
Active Inactive
Active High High Voltage Low Voltage
Active Low Low Voltage High Voltage

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Counting up, down, center

69
Up-Counting: Left Edge-aligned (PWM mode1)

Clock
6 6 6 6
CCR = 6 5 5 5 5
4 4 4 4
CCR = 3 3 3 3 3
Counter 2 2
1
2
1
2
1 1
0 0 0 0
CCR = 3
OC1REF
CCR = 6
OC2REF
Left-aligned
All rising edges occur at the same time! PWM Period
the up-counting PWM mode 1, when multiple PWM signals are generated by the same timer, all rising
edges occur at the same time at left clk edge. That is why the up-counting mode is left edge-aligned.
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Upcounting, PWM Mode 2: Right Edge-aligned

Clock
6 6 6 6
CCR = 5 5 5 5 5
4 4 4 4
CCR = 3 3 3 3 3
Counter 2 2
1
2
1
2
1 1
0 0 0 0
OC1REF CCR = 3
OC2REF CCR = 5
Right-aligned
All falling edges occur at the same time!
PWM Period

71
PWM Mode 2: Center Aligned

Timer Output =
High if counter ≥ CCR
Clock
6 6
5 5 5 5
4 4 4 4
CCR = 3 3 3 3 3
Counter 2 2
1
2 2
1
1 1
CCR = 1 0 0 0
CCR = 3
OC1REF
CCR = 1
OC2REF
Center-aligned
PWM signals are center aligned!
PWM Period

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PWM Example: LED Fading

• Let us programs a timer to generate a PWM output signal
to increase or decrease the brightness of an LED
gradually.
• Green LED at PE8, with TIM1_CH1N as AF1
• On STM32L4, a 4 MHz clock that drives the processor

core and its peripherals, (such as timers) by default.
Assume the prescaler factor is set as 39, thus the
frequency at which the counter increments is
73
• Suppose the refresh rate of the LED is 100 Hz. (human eye cannot
detect flicker at a refresh rate higher than 100 Hz. Thus, we will see
a steady and continuously source of light even though the LED is
switched on and off 100 times per second.)

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 When ARR is kept at a fixed

value, CCR controls the duty
cycle.
 Assume timer 1 uses PWM
mode 1, in which the reference
output (OCREF) is high for up-
counting if the timer counter is
less than CCR, and otherwise,
OCREF is low.
 Figure 15-16 shows that as CCR
increases gradually, the duty
cycle of OCREF also increases.

75
• The complementary output of time 1 channel 1

(TIMl_CHlN) drives the
• LED.
OCN = OCREF xor (Polarity bit for OCN)
• If we use CCR to represent the LED brightness, we need
to set the polarity bit (CCNP) for the complement output to
0. In other words, OCN waveform is the same as OCREF.

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PWM Programming Flowchart Correction in book: CCER instead of CCMR

77
• The Code in next slide (Example 15-5) changes the duty

cycle of the PWM output.
• The code does not configure the system clock and thus the
default MSI 4 MHz is selected.
• The GPIO initialization code is not given in the demo code.
• Within the endless loop, the compare and capture register
for channel 1 (CCRl) is increased or decreased (The
variable direction either 1 or -1) gradually after a short
delay.
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Code
CCMR register e shob OC,

and CCER register e shob CC

79
The devil is in
the detail
• Timer output control
• Enable Timer Output
• MOE: Main output enable
• OSSI: Off-state selection for Idle mode
• OSSR: Off-state selection for Run mode
• CCxE: Enable of capture/compare output for channel x
• CCxNE: Enable of capture/compare complementary output for
channel x
• These control bits are located in the timer register CCER,
and register BDTR.
• For example, in order to enable the output (OC) for
channel x, we need to set the MOE bit to 1 in register BD
TR.
• Based on the need of software application, we can choose
one of these three configurations.

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DRAFT 8/14/2023
BDTR
OSSI: Only important when MOE = 0
OSSR: Only important when Dr. MOE Sajid= 1, & eitherChoudhury

Muhaimin OC or OCN81is
EEE 415 - Department of EEE, BUET disabled. Don’t
Yifengcare when Systems
Zhu Embedded both OC & Cortex-M
with ARM OCN Microcontrollers
enabled © 2015
81
Summary: Timer Output

Up-counting or Down-counting:
1
𝑂𝑢𝑡𝑝𝑢𝑡 𝑆𝑖𝑔𝑛𝑎𝑙 𝑃𝑒𝑟𝑖𝑜𝑑 = × 𝐴𝑅𝑅 + 1
𝑓
𝑓
𝑓 =
𝑃𝑆𝐶 + 1
𝐴𝑅𝑅 + 1 (𝑃𝑆𝐶 + 1)
𝑂𝑢𝑡𝑝𝑢𝑡 𝑆𝑖𝑔𝑛𝑎𝑙 𝑃𝑒𝑟𝑖𝑜𝑑 =
𝑓

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82
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Appendix: TIM1 Reg Map (Reg’s discussed for TIM1 CH1 are
highlighted)

83
Appendix: TIM1 Reg Map

42
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85

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86
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87
LED Fading (PWM)

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88
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EEE 416: LED Fading (PWM)

89
EEE 416: LED Pin Initialization

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91
46

EEE415 Week10 Timer

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DRAFT 8/14/2023

EEE 415 - Microprocessors and Embedded Systems

EEE General Purpose Timer

415 Lecture 10.1

Dr. Sajid Muhaimin Choudhury, Assistant Professor

Topics Covered from

Dr. Sajid Muhaimin Choudhury 2

• Week 10: (2 lecture) General Purpose Timer – GPT, PWM

• Week 11: (5 lecture) Interrupts

• Week 12: (2 lecture) ADC/DAC

• Week 13: (3 lecture) Serial Comm

Slides of timer are prepared by Sadman Sakib Ahbab

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Block Diagram of a Timer

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• The main block of the programmable advanced-control timer is a

• The counter clock can be divided by a prescaler. The counter, the

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• The time-base unit includes:

• Different type of Timers on STM32L4 –

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Basic timer function

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Timer: Clock (Pre-Scaler)

𝑓 _ The prescaler enables a tradeoff between timer

16MHz fCL_CNT TIMx_SR

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Counting modes & ARR

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Period = (1 + ARR) * Clock Period

Clock Period = 1/fCNT fCNT = fSOURCE/(1 + PSC)

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Update event (UEV)

Period = 2 * ARR * Clock Period

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fCL_PSC fCL_CNT TIMx_SR

CCR (compare and capture register)

• The output of the timer, OCREF, can be high or low, depending on

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Input Capture (Will be discussed in Interrupt)

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Timer: Input Capture

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• When the timer counter (CNT) equals the compare value

that means, active high signal e OCREF logic

 logic representation for the

 polarity bit is 0 -> Active

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OCM (Output Compare Mode)

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OCREF is not the actual output!

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Toggling output every 1 sec

AF of GPIOA of the STM board in lab

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Example of Toggling LED (Zhu 15.2.2)

 So, we use PE 8 in AF mode (MODER=10), use AF1 (AFR[1] = 0001), which

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Class Plan for Rest of the Semester