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ADSP-2188M
FEATURES System Interface
Performance Flexible I/O Structure Allows 2.75 V or 3.3 V Operation;
13.3 ns Instruction Cycle Time @ 2.75 V (Internal), All Inputs Tolerate up to 3.6 V Regardless of Mode
75 MIPS Sustained Performance 16-Bit Internal DMA Port for High-Speed Access to
Single-Cycle Instruction Execution On-Chip Memory (Mode Selectable)
Single-Cycle Context Switch 4 MByte Memory Interface for Storage of Data Tables
3-Bus Architecture Allows Dual Operand Fetches in and Program Overlays (Mode Selectable)
Every Instruction Cycle 8-Bit DMA to Byte Memory for Transparent Program
Multifunction Instructions and Data Memory Transfers (Mode Selectable)
Power-Down Mode Featuring Low CMOS Standby Power I/O Memory Interface with 2048 Locations Supports
Dissipation with 200 CLKIN Cycle Recovery from Parallel Peripherals (Mode Selectable)
Power-Down Condition Programmable Memory Strobe and Separate I/O
Low Power Dissipation in Idle Mode Memory Space Permits “Glueless” System Design
Programmable Wait State Generation
Integration
Two Double-Buffered Serial Ports with Companding
ADSP-2100 Family Code Compatible (Easy to Use
Hardware and Automatic Data Buffering
Algebraic Syntax), with Instruction Set Extensions
Automatic Booting of On-Chip Program Memory from
256K Bytes of On-Chip RAM, Configured as
Byte-Wide External Memory, e.g., EPROM, or
48K Words Program Memory RAM
through Internal DMA Port
56K Words Data Memory RAM
Six External Interrupts
Dual-Purpose Program Memory for Both Instruction and
13 Programmable Flag Pins Provide Flexible System
Data Storage
Signaling
Independent ALU, Multiplier/Accumulator, and Barrel
UART Emulation through Software SPORT Reconfiguration
Shifter Computational Units
ICE-Port™ Emulator Interface Supports Debugging in
Two Independent Data Address Generators
Final Systems
Powerful Program Sequencer Provides Zero Overhead
Looping Conditional Instruction Execution
Programmable 16-Bit Interval Timer with Prescaler
100-Lead LQFP and 144-Ball Mini-BGA
FUNCTIONAL BLOCK DIAGRAM
POWER-DOWN
CONTROL
FULL MEMORY MODE
MEMORY
PROGRAMMABLE EXTERNAL
DATA ADDRESS PROGRAM DATA I/O ADDRESS
GENERATORS PROGRAM MEMORY MEMORY AND BUS
SEQUENCER FLAGS
DAG1 DAG2 48K ⴛ 24 BIT 56K ⴛ 16 BIT
EXTERNAL
DATA
BUS
PROGRAM MEMORY ADDRESS
BYTE DMA
DATA MEMORY ADDRESS CONTROLLER
REV. 0
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ADSP-2188M
TABLE OF CONTENTS
–2– REV. 0
ADSP-2188M
GENERAL DESCRIPTION The EZ-KIT Lite is a hardware/software kit offering a complete
The ADSP-2188M is a single-chip microcomputer optimized evaluation environment for the ADSP-218x family: an ADSP-
for digital signal processing (DSP) and other high-speed numeric 2189M-based evaluation board with PC monitor software plus
processing applications. assembler, linker, simulator, and PROM splitter software. The
The ADSP-2188M combines the ADSP-2100 family base archi- ADSP-2189M EZ-KIT Lite is a low cost, easy to use hardware
tecture (three computational units, data address generators, and platform on which you can quickly get started with your DSP
a program sequencer) with two serial ports, a 16-bit internal DMA software design. The EZ-KIT Lite includes the following features:
port, a byte DMA port, a programmable timer, Flag I/O, exten- • 75 MHz ADSP-2189M
sive interrupt capabilities, and on-chip program and data memory. • Full 16-Bit Stereo Audio I/O with AD73322 Codec
The ADSP-2188M integrates 256K bytes of on-chip memory • RS-232 Interface
configured as 48K words (24-bit) of program RAM, and 56K • EZ-ICE Connector for Emulator Control
words (16-bit) of data RAM. Power-down circuitry is also pro- • DSP Demo Programs
vided to meet the low power needs of battery-operated portable • Evaluation Suite of VisualDSP
equipment. The ADSP-2188M is available in a 100-lead LQFP The ADSP-218x EZ-ICE® Emulator aids in the hardware
package and 144 Ball Mini-BGA. debugging of an ADSP-2188M system. The ADSP-2188M
In addition, the ADSP-2188M supports new instructions, which integrates on-chip emulation support with a 14-pin ICE-Port
include bit manipulations—bit set, bit clear, bit toggle, bit test— interface. This interface provides a simpler target board connec-
new ALU constants, new multiplication instruction (× squared), tion that requires fewer mechanical clearance considerations
biased rounding, result-free ALU operations, I/O memory trans- than other ADSP-2100 Family EZ-ICEs. The ADSP-2188M
fers, and global interrupt masking, for increased flexibility. device need not be removed from the target system when using
the EZ-ICE, nor are any adapters needed. Due to the small
Fabricated in a high-speed, low-power, CMOS process, the footprint of the EZ-ICE connector, emulation can be supported
ADSP-2188M operates with a 13.3 ns instruction cycle time. in final board designs.
Every instruction can execute in a single processor cycle.
The EZ-ICE performs a full range of functions, including:
The ADSP-2188M’s flexible architecture and comprehensive
instruction set allow the processor to perform multiple opera- • In-target operation
tions in parallel. In one processor cycle, the ADSP-2188M can: • Up to 20 breakpoints
• Single-step or full-speed operation
• Generate the next program address • Registers and memory values can be examined and altered
• Fetch the next instruction • PC upload and download functions
• Perform one or two data moves • Instruction-level emulation of program booting and execution
• Update one or two data address pointers • Complete assembly and disassembly of instructions
• Perform a computational operation • C source-level debugging
This takes place while the processor continues to: See Designing An EZ-ICE-Compatible Target System in the
• Receive and transmit data through the two serial ports ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections) as
• Receive and/or transmit data through the internal DMA port well as the Designing an EZ-ICE-Compatible System section of
• Receive and/or transmit data through the byte DMA port this data sheet for the exact specifications of the EZ-ICE target
• Decrement timer board connector.
Additional Information
DEVELOPMENT SYSTEM This data sheet provides a general overview of ADSP-2188M
The ADSP-2100 Family Development Software, a complete set functionality. For additional information on the architecture and
of tools for software and hardware system development, supports instruction set of the processor, refer to the ADSP-2100 Family
the ADSP-2188M. The System Builder provides a high-level User’s Manual. For more information about the development
method for defining the architecture of systems under develop- tools, refer to the ADSP-2100 Family Development Tools
ment. The Assembler has an algebraic syntax that is easy to data sheet.
program and debug. The Linker combines object files into an
executable file. The Simulator provides an interactive instruction-
level simulation with a reconfigurable user interface to display
different portions of the hardware environment.
REV. 0 –3–
ADSP-2188M
POWER-DOWN
CONTROL
FULL MEMORY MODE
MEMORY
PROGRAMMABLE EXTERNAL
DATA ADDRESS PROGRAM DATA I/O ADDRESS
GENERATORS PROGRAM MEMORY MEMORY AND BUS
SEQUENCER FLAGS
DAG1 DAG2 48K ⴛ 24 BIT 56K ⴛ 16 BIT
EXTERNAL
DATA
BUS
PROGRAM MEMORY ADDRESS
BYTE DMA
DATA MEMORY ADDRESS CONTROLLER
–4– REV. 0
ADSP-2188M
external buses with bus request/grant signals (BR, BGH, and BG). • SPORTs can use an external serial clock or generate their
One execution mode (Go Mode) allows the ADSP-2188M to own serial clock internally.
continue running from on-chip memory. Normal execution • SPORTs have independent framing for the receive and trans-
mode requires the processor to halt while buses are granted. mit sections. Sections run in a frameless mode or with frame
The ADSP-2188M can respond to eleven interrupts. There can synchronization signals internally or externally generated.
be up to six external interrupts (one edge-sensitive, two level- Frame sync signals are active high or inverted, with either of
sensitive, and three configurable) and seven internal interrupts two pulsewidths and timings.
generated by the timer, the serial ports (SPORTs), the Byte DMA • SPORTs support serial data word lengths from 3 to 16 bits
port, and the power-down circuitry. There is also a master and provide optional A-law and µ-law companding according
RESET signal. The two serial ports provide a complete synchro- to CCITT recommendation G.711.
nous serial interface with optional companding in hardware and
a wide variety of framed or frameless data transmit and receive • SPORT receive and transmit sections can generate unique
modes of operation. interrupts on completing a data word transfer.
Each port can generate an internal programmable serial clock or • SPORTs can receive and transmit an entire circular buffer of
accept an external serial clock. data with only one overhead cycle per data word. An interrupt
is generated after a data buffer transfer.
The ADSP-2188M provides up to 13 general-purpose flag pins.
The data input and output pins on SPORT1 can be alternatively • SPORT0 has a multichannel interface to selectively receive
configured as an input flag and an output flag. In addition, eight and transmit a 24 or 32 word, time- division multiplexed,
flags are programmable as inputs or outputs, and three flags are serial bitstream.
always outputs. • SPORT1 can be configured to have two external interrupts
A programmable interval timer generates periodic interrupts. (IRQ0 and IRQ1) and the FI and FO signals. The internally
A 16-bit count register (TCOUNT) decrements every n pro- generated serial clock may still be used in this configuration.
cessor cycle, where n is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero, PIN DESCRIPTIONS
an interrupt is generated and the count register is reloaded from The ADSP-2188M is available in a 100-lead LQFP package
a 16-bit period register (TPERIOD). and a 144-Ball Mini-BGA package. In order to maintain maxi-
mum functionality and reduce package size and pin count, some
Serial Ports serial port, programmable flag, interrupt and external bus pins
The ADSP-2188M incorporates two complete synchronous have dual, multiplexed functionality. The external bus pins are
serial ports (SPORT0 and SPORT1) for serial communications configured during RESET only, while serial port pins are soft-
and multiprocessor communication. ware configurable during program execution. Flag and interrupt
Here is a brief list of the capabilities of the ADSP-2188M functionality is retained concurrently on multiplexed pins. In
SPORTs. For additional information on Serial Ports, refer to cases where pin functionality is reconfigurable, the default state is
the ADSP-2100 Family User’s Manual. shown in plain text; alternate functionality is shown in italics.
• SPORTs are bidirectional and have a separate, double-
buffered transmit and receive section.
REV. 0 –5–
ADSP-2188M
Common-Mode Pins
–6– REV. 0
ADSP-2188M
Memory Interface Pins
The ADSP-2188M processor can be used in one of two modes: Full Memory Mode, which allows BDMA operation with full exter-
nal overlay memory and I/O capability, or Host Mode, which allows IDMA operation with limited external addressing capabilities.
The operating mode is determined by the state of the Mode C pin during RESET and cannot be changed while the processor is running.
The following tables list the active signals at specific pins of the DSP during either of the two operating modes (Full Memory or
Host). A signal in one table shares a pin with a signal from the other table, with the active signal determined by the mode set. For the
shared pins and their alternate signals (e.g., A4/IAD3), refer to the package pinout tables.
REV. 0 –7–
ADSP-2188M
Terminating Unused Pins
The following table shows the recommendations for terminating unused pins.
Pin Terminations
–8– REV. 0
ADSP-2188M
Interrupts LOW POWER OPERATION
The interrupt controller allows the processor to respond to the The ADSP-2188M has three low power modes that significantly
11 possible interrupts and reset with minimum overhead. The reduce the power dissipation when the device operates under
ADSP-2188M provides four dedicated external interrupt input standby conditions. These modes are:
pins: IRQ2, IRQL0, IRQL1, and IRQE (shared with the PF7:4 • Power-Down
pins). In addition, SPORT1 may be reconfigured for IRQ0, • Idle
IRQ1, FI and FO, for a total of six external interrupts. The • Slow Idle
ADSP-2188M also supports internal interrupts from the timer,
the byte DMA port, the two serial ports, software, and the power- The CLKOUT pin may also be disabled to reduce external
down control circuit. The interrupt levels are internally prioritized power dissipation.
and individually maskable (except power- down and reset). The Power-Down
IRQ2, IRQ0, and IRQ1 input pins can be programmed to be The ADSP-2188M processor has a low power feature that lets
either level- or edge-sensitive. IRQL0 and IRQL1 are level- the processor enter a very low-power dormant state through
sensitive and IRQE is edge-sensitive. The priorities and vector hardware or software control. Following is a brief list of power-
addresses of all interrupts are shown in Table I. down features. Refer to the ADSP-2100 Family User’s Manual,
“System Interface” chapter, for detailed information about the
Table I. Interrupt Priority and Interrupt Vector Addresses power-down feature.
Interrupt Vector • Quick recovery from power-down. The processor begins
Source Of Interrupt Address (Hex) executing instructions in as few as 200 CLKIN cycles.
Reset (or Power-Up with PUCR = 1) 0000 (Highest Priority) • Support for an externally generated TTL or CMOS processor
Power-Down (Nonmaskable) 002C clock. The external clock can continue running during power-
IRQ2 0004 down without affecting the lowest power rating and 200 CLKIN
IRQL1 0008 cycle recovery.
IRQL0 000C • Support for crystal operation includes disabling the oscillator
SPORT0 Transmit 0010 to save power (the processor automatically waits approximately
SPORT0 Receive 0014 4096 CLKIN cycles for the crystal oscillator to start or stabi-
IRQE 0018 lize), and letting the oscillator run to allow 200 CLKIN cycle
BDMA Interrupt 001C start-up.
SPORT1 Transmit or IRQ1 0020 • Power-down is initiated by either the power-down pin (PWD)
SPORT1 Receive or IRQ0 0024 or the software power-down force bit. Interrupt support allows
Timer 0028 (Lowest Priority) an unlimited number of instructions to be executed before
optionally powering down. The power-down interrupt also
Interrupt routines can either be nested with higher priority inter-
can be used as a nonmaskable, edge-sensitive interrupt.
rupts taking precedence or processed sequentially. Interrupts
can be masked or unmasked with the IMASK register. Individual • Context clear/save control allows the processor to continue
interrupt requests are logically ANDed with the bits in IMASK; where it left off or start with a clean context when leaving the
the highest priority unmasked interrupt is then selected. The power-down state.
power-down interrupt is nonmaskable. • The RESET pin also can be used to terminate power-down.
The ADSP-2188M masks all interrupts for one instruction • Power-down acknowledge pin indicates when the processor
cycle following the execution of an instruction that modifies the has entered power-down.
IMASK register. This does not affect serial port autobuffering
or DMA transfers. Idle
When the ADSP-2188M is in the Idle Mode, the processor
The interrupt control register, ICNTL, controls interrupt nest- waits indefinitely in a low-power state until an interrupt occurs.
ing and defines the IRQ0, IRQ1, and IRQ2 external interrupts When an unmasked interrupt occurs, it is serviced; execution
to be either edge- or level-sensitive. The IRQE pin is an exter- then continues with the instruction following the IDLE instruc-
nal edge sensitive interrupt and can be forced and cleared. The tion. In Idle mode IDMA, BDMA and autobuffer cycle steals
IRQL0 and IRQL1 pins are external level sensitive interrupts. still occur.
The IFC register is a write-only register used to force and clear Slow Idle
interrupts. On-chip stacks preserve the processor status and are The IDLE instruction is enhanced on the ADSP-2188M to let
automatically maintained during interrupt handling. The stacks the processor’s internal clock signal be slowed, further reducing
are twelve levels deep to allow interrupt, loop, and subroutine power consumption. The reduced clock frequency, a program-
nesting. The following instructions allow global enable or disable mable fraction of the normal clock rate, is specified by a selectable
servicing of the interrupts (including power down), regardless divisor given in the IDLE instruction.
of the state of IMASK. Disabling the interrupts does not affect
serial port autobuffering or DMA. The format of the instruction is:
REV. 0 –9–
ADSP-2188M
FULL MEMORY MODE HOST MEMORY MODE
ADSP-2188M ADSP-2188M
1/2x CLOCK CLKIN 1/2x CLOCK CLKIN
OR 14 A13–0 OR
CRYSTAL XTAL XTAL
ADDR13–0 CRYSTAL 1
FL0–2 D23–16 A0–A21 FL0–2 A0
as SCLK, CLKOUT, and timer clock, are reduced by the same The CLKIN input cannot be halted, changed during opera-
ratio. The default form of the instruction, when no clock divisor tion, nor operated below the specified frequency during normal
is given, is the standard IDLE instruction. operation. The only exception is while the processor is in the
When the IDLE (n) instruction is used, it effectively slows down power-down state. For additional information, refer to Chap-
the processor’s internal clock and thus its response time to incom- ter 9, ADSP-2100 Family User’s Manual, for detailed information
ing interrupts. The one-cycle response time of the standard idle on this power-down feature.
state is increased by n, the clock divisor. When an enabled inter- If an external clock is used, it should be a TTL-compatible signal
rupt is received, the ADSP-2188M will remain in the idle state running at half the instruction rate. The signal is connected to
for up to a maximum of n processor cycles (n = 16, 32, 64, or the processor’s CLKIN input. When an external clock is used,
128) before resuming normal operation. the XTAL input must be left unconnected.
When the IDLE (n) instruction is used in systems that have an The ADSP-2188M uses an input clock with a frequency equal to
externally generated serial clock (SCLK), the serial clock rate half the instruction rate; a 37.50 MHz input clock yields a 13 ns
may be faster than the processor’s reduced internal clock rate. processor cycle (which is equivalent to 75 MHz). Normally,
Under these conditions, interrupts must not be generated at a instructions are executed in a single processor cycle. All device
faster than can be serviced, due to the additional time the timing is relative to the internal instruction clock rate, which is
processor takes to come out of the idle state (a maximum of n indicated by the CLKOUT signal when enabled.
processor cycles). Because the ADSP-2188M includes an on-chip oscillator circuit,
an external crystal may be used. The crystal should be connected
SYSTEM INTERFACE across the CLKIN and XTAL pins, with two capacitors con-
Figure 2 shows typical basic system configurations with the nected as shown in Figure 3. Capacitor values are dependent on
ADSP-2188M, two serial devices, a byte-wide EPROM, and crystal type and should be specified by the crystal manufacturer.
optional external program and data overlay memories (mode- A parallel-resonant, fundamental frequency, microprocessor-
selectable). Programmable wait state generation allows the grade crystal should be used.
processor to connect easily to slow peripheral devices. The
ADSP-2188M also provides four external interrupts and two A clock output (CLKOUT) signal is generated by the processor
serial ports or six external interrupts and one serial port. Host at the processor’s cycle rate. This can be enabled and disabled by
Memory Mode allows access to the full external data bus, but the CLKODIS bit in the SPORT0 Autobuffer Control Register.
limits addressing to a single address bit (A0). Through the use
of external hardware, additional system peripherals can be added
in this mode to generate and latch address signals.
CLKIN XTAL CLKOUT
Clock Signals DSP
The ADSP-2188M can be clocked by either a crystal or a
TTL-compatible clock signal.
Figure 3. External Crystal Connections
–10– REV. 0
ADSP-2188M
RESET 3.6 V, regardless of the external supply voltage. This feature pro-
The RESET signal initiates a master reset of the ADSP-2188M. vides maximum flexibility in mixing 2.75 V and 3.3 V components.
The RESET signal must be asserted during the power-up
sequence to assure proper initialization. RESET during initial MODES OF OPERATION
power-up must be held long enough to allow the internal clock Setting Memory Mode
to stabilize. If RESET is activated any time after power-up, the Memory Mode selection for the ADSP-2188M is made during
clock continues to run and does not require stabilization time. chip reset through the use of the Mode C pin. This pin is multi-
The power-up sequence is defined as the total time required for the plexed with the DSP’s PF2 pin, so care must be taken in how
crystal oscillator circuit to stabilize after a valid VDD is applied to the mode selection is made. The two methods for selecting the
the processor, and for the internal phase-locked loop (PLL) to lock value of Mode C are active and passive.
onto the specific crystal frequency. A minimum of 2000 CLKIN Passive Configuration
cycles ensures that the PLL has locked but does not include the Passive Configuration involves the use a pull-up or pull-down
crystal oscillator start-up time. During this power-up sequence resistor connected to the Mode C pin. To minimize power con-
the RESET signal should be held low. On any subsequent resets, sumption, or if the PF2 pin is to be used as an output in the DSP
the RESET signal must meet the minimum pulsewidth specifi- application, a weak pull-up or pull-down, on the order of 10 kΩ,
cation, tRSP. can be used. This value should be sufficient to pull the pin to the
The RESET input contains some hysteresis; however, if an desired level and still allow the pin to operate as a programmable
RC circuit is used to generate the RESET signal, the use of an flag output without undue strain on the processor’s output driver.
external Schmidt trigger is recommended. For minimum power consumption during power-down, recon-
figure PF2 to be an input, as the pull-up or pull-down will
The master reset sets all internal stack pointers to the empty stack hold the pin in a known state, and will not switch.
condition, masks all interrupts, and clears the MSTAT register.
When RESET is released, if there is no pending bus request and Active Configuration
the chip is configured for booting, the boot-loading sequence is Active Configuration involves the use of a three-statable external
performed. The first instruction is fetched from on-chip pro- driver connected to the Mode C pin. A driver’s output enable
gram memory location 0x0000 once boot loading completes. should be connected to the DSP’s RESET signal such that it
only drives the PF2 pin when RESET is active (low). When
Power Supplies RESET is deasserted, the driver should three-state, thus allow-
The ADSP-2188M has separate power supply connections for ing full use of the PF2 pin as either an input or output. To
the internal (VDDINT) and external (VDDEXT) power supplies. minimize power consumption during power-down, configure
The internal supply must meet the 2.75 V requirement. The the programmable flag as an output when connected to a three-
external supply can be connected to either a 2.75 V or 3.3 V stated buffer. This ensures that the pin will be held at a constant
supply. All external supply pins must be connected to the same level, and will not oscillate should the three-state driver’s level
supply. All input and I/O pins can tolerate input voltages up to hover around the logic switching point.
REV. 0 –11–
ADSP-2188M
IACK Configuration Program Memory
Mode D = 0 and in host mode: IACK is an active, driven signal Program Memory (Full Memory Mode) is a 24-bit-wide
and cannot be “wire OR’d.” space for storing both instruction opcodes and data. The ADSP-
Mode D = 1 and in host mode: IACK is an open drain and 2188M has 48K words of Program Memory RAM on chip, and
requires an external pull-down, but multiple IACK pins can be the capability of accessing up to two 8K external memory over-
“wire OR’d” together. lay spaces using the external data bus.
Program Memory (Host Mode) allows access to all internal
MEMORY ARCHITECTURE memory. External overlay access is limited by a single external
The ADSP-2188M provides a variety of memory and peripheral address line (A0). External program execution is not available in
interface options. The key functional groups are Program Memory, host mode due to a restricted data bus that is 16 bits wide only.
Data Memory, Byte Memory, and I/O. Refer to the following
figures and tables for PM and DM memory allocations in the
ADSP-2188M.
ALWAYS
ACCESSIBLE
AT ADDRESS RESERVED 0x2000 – 0x3FFF
0x0000 – 0x1FFF
–12– REV. 0
ADSP-2188M
DATA MEMORY DATA MEMORY ADDRESS
ALWAYS 0x3FFF
32 MEMORY
ACCESSIBLE MAPPED
AT ADDRESS REGISTERS
0x2000 – 0x3FFF 0x3FE0
INTERNAL 0x3FDF
0x0000 – 0x1FFF
8160 WORDS 0x2000
0x0000 – 0x1FFF
ACCESSIBLE WHEN 0x1FFF
8K INTERNAL
DMOVLAY = 0
DMOVLAY = 0, 4, 5, 6, 7, 8
0x0000 – 0x1FFF
ACCESSIBLE WHEN OR
DMOVLAY = 4 8K EXTERNAL
0x0000 – 0x1FFF
ACCESSIBLE WHEN DMOVLAY = 1, 2 0x0000
DMOVLAY = 5
0x0000 – 0x1FFF
INTERNAL ACCESSIBLE WHEN
MEMORY DMOVLAY = 6
0x0000 – 0x1FFF
ACCESSIBLE WHEN
DMOVLAY = 7
0x0000 –0x1FFF
ACCESSIBLE WHEN
DMOVLAY = 8
ACCESSIBLE WHEN 0x0000 –0x1FFF
DMOVLAY = 1
EXTERNAL ACCESSIBLE WHEN
MEMORY DMOVLAY = 2
Data Memory
Data Memory (Full Memory Mode) is a 16-bit-wide space PROGRAMMABLE FLAG
used for the storage of data variables and for memory-mapped AND COMPOSITE SELECT CONTROL
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
control registers. The ADSP-2188M has 56K words on Data 1 1 1 1 1 0 1 1 0 0 0 0 0 0 0 0 DM(0x3FE6)
Memory RAM on-chip. Part of this space is used by 32 memory-
mapped registers. Support also exists for up to two 8K external BMWAIT CMSSEL PFTYPE
0 = DISABLE CMS 0 = INPUT
memory overlay spaces through the external data bus. All internal 1 = ENABLE CMS 1 = OUTPUT
accesses complete in one cycle. Accesses to external memory are (WHERE BIT: 11-IOM, 10-BM, 9-DM, 8-PM)
timed using the wait states specified by the DWAIT register and
the wait state mode bit. Figure 7. Programmable Flag and Composite Control
Register
Data Memory (Host Mode) allows access to all internal memory.
External overlay access is limited by a single external address
line (A0). SYSTEM CONTROL
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Memory Mapped Registers (New to the ADSP-2188M)
0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 DM(0x3FFF)
The ADSP-2188M has three memory mapped registers that differ
from other ADSP-21xx Family DSPs. The slight modifications RESERVED RESERVED, ALWAYS PWAIT
SET TO 0 SET TO 0 PROGRAM MEMORY
to these registers (Wait State Control, Programmable Flag and WAIT STATES
Composite Select Control, and System Control) provide the SPORT0 ENABLE
0 = DISABLE
ADSP-2188M’s wait state and BMS control features. Default 1 = ENABLE DISABLE BMS
0 = ENABLE BMS
bit values at reset are shown; if no value is shown, the bit is unde- SPORT1 ENABLE 1 = DISABLE BMS, EXCEPT WHEN MEMORY
fined at reset. Reserved bits are shown on a grey field. These bits 0 = DISABLE STROBES ARE THREE-STATED
1 = ENABLE
should always be written with zeros.
WAITSTATE CONTROL SPORT1 CONFIGURE
0 = FI, FO, IRQ0, IRQ1, SCLK
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 = SPORT1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DM(0x3FFE)
NOTE: RESERVED BITS ARE SHOWN ON A GRAY FIELD. THESE BITS SHOULD
ALWAYS BE WRITTEN WITH ZEROS.
DWAIT IOWAIT3 IOWAIT2 IOWAIT1 IOWAIT0
Figure 8. System Control Register
WAIT STATE MODE SELECT
0 = NORMAL MODE (PWAIT, DWAIT, IOWAIT0–3 = N WAIT STATES, RANGING
FROM 0 TO 7)
1 = 2N + 1 MODE (PWAIT, DWAIT, IOWAIT0–3 = 2N + 1 WAIT STATES, RANGING
FROM 0 TO 15)
REV. 0 –13–
ADSP-2188M
I/O Space (Full Memory Mode) The byte memory space on the ADSP-2188M supports read and
The ADSP-2188M supports an additional external memory write operations as well as four different data formats. The byte
space called I/O space. This space is designed to support simple memory uses data bits 15:8 for data. The byte memory uses data
connections to peripherals (such as data converters and external bits 23:16 and address bits 13:0 to create a 22-bit address. This
registers) or to bus interface ASIC data registers. I/O space sup- allows up to a 4 meg × 8 (32 megabit) ROM or RAM to be used
ports 2048 locations of 16-bit wide data. The lower eleven bits without glue logic. All byte memory accesses are timed by the
of the external address bus are used; the upper three bits are BMWAIT register and the wait state mode bit.
undefined. Two instructions were added to the core ADSP-2100
Byte Memory DMA (BDMA, Full Memory Mode)
Family instruction set to read from and write to I/O memory
The byte memory DMA controller allows loading and storing of
space. The I/O space also has four dedicated three-bit wait state
program instructions and data using the byte memory space. The
registers, IOWAIT0–3, which in combination with the wait state
BDMA circuit is able to access the byte memory space while the
mode bit, specify up to 15 wait states to be automatically gener-
processor is operating normally and steals only one DSP cycle
ated for each of four regions. The wait states act on address
per 8-, 16- or 24-bit word transferred.
ranges as shown in Table V.
BDMA CONTROL
Table V. Wait States 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 DM (0x3FE3)
Address Range Wait State Register
BMPAGE BDMA BTYPE
0x000–0x1FF IOWAIT0 and Wait State Mode Select Bit OVERLAY BDIR
BITS 0 = LOAD FROM BM
0x200–0x3FF IOWAIT1 and Wait State Mode Select Bit 1 = STORE TO BM
0x400–0x5FF IOWAIT2 and Wait State Mode Select Bit BCR
0 = RUN DURING BDMA
0x600–0x7FF IOWAIT3 and Wait State Mode Select Bit 1 = HALT DURING BDMA
–14– REV. 0
ADSP-2188M
When the BWCOUNT register is written with a nonzero value IDMA Port access occurs in two phases. The first is the IDMA
the BDMA circuit starts executing byte memory accesses with wait Address Latch cycle. When the acknowledge is asserted, a 14-bit
states set by BMWAIT. These accesses continue until the count address and 1-bit destination type can be driven onto the bus by
reaches zero. When enough accesses have occurred to create a an external device. The address specifies an on-chip memory
destination word, it is transferred to or from on-chip memory. location, the destination type specifies whether it is a DM or
The transfer takes one DSP cycle. DSP accesses to external PM access. The falling edge of the IDMA address latch signal
memory have priority over BDMA byte memory accesses. (IAL) or the missing edge of the IDMA select signal (IS) latches
The BDMA Context Reset bit (BCR) controls whether the this value into the IDMAA register.
processor is held off while the BDMA accesses are occurring. Once the address is stored, data can be read from, or written to,
Setting the BCR bit to 0 allows the processor to continue opera- the ADSP-2188M’s on-chip memory. Asserting the select line
tions. Setting the BCR bit to 1 causes the processor to stop (IS) and the appropriate read or write line (IRD and IWR
execution while the BDMA accesses are occurring, to clear the respectively) signals the ADSP-2188M that a particular transac-
context of the processor, and start execution at address 0 when tion is required. In either case, there is a one-processor-cycle
the BDMA accesses have completed. delay for synchronization. The memory access consumes one
The BDMA overlay bits specify the OVLAY memory blocks to additional processor cycle.
be accessed for internal memory. Once an access has occurred, the latched address is automati-
The BMWAIT field, which has 4 bits on ADSP-2188M, allows cally incremented, and another access can occur.
selection up to 15 wait states for BDMA transfers. Through the IDMAA register, the DSP can also specify the
Internal Memory DMA Port (IDMA Port; Host Memory starting address and data format for DMA operation. Asserting
Mode) the IDMA port select (IS) and address latch enable (IAL) directs
The IDMA Port provides an efficient means of communication the ADSP-2188M to write the address onto the IAD0–14 bus
between a host system and the ADSP-2188M. The port is used into the IDMA Control Register. If Bit 15 is set to 0, IDMA
to access the on-chip program memory and data memory of the latches the address. If Bit 15 is set to 1, IDMA latches into the
DSP with only one DSP cycle per word overhead. The IDMA OVLAY register. This register, shown below, is memory mapped
port cannot, however, be used to write to the DSP’s memory- at address DM (0x3FE0). Note that the latched address (IDMAA)
mapped control registers. A typical IDMA transfer process is cannot be read back by the host. When Bit 14 in 0x3FE7 is set
described as follows: to 1, timing in Figure 31 applies for short reads. When Bit 14
in 0x3FE7 is set to zero, short reads use the timing shown in Fig-
1. Host starts IDMA transfer
ure 32.
2. Host checks IACK control line to see if the DSP is busy
Refer to the following figures for more information on IDMA
3. Host uses IS and IAL control lines to latch either the DMA and DMA memory maps.
starting address (IDMAA) or the PM/DM OVLAY selection
into the DSP’s IDMA control registers. If Bit 15 = 1, the IDMA OVERLAY
value of bits 7:0 represent the IDMA overlay: bits 14:8 must 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x3FE7)
be set to 0. If Bit 15 = 0, the value of Bits 13:0 represent the
starting address of internal memory to be accessed and RESERVED SET TO 0 IDDMOVLAY IDPMOVLAY
Bit 14 reflects PM or DM for access.
SHORT READ ONLY
4. Host uses IS and IRD (or IWR) to read (or write) DSP inter- RESERVED SET TO 0
0 = ENABLE
1 = DISABLE
nal memory (PM or DM).
IDMA CONTROL (U = UNDEFINED AT RESET)
5. Host checks IACK line to see if the DSP has completed the 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
previous IDMA operation. 0 U U U U U U U U U U U U U U U DM (0x3FE0)
pletely asynchronous and can be written while the ADSP-2188M NOTE: RESERVED BITS ARE SHOWN ON A GRAY FIELD. THESE BITS SHOULD
is operating at full speed. ALWAYS BE WRITTEN WITH ZEROS.
The DSP memory address is latched and then automatically incre- Figure 10. IDMA Control/OVLAY Registers
mented after each IDMA transaction. An external device can
therefore access a block of sequentially addressed memory by
specifying only the starting address of the block. This increases
throughput as the address does not have to be sent for each
memory access.
REV. 0 –15–
ADSP-2188M
DMA DMA
PROGRAM MEMORY DATA MEMORY
OVLAY OVLAY
ALWAYS ALWAYS
ACCESSIBLE ACCESSIBLE
AT ADDRESS AT ADDRESS
0x0000 – 0x1FFF 0x2000 – 0x3FFF
–16– REV. 0
ADSP-2188M
In addition to the programmable flags, the ADSP-2188M has five
ERESET
fixed-mode flags, FI, FO, FL0, FL1, and FL2. FL0–FL2 are
RESET
dedicated output flags. FI and FO are available as an alternate
configuration of SPORT1. ADSP-2188M
Note: Pins PF0, PF1, PF2, and PF3 are also used for device
1k⍀
configuration during reset. MODE A/PFO
REV. 0 –17–
ADSP-2188M
The 14-pin, 2-row pin strip header is keyed at the Pin 7 loca- Restriction: All memory strobe signals on the ADSP-2188M
tion—you must remove Pin 7 from the header. The pins must (RD, WR, PMS, DMS, BMS, CMS, and IOMS) used in your
be 0.025 inch square and at least 0.20 inch in length. Pin spac- target system must have 10 kΩ pull-up resistors connected when
ing should be 0.1 × 0.1 inches. The pin strip header must have the EZ-ICE is being used. The pull-up resistors are necessary
at least 0.15 inch clearance on all sides to accept the EZ- ICE because there are no internal pull-ups to guarantee their state
probe plug. during prolonged three-state conditions resulting from typical
Pin strip headers are available from vendors such as 3M, EZ-ICE debugging sessions. These resistors may be removed at
McKenzie, and Samtec. your option when the EZ-ICE is not being used.
Target Memory Interface Target System Interface Signals
For your target system to be compatible with the EZ-ICE When the EZ-ICE board is installed, the performance on some
emulator, it must comply with the memory interface guidelines system signals change. Design your system to be compatible
listed below. with the following system interface signal changes introduced by
the EZ-ICE board:
PM, DM, BM, IOM, AND CM • EZ-ICE emulation introduces an 8 ns propagation delay
Design your Program Memory (PM), Data Memory (DM), Byte between your target circuitry and the DSP on the RESET
Memory (BM), I/O Memory (IOM), and Composite Memory signal.
(CM) external interfaces to comply with worst case device tim- • EZ-ICE emulation introduces an 8 ns propagation delay
ing requirements and switching characteristics as specified in between your target circuitry and the DSP on the BR signal.
this data sheet. The performance of the EZ- ICE may approach
published worst case specification for some memory access • EZ-ICE emulation ignores RESET and BR when single-
timing requirements and switching characteristics. stepping.
Note: If your target does not meet the worst-case chip specifica- • EZ-ICE emulation ignores RESET and BR when in Emulator
tion for memory access parameters, you may not be able to Space (DSP halted).
emulate your circuitry at the desired CLKIN frequency. Depend- • EZ-ICE emulation ignores the state of target BR in certain
ing on the severity of the specification violation, you may have modes. As a result, the target system may take control of the
trouble manufacturing your system as DSP components statisti- DSP’s external memory bus only if bus grant (BG) is asserted
cally vary in switching characteristic and timing requirements by the EZ- ICE board’s DSP.
within published limits.
–18– REV. 0
ADSP-2188M
SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
K Grade B Grade
Parameter Min Max Min Max Unit
VDDINT 2.61 2.89 2.25 2.75 V
VDDEXT 2.61 3.6 2.25 3.6 V
VINPUT1 VIL = –0.3 VIH = +3.6 VIL = –0.3 VIH = +3.6 V
TAMB 0 +70 –40 +85 °C
NOTES
1
The ADSP-2188M is 3.3 V tolerant (always accepts up to 3.6 V max V IH), but voltage compliance (on outputs, V OH) depends on the input VDDEXT; because VOH (max)
≈ VDDEXT (max). This applies to bidirectional pins (D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS 0, TFS1, A1–A13, PF0–PF7) and input only pins (CLKIN, RESET,
BR, DR0, DR1, PWD).
Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICS
K/B Grades
Parameter Test Conditions Min Typ Max Unit
VIH Hi-Level Input Voltage1, 2 @ VDDINT = max 1.5 V
VIH Hi-Level CLKIN Voltage @ VDDINT = max 2.0 V
VIL Lo-Level Input Voltage1, 3 @ VDDINT = min 0.7 V
VOH Hi-Level Output Voltage1, 4, 5 @ VDDEXT = min, IOH = –0.5 mA 2.0 V
@ VDDEXT = 3.0 V, IOH = –0.5 mA 2.4 V
@ VDDEXT = min, IOH = –100 µA6 VDDEXT – 0.3 V
VOL Lo-Level Output Voltage1, 4, 5 @ VDDEXT = min, IOL = 2 mA 0.4 V
IIH Hi-Level Input Current3 @ VDDINT = max, VIN = 3.6 V 10 µA
IIL Lo-Level Input Current3 @ VDDINT = max, VIN = 0 V 10 µA
IOZH Three-State Leakage Current7 @ VDDEXT = max, VIN = 3.6 V8 10 µA
IOZL Three-State Leakage Current7 @ VDDEXT = max, VIN = 0 V8 10 µA
IDD Supply Current (Idle)9 @ VDDINT = 2.75, tCK = 15 ns 9 mA
IDD Supply Current (Idle)9 @ VDDINT = 2.75, tCK = 13.3 ns 10 mA
IDD Supply Current (Dynamic)10 @ VDDINT = 2.75, tCK = 15 ns11, TAMB = 25°C 44 mA
IDD Supply Current (Dynamic)10 @ VDDINT = 2.75, tCK = 13.3 ns11, TAMB = 25°C 42 mA
IDD Supply Current (Power-Down)12 @ VDDINT = 2.75, TAMB = 25°C in Lowest 100 µA
Power Mode
CI Input Pin Capacitance3, 6 @ VIN = 2.75 V, fIN = 1.0 MHz, TAMB = 25°C 8 pF
CO Output Pin Capacitance6, 7, 12, 13 @ VIN = 2.75 V, fIN = 1.0 MHz, TAMB = 25°C 8 pF
NOTES
1
Bidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7.
2
Input only pins: RESET, BR, DR0, DR1, PWD.
3
Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD.
4
Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2–0, BGH.
5
Although specified for TTL outputs, all ADSP-2188M outputs are CMOS-compatible and will drive to V DDEXT and GND, assuming no dc loads.
6
Guaranteed but not tested.
7
Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0–PF7.
8
0 V on BR.
9
Idle refers to ADSP-2188M state of operation during execution of IDLE instruction. Deasserted pins are driven to either V DD or GND.
10
IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (Types 1, 4, 5, 12, 13, 14), 30% are Type 2
and Type 6, and 20% are idle instructions.
11
VIN = 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section.
12
See Chapter 9 of the ADSP-2100 Family User’s Manual for details.
13
Output pin capacitance is the capacitive load for any three-stated output pin.
Specifications subject to change without notice.
REV. 0 –19–
ADSP-2188M
ABSOLUTE MAXIMUM RATINGS 1 NOTES
1
Stresses greater than those listed may cause permanent damage to the device.
Value These are stress ratings only; functional operation of the device at these or any other
Parameter Min Max conditions greater than those indicated in the operational sections of this specifi-
cation is not implied. Exposure to absolute maximum rating conditions for
Internal Supply Voltage (VDDINT) –0.3 V +3.0 V extended periods may affect device reliability.
External Supply Voltage (VDDEXT) –0.3 V +4.0 V 2
Applies to Bidirectional pins (D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0,
Input Voltage2 –0.5 V +4.0 V TFS1, A1–A13, PF0–PF7) and Input only pins (CLKIN, RESET, BR, DR0,
DR1, PWD).
Output Voltage Swing3 –0.5 V VDDEXT + 0.5 V 3
Applies to Output pins (BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK,
Operating Temperature Range –40°C +85°C A0, DT0, DT1, CLKOUT, FL2–0, BGH).
Storage Temperature Range –65°C +150°C
Lead Temperature (5 sec) LQFP 280°C
ESD SENSITIVITY
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although WARNING!
the ADSP-2188M features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
ESD SENSITIVE DEVICE
recommended to avoid performance degradation or loss of functionality.
–20– REV. 0
ADSP-2188M
FREQUENCY DEPENDENCY FOR TIMING • Each address and data pin has a 10 pF total load at the pin.
SPECIFICATIONS • The application operates at VDDEXT = 3.3 V and tCK = 30 ns.
tCK is defined as 0.5 tCKI. The ADSP-2188M uses an input clock
with a frequency equal to half the instruction rate. For example, Total Power Dissipation = PINT + (C × VDDEXT2 × f )
a 37.50 MHz input clock (which is equivalent to 26.6 ns) yields PINT = internal power dissipation from Power vs. Frequency
a 13.3 ns processor cycle (equivalent to 75 MHz). tCK values graph (Figure 15).
within the range of 0.5 tCKI period should be substituted for all
(C × VDDEXT2 × f ) is calculated for each output:
relevant timing parameters to obtain the specification value.
Example: tCKH = 0.5 tCK – 2 ns = 0.5 (15 ns) – 2 ns = 5.5 ns
# of ⴛC ⴛ VDDEXT2 ⴛ f PD
1 Parameters Pins pF V MHz mW
ENVIRONMENTAL CONDITIONS
Address 7 10 3.32 16.67 12.7
Rating Data Output, WR 9 10 3.32 16.67 16.3
Description Symbol LQFP Mini-BGA RD 1 10 3.32 16.67 1.8
Thermal Resistance θCA 48°C/W 63.3°C/W CLKOUT, DMS 2 10 3.32 33.3 7.2
(Case-to-Ambient) 38.0
Thermal Resistance θJA 50°C/W 70.7°C/W
(Junction-to-Ambient) Total power dissipation for this example is PINT + 38.0 mW.
Thermal Resistance θJC 2°C/W 7.4°C/W Output Drive Currents
(Junction-to-Case) Figure 14 shows typical I-V characteristics for the output drivers
NOTE on the ADSP-2188M. The curves represent the current drive
1
Where the Ambient Temperature Rating (T AMB) is: capability of the output drivers as a function of output voltage.
TAMB = TCASE – (PD × θCA)
TCASE = Case Temperature in °C 80
PD = Power Dissipation in W
60 VOH
VDDEXT = 3.6V @ –40ⴗC
POWER DISSIPATION
40
SOURCE CURRENT – mA
Assumptions: –80
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
• External data memory is accessed every cycle with 50% of the SOURCE VOLTAGE – V
address pins switching.
Figure 14. Typical Output Driver Characteristics
• External data memory writes occur every other cycle with
50% of the data pins switching.
REV. 0 –21–
ADSP-2188M
POWER, INTERNAL1, 2, 3 Capacitive Loading
150 Figure 16 and Figure 17 show the capacitive loading character-
145 145mW
140 istics of the ADSP-2188M.
135 129mW
.9V
POWER (PINT) – mW
130 30
125 =2
T T = 85ⴗC
VD DIN
120 VDD = 0V TO 2.0V
5V
115
= 2.7 111mW 25
110 INT
POWER, IDLE1, 2, 4 5
45
0
40 0 50 100 150 200 250 300
36mW CL – pF
POWER (PIDLE) – mW
35
= 2.9V 32mW Figure 16. Typical Output Rise Time vs. Load Capacitance
V DDINT
30 V
(at Maximum Ambient Operating Temperature)
= 2.75 28mW
V DDINT
28mW 18
25 = 2.6V
V DDINT
24mW 16
VALID OUTPUT DELAY OR HOLD – ns
20 14
20mW
12
15 10
50 55 60 65 70 75
1/tCK – MHz 8
2
35
NOMINAL
32mW
POWER (PIDLEn) – mW
–2
30
IDLE
–4
24mW
25 –6
21mW 0 50 100 150 200 250
IDLE (16) CL – pF
20 19mW
IDLE (128)
19mW Figure 17. Typical Output Valid Delay or Hold vs. Load
18mW
15 Capacitance, CL (at Maximum Ambient Operating
Temperature)
10
50 55 60 65 70 75
1/tCK – MHz
NOTES:
VALID FOR ALL TEMPERATURE GRADES.
1 POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.
2 TYPICAL POWER DISSIPATION AT 2.75V V
DDINT AND 25ⴗC, EXCEPT
WHERE SPECIFIED.
3I
DD MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING
FROM INTERNAL MEMORY. 50% OF THE INSTRUCTIONS ARE
MULTIFUNCTION (TYPES 1, 4, 5, 12, 13, 14), 30% ARE TYPE 2 AND
TYPE 6, AND 20% ARE IDLE INSTRUCTIONS.
4 IDLE REFERS TO STATE OF OPERATION DURING EXECUTION
OF IDLE INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO
EITHER VDD OR GND.
–22– REV. 0
ADSP-2188M
TEST CONDITIONS Output Enable Time
Output Disable Time Output pins are considered to be enabled when they have made
Output pins are considered to be disabled when they have stopped a transition from a high-impedance state to when they start driving.
driving and started a transition from the measured output high The output enable time (tENA) is the interval from when a refer-
or low voltage to a high impedance state. The output disable ence signal reaches a high or low voltage level to when the output
time (tDIS) is the difference of tMEASURED and tDECAY, as shown has reached a specified high or low trip point, as shown Figure
in the Output Enable/Disable diagram. The time is the interval 19. If multiple pins (such as the data bus) are enabled, the mea-
from when a reference signal reaches a high or low voltage level surement value is that of the first pin to start driving.
to when the output voltages have changed by 0.5 V from the
measured output high or low voltage. REFERENCE
SIGNAL
The decay time, tDECAY, is dependent on the capacitive load, tMEASURED
CL, and the current load, iL, on the output pin. It can be tENA
approximated by the following equation: VOH tDIS VOH
(MEASURED) (MEASURED)
C L × 0.5V VOH (MEASURED) – 0.5V
t DECAY = OUTPUT
2.0V
iL VOL (MEASURED) +0.5V 1.0V
from which VOL
tDECAY
VOL
(MEASURED) (MEASURED)
tDIS = tMEASURED – tDECAY OUTPUT
OUTPUT STOPS STARTS
is calculated. If multiple pins (such as the data bus) are disabled, DRIVING DRIVING
the measurement value is that of the last pin to stop driving. HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.
IOL
2.0V
OUTPUT 1.5V
0.8V
IOH
REV. 0 –23–
ADSP-2188M
Parameter Min Max Unit
Clock Signals and Reset
Timing Requirements:
tCKI CLKIN Period 26.6 80 ns
tCKIL CLKIN Width Low 8 ns
tCKIH CLKIN Width High 8 ns
Switching Characteristics:
tCKL CLKOUT Width Low 0.5tCK – 2 ns
tCKH CLKOUT Width High 0.5tCK – 2 ns
tCKOH CLKIN High to CLKOUT High 0 13 ns
Control Signals Timing Requirements:
tRSP RESET Width Low 5tCK1 ns
tMS Mode Setup before RESET High 2 ns
tMH Mode Hold after RESET High 5 ns
NOTE
1
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).
tCKI
tCKIH
CLKIN
tCKIL
tCKOH
tCKH
CLKOUT
tCKL
PF(3:0)*
tMS tMH
RESET
tRSP
–24– REV. 0
ADSP-2188M
Parameter Min Max Unit
Interrupts and Flags
Timing Requirements:
tIFS IRQx, FI, or PFx Setup before CLKOUT Low1, 2, 3, 4 0.25tCK + 10 ns
tIFH IRQx, FI, or PFx Hold after CLKOUT High1, 2, 3, 4 0.25tCK ns
Switching Characteristics:
tFOH Flag Output Hold after CLKOUT Low5 0.5tCK – 5 ns
tFOD Flag Output Delay from CLKOUT Low5 0.5tCK + 4 ns
NOTES
1
If IRQx and FI inputs meet t IFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on
the following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the ADSP-2100 Family User’s Manual for further information on
interrupt servicing.)
2
Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.
3
IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQLE.
4
PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.
5
Flag Outputs = PFx, FL0, FL1, FL2, FO.
tFOD
CLKOUT
tFOH
FLAG
OUTPUTS
tIFH
IRQx
FI
PFx
tIFS
REV. 0 –25–
ADSP-2188M
Parameter Min Max Unit
Bus Request–Bus Grant
Timing Requirements:
tBH BR Hold after CLKOUT High1 0.25tCK + 2 ns
tBS BR Setup before CLKOUT Low1 0.25tCK + 10 ns
Switching Characteristics:
tSD CLKOUT High to xMS, RD, WR Disable 0.25tCK + 8 ns
tSDB xMS, RD, WR Disable to BG Low 0 ns
tSE BG High to xMS, RD, WR Enable 0 ns
tSEC xMS, RD, WR Enable to CLKOUT High 0.25tCK – 3 ns
tSDBH xMS, RD, WR Disable to BGH Low2 0 ns
tSEH BGH High to xMS, RD, WR Enable2 0 ns
NOTES
xMS = PMS, DMS, CMS, IOMS, BMS.
1
BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on
the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships.
2
BGH is asserted when the bus is granted and the processor or BDMA requires control of the bus to continue.
tBH
CLKOUT
BR
tBS
CLKOUT
PMS, DMS
BMS, RD
WR tSD tSEC
BG
tSDB
tSE
BGH
tSDBH
tSEH
–26– REV. 0
ADSP-2188M
Parameter Min Max Unit
Memory Read
Timing Requirements:
tRDD RD Low to Data Valid 0.5tCK – 5 + w ns
tAA A0–A13, xMS to Data Valid 0.75tCK – 6 + w ns
tRDH Data Hold from RD High 0 ns
Switching Characteristics:
tRP RD Pulsewidth 0.5tCK – 3 + w ns
tCRD CLKOUT High to RD Low 0.25tCK – 2 0.25tCK + 4 ns
tASR A0–A13, xMS Setup before RD Low 0.25tCK – 3 ns
tRDA A0–A13, xMS Hold after RD Deasserted 0.25tCK – 3 ns
tRWR RD High to RD or WR Low 0.5tCK – 3 ns
NOTES
w = wait states x t CK.
xMS = PMS, DMS, CMS, IOMS, BMS.
CLKOUT
A0–A13
DMS, PMS,
BMS, IOMS,
CMS
tRDA
RD
tASR
tRP tRWR
tCRD
D0–D23
tRDD tRDH
tAA
WR
REV. 0 –27–
ADSP-2188M
Parameter Min Max Unit
Memory Write
Switching Characteristics:
tDW Data Setup before WR High 0.5tCK – 4 + w ns
tDH Data Hold after WR High 0.25tCK – 1 ns
tWP WR Pulsewidth 0.5tCK – 3 + w ns
tWDE WR Low to Data Enabled 0 ns
tASW A0–A13, xMS Setup before WR Low 0.25tCK – 3 ns
tDDR Data Disable before WR or RD Low 0.25tCK – 3 ns
tCWR CLKOUT High to WR Low 0.25tCK – 2 0.25 tCK + 4 ns
tAW A0–A13, xMS, Setup before WR Deasserted 0.75tCK – 5 + w ns
tWRA A0–A13, xMS Hold after WR Deasserted 0.25tCK – 1 ns
tWWR WR High to RD or WR Low 0.5tCK – 3 ns
NOTES
w = wait states x tCK.
xMS = PMS, DMS, CMS, IOMS, BMS.
CLKOUT
A0–A13
DMS, PMS,
BMS, CMS,
IOMS
tWRA
WR
tDW
tWDE
RD
–28– REV. 0
ADSP-2188M
Serial Ports
Parameter Min Max Unit
Serial Ports
Timing Requirements:
tSCK SCLK Period 26.6 ns
tSCS DR/TFS/RFS Setup before SCLK Low 4 ns
tSCH DR/TFS/RFS Hold after SCLK Low 7 ns
tSCP SCLKIN Width 12 ns
Switching Characteristics:
tCC CLKOUT High to SCLKOUT 0.25tCK 0.25tCK + 6 ns
tSCDE SCLK High to DT Enable 0 ns
tSCDV SCLK High to DT Valid 12 ns
tRH TFS/RFSOUT Hold after SCLK High 0 ns
tRD TFS/RFSOUT Delay from SCLK High 12 ns
tSCDH DT Hold after SCLK High 0 ns
tTDE TFS (Alt) to DT Enable 0 ns
tTDV TFS (Alt) to DT Valid 12 ns
tSCDD SCLK High to DT Disable 12 ns
tRDV RFS (Multichannel, Frame Delay Zero) to DT Valid 12 ns
CLKOUT
tCC tCC tSCK
SCLK
tSCP
tSCS tSCH tSCP
DR
TFSIN
RFSIN
tRD
tRH
RFSOUT
TFSOUT
tSCDD
tSCDV
tSCDE tSCDH
DT
tTDE
tTDV
TFSOUT
ALTERNATE
FRAME MODE
tRDV
RFSOUT
MULTICHANNEL
MODE,
FRAME DELAY 0
(MFD = 0) tTDE
tTDV
TFSIN
ALTERNATE
FRAME MODE
tRDV
RFSIN
MULTICHANNEL
MODE,
FRAME DELAY 0
(MFD = 0)
REV. 0 –29–
ADSP-2188M
Parameter Min Max Unit
IDMA Address Latch
Timing Requirements:
tIALP Duration of Address Latch1, 2 10 ns
tIASU IAD15–0 Address Setup before Address Latch End2 5 ns
tIAH IAD15–0 Address Hold after Address Latch End2 3 ns
tIKA IACK Low before Start of Address Latch2, 3 0 ns
tIALS Start of Write or Read after Address Latch End2, 3 3 ns
tIALD Address Latch Start after Address Latch End1, 2 2 ns
NOTES
1
Start of Address Latch = IS Low and IAL High.
2
End of Address Latch = IS High or IAL Low.
3
Start of Write or Read = IS Low and IWR Low or IRD Low.
IACK
tIKA
tIALD
IAL
tIALP tIALP
IS
IAD15–0
tIASU tIASU
tIAH tIAH
tIALS
IRD OR IWR
–30– REV. 0
ADSP-2188M
Parameter Min Max Unit
IDMA Write, Short Write Cycle
Timing Requirements:
tIKW IACK Low before Start of Write1 0 ns
tIWP Duration of Write1, 2 10 ns
tIDSU IAD15–0 Data Setup before End of Write2, 3, 4 3 ns
tIDH IAD15–0 Data Hold after End of Write2, 3, 4 2 ns
Switching Characteristic:
tIKHW Start of Write to IACK High 10 ns
NOTES
1
Start of Write = IS Low and IWR Low.
2
End of Write = IS High or IWR High.
3
If Write Pulse ends before IACK Low, use specifications t IDSU, tIDH.
4
If Write Pulse ends after IACK Low, use specifications t IKSU, tIKH.
tIKW
IACK
tIKHW
IS
tIWP
IWR
tIDH
tIDSU
IAD15–0 DATA
REV. 0 –31–
ADSP-2188M
Parameter Min Max Unit
IDMA Write, Long Write Cycle
Timing Requirements:
tIKW IACK Low before Start of Write1 0 ns
tIKSU IAD15–0 Data Setup before End of Write2, 3, 4 0.5tCK + 5 ns
tIKH IAD15–0 Data Hold after End of Write2, 3, 4 0 ns
Switching Characteristics:
tIKLW Start of Write to IACK Low4 1.5tCK ns
tIKHW Start of Write to IACK High 10 ns
NOTES
1
Start of Write = IS Low and IWR Low.
2
If Write Pulse ends before IACK Low, use specifications t IDSU, tIDH.
3
If Write Pulse ends after IACK Low, use specifications t IKSU, tIKH.
4
This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User’s Manual.
tIKW
IACK
tIKHW
tIKLW
IS
IWR
tIKSU
tIKH
IAD15–0 DATA
–32– REV. 0
ADSP-2188M
Parameter Min Max Unit
IDMA Read, Long Read Cycle
Timing Requirements:
tIKR IACK Low before Start of Read1 0 ns
tIRK End of read after IACK Low2 2 ns
Switching Characteristics:
tIKHR IACK High after Start of Read1 10 ns
tIKDS IAD15–0 Data Setup before IACK Low 0.5tCK – 2 ns
tIKDH IAD15–0 Data Hold after End of Read2 0 ns
tIKDD IAD15–0 Data Disabled after End of Read2 10 ns
tIRDE IAD15–0 Previous Data Enabled after Start of Read 0 ns
tIRDV IAD15–0 Previous Data Valid after Start of Read 11 ns
tIRDH1 IAD15–0 Previous Data Hold after Start of Read (DM/PM1)3 2tCK – 5 ns
tIRDH2 IAD15–0 Previous Data Hold after Start of Read (PM2)4 tCK – 5 ns
NOTES
1
Start of Read = IS Low and IRD Low.
2
End of Read = IS High or IRD High.
3
DM read or first half of PM read.
4
Second half of PM read.
IACK
tIKHR
tIKR
IS
tIRK
IRD
PREVIOUS READ
IAD15–0 DATA DATA
tIRDV tIKDD
tIRDH1 or tIRDH2
REV. 0 –33–
ADSP-2188M
Parameter Min Max Unit
IDMA Read, Short Read Cycle1, 2
Timing Requirements:
tIKR IACK Low before Start of Read3 0 ns
tIRP1 Duration of Read (DM/PM1)4 10 2tCK – 5 ns
tIRP2 Duration of Read (PM2)5 10 tCK – 5 ns
Switching Characteristics:
tIKHR IACK High after Start of Read3 10 ns
tIKDH IAD15–0 Data Hold after End of Read6 0 ns
tIKDD IAD15–0 Data Disabled after End of Read6 10 ns
tIRDE IAD15–0 Previous Data Enabled after Start of Read 0 ns
tIRDV IAD15–0 Previous Data Valid after Start of Read 10 ns
NOTES
1
Short Read Only must be disabled in the IDMA Overlay memory mapped register.
2
Consider using the Short Read Only mode, instead, because Short Read mode is not applicable at high clock frequencies.
3
Start of Read = IS Low and IRD Low.
4
DM Read or first half of PM Read.
5
Second half of PM Read.
6
End of Read = IS High or IRD High.
IACK
tIKR
tIKHR
IS
tIRP
IRD
tIRDE tIKDH
IAD15–0 PREVIOUS
DATA
tIRDV tIKDD
–34– REV. 0
ADSP-2188M
Parameter Min Max Unit
1
IDMA Read, Short Read Cycle in Short Read Only Mode
Timing Requirements:
tIKR IACK Low before Start of Read2 0 ns
tIRP Duration of Read3 10 ns
Switching Characteristics:
tIKHR IACK High after Start of Read2 10 ns
tIKDH IAD15–0 Previous Data Hold after End of Read3 0 ns
tIKDD IAD15–0 Previous Data Disabled after End of Read3 10 ns
tIRDE IAD15–0 Previous Data Enabled after Start of Read 0 ns
tIRDV IAD15–0 Previous Data Valid after Start of Read 10 ns
NOTES
1
Short Read Only is enabled by setting Bit 14 of the IDMA Overlay Register to 1 (0x3FE7). Short Read Only can be enabled by the processor core writing to the
register or by an external host writing to the register. Disabled by default.
2
Start of Read = IS Low and IRD Low. Previous data remains until end of read.
3
End of Read = IS High or IRD High.
IACK
tIKR
tIKHR
IS
tIRP
IRD
tIRDE tIKDH
IAD15–0 PREVIOUS
DATA
tIRDV tIKDD
REV. 0 –35–
ADSP-2188M
100-LEAD LQFP PIN CONFIGURATION
93 PF1 [MODE B]
88 PF3 [MODE D]
94 PF0 [MODE A]
89 PF2 [MODE C]
96 PWDACK
98 A1/IAD0
99 A2/IAD1
100 A3/IAD2
90 VDDEXT
92 GND
91 PWD
95 BGH
80 GND
84 D23
77 D17
76 D16
82 D21
81 D20
79 D19
78 D18
83 D22
85 FL2
87 FL0
86 FL1
97 A0
A4/IAD3 1 75 D15
A5/IAD4 2 PIN 1 74 D14
IDENTIFIER
GND 3 73 D13
A6/IAD5 4 72 D12
A7/IAD6 5 71 GND
A8/IAD7 6 70 D11
A9/IAD8 7 69 D10
A10/IAD9 8 68 D9
A11/IAD10 9 67 VDDEXT
A12/IAD11 10 66 GND
A13/IAD12 11 65 D8
GND 12 64 D7/IWR
CLKIN 13
ADSP-2188M 63 D6/IRD
XTAL 14 TOP VIEW 62 D5/IAL
(Not to Scale)
VDDEXT 15 61 D4/IS
CLKOUT 16 60 GND
GND 17 59 VDD INT
VDDINT 18 58 D3/IACK
WR 19 57 D2/IAD15
RD 20 56 D1/IAD14
BMS 21 55 D0/IAD13
DMS 22 54 BG
PMS 23 53 EBG
IOMS 24 52 BR
CMS 25 51 EBR
VDDEXT 36
DT1/FO 37
RFS1/IRQ0 39
GND 41
SCLK1 42
RESET 44
EE 46
ECLK 47
ELIN 49
IRQL0+PF5 27
SCLK0 35
IRQL1+PF6 29
DT0 31
TFS1/IRQ1 38
TFS0 32
DR1/FI 40
DR0 34
EINT 50
ERESET 43
EMS 45
ELOUT 48
GND 28
IRQ2+PF7 30
RFS0 33
IRQE+PF4 26
–36– REV. 0
ADSP-2188M
The LQFP package pinout is shown in the table below. Pin names in bold text replace the plain text named functions when
Mode C = 1. A + sign separates two functions when either function can be active for either major I/O mode. Signals enclosed in
brackets [ ] are state bits latched from the value of the pin at the deassertion of RESET.
The multiplexed pins DT1/FO, TFS1/IRQ1, RFS1/IRQ0, and DR1/FI, are mode selectable by setting Bit 10 (SPORT1 configure)
of the System Control Register. If Bit 10 = 1, these pins have serial port functionality. If Bit 10 = 0, these pins are the external inter-
rupt and flag pins. This bit is set to 1 by default upon reset.
REV. 0 –37–
ADSP-2188M
144-Ball Mini-BGA Package Pinout (Bottom View)
12 11 10 9 8 7 6 5 4 3 2 1
D16 D17 D18 D20 D23 VDDEXT GND NC NC GND A3/IAD2 A4/IAD3 B
D14 NC D15 D19 D21 VDDEXT PWD A7/IAD6 A5/IAD4 RD A6/IAD5 PWDACK C
PF2 PF1
GND NC D12 D13 NC
[MODE C] [MODE B]
A9/IAD8 BGH NC WR NC D
D10 GND VDDEXT GND GND PF3 FL2 PF0 FL0 A8/IAD7 VDDEXT VDDEXT E
[MODE D] [MODE A]
GND NC GND D3/IACK D2/IAD15 TFS0 DT0 VDDINT GND GND GND CLKIN H
VDDINT VDDINT D1/IAD14 BG RFS1/IRQ0 D0/IAD13 SCLK0 VDDEXT VDDEXT NC VDDINT CLKOUT J
EINT ELOUT ELIN RESET GND DR0 PMS GND IOMS IRQL1 + PF6 NC IRQE + PF4 L
ECLK EE EMS NC GND DR1/FI DT1/FO GND CMS NC IRQ2 + PF7 IRQL0 + PF5 M
–38– REV. 0
ADSP-2188M
The Mini-BGA package pinout is shown in the table below. Pin names in bold text replace the plain text named functions when
Mode C = 1. A + sign separates two functions when either function can be active for either major I/O mode. Signals enclosed in
brackets [ ] are state bits latched from the value of the pin at the deassertion of RESET.
The multiplexed pins DT1/FO, TFS1/IRQ1, RFS1/IRQ0, and DR1/FI, are mode selectable by setting Bit 10 (SPORT1 configure) of
the System Control Register. If Bit 10 = 1, these pins have serial port functionality. If Bit 10 = 0, these pins are the external interrupt
and flag pins. This bit is set to 1 by default upon reset.
Ball # Pin Name Ball # Pin Name Ball # Pin Name Ball # Pin Name
A01 A2/IAD1 D01 NC G01 XTAL K01 NC
A02 A1/IAD0 D02 WR G02 NC K02 NC
A03 GND D03 NC G03 GND K03 NC
A04 A0 D04 BGH G04 A10/IAD9 K04 BMS
A05 NC D05 A9/IAD8 G05 NC K05 DMS
A06 GND D06 PF1 [MODE B] G06 NC K06 RFS0
A07 NC D07 PF2 [MODE C] G07 NC K07 TFS1/IRQ1
A08 NC D08 NC G08 D6/IRD K08 SCLK1
A09 NC D09 D13 G09 D5/IAL K09 ERESET
A10 D22 D10 D12 G10 NC K10 EBR
A11 GND D11 NC G11 NC K11 BR
A12 GND D12 GND G12 D4/IS K12 EBG
B01 A4/IAD3 E01 VDDEXT H01 CLKIN L01 IRQE + PF4
B02 A3/IAD2 E02 VDDEXT H02 GND L02 NC
B03 GND E03 A8/IAD7 H03 GND L03 IRQL1 + PF6
B04 NC E04 FL0 H04 GND L04 IOMS
B05 NC E05 PF0 [MODE A] H05 VDDINT L05 GND
B06 GND E06 FL2 H06 DT0 L06 PMS
B07 VDDEXT E07 PF3 [MODE D] H07 TFS0 L07 DR0
B08 D23 E08 GND H08 D2/IAD15 L08 GND
B09 D20 E09 GND H09 D3/IACK L09 RESET
B10 D18 E10 VDDEXT H10 GND L10 ELIN
B11 D17 E11 GND H11 NC L11 ELOUT
B12 D16 E12 D10 H12 GND L12 EINT
C01 PWDACK F01 A13/IAD12 J01 CLKOUT M01 IRQL0 + PF5
C02 A6/IAD5 F02 NC J02 VDDINT M02 IRQL2 + PF7
C03 RD F03 A12/IAD11 J03 NC M03 NC
C04 A5/IAD4 F04 A11/IAD10 J04 VDDEXT M04 CMS
C05 A7/IAD6 F05 FL1 J05 VDDEXT M05 GND
C06 PWD F06 NC J06 SCLK0 M06 DT1/FO
C07 VDDEXT F07 NC J07 D0/IAD13 M07 DR1/FI
C08 D21 F08 D7/IWR J08 RFS1/IRQ0 M08 GND
C09 D19 F09 D11 J09 BG M09 NC
C10 D15 F10 D8 J10 D1/IAD14 M10 EMS
C11 NC F11 NC J11 VDDINT M11 EE
C12 D14 F12 D9 J12 VDDINT M12 ECLK
REV. 0 –39–
ADSP-2188M
OUTLINE DIMENSIONS
Dimensions shown in millimeters.
C01629–2.5–9/00 (rev. 0)
16.20
10.10
16.00 TYP SQ
10.00 SQ
15.80
9.90 12 11 10 9 8 7 6 5 4 3 2 1
14.05
14.00 TYP SQ A
13.95 B
1.60 MAX C
12.00 BSC
0.75 D
0.60 TYP 8.80 E
100 76 10.10 BSC F
0.50 12ⴗ 1 75
TYP 10.00 SQ TOP VIEW G
9.90 H
SEATING
PLANE 0.80 J
BSC K
L
M
TOP VIEW
(PINS DOWN) 0.80 BSC
1.40 8.80 BSC
MAX
DETAIL A
DETAIL A
0.08 1.00
25 51
MAX LEAD 26 50 NOTES: 0.85
COPLANARITY 6ⴗ ± 4ⴗ
1. THE ACTUAL POSITION OF THE BALL 0.40
0ⴗ – 7ⴗ POPULATION IS WITHIN 0.150 OF ITS 0.25
0.50 0.27 IDEAL POSITION RELATIVE TO THE
0.15 BSC 0.22 TYP PACKAGE EDGES. 0.55 0.12 SEATING
0.05 LEAD PITCH 0.17 2. THE ACTUAL POSITION OF EACH BALL 0.50 MAX PLANE
LEAD WIDTH IS WITHIN 0.08 OF ITS IDEAL POSITION 0.45
NOTE: RELATIVE TO THE BALL POPULATION. BALL DIAMETER
THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 FROM ITS IDEAL
POSITION WHEN MEASURED IN THE LATERAL DIRECTION.
ORDERING GUIDE
PRINTED IN U.S.A.
–40– REV. 0