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16 Megabit (1 M x 16-Bit)
CMOS 3.0 Volt-only Burst Mode Flash Memory
DISTINCTIVE CHARACTERISTICS
■ 32 words sequential with wrap around (linear ■ 20-year data retention
32), bottom boot ■ CFI (Common Flash Interface) compliant
■ One 8 Kword, two 4 Kword, one 112 Kword, and — Provides device-specific information to the
seven 128 Kword sectors system, allowing host software to easily
reconfigure for different Flash devices
■ Single power supply operation
— Regulated voltage range: 3.0 to 3.6 volt read ■ Compatibility with JEDEC standards
and write operations and for compatibility with — Pinout and software compatible with single-
high performance 3.3 volt microprocessors power supply Flash
■ Read access times — Superior inadvertent write protection
Burst access times as fast as 17 ns at industrial — Backward-compatible with AMD Am29LVxxx
temperature range (18 ns at extended and Am29Fxxx flash memories: powers up in
temperature range) asynchronous mode for system boot, but can
immediately be placed into burst mode
Initial/random access times as fast as 65 ns
■ Alterable burst length via BAA# pin ■ Data# Polling and toggle bits
■ Power dissipation (typical) — Provides a software method of detecting
program or erase operation completion
— Burst Mode Read: 15 mA @ 25 MHz,
20 mA @ 33 MHz, 25 mA @ 40 MHz ■ Ready/Busy# pin (RY/BY#)
— Program/Erase: 20 mA — Provides a hardware method of detecting
— Standby mode, CMOS: 3 µA program or erase cycle completion
This Data Sheet states AMD’s current specifications regarding the Products described herein. This Data Sheet may Publication# 22142 Rev: F Amendment/+5
be revised by subsequent versions or modifications due to changes in technical specifications. Issue Date: November 22, 2002
Speed Regulated Voltage Range: VCC =3.0–3.6 V 65R 70R 90R 120R
Option Temperature Range: Industrial (I), Extended (E) I E I, E I, E I, E
Note:
1. See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
DQ0–DQ15
RY/BY#
IND#
VCC
VSS Sector
Switches
Input/Output IND#
RESET# Buffers Buffer
Erase Voltage
Generator
WE# State
Control
Command
PGM Voltage
Register
Generator Chip Enable
Output Enable
CE# STB
Logic Data Latch
OE#
A3, A4
Y-Gating A0–A2
STB Y-Decoder
VCC Detector Timer
Address Latch
A0–A19
X-Decoder Cell Matrix
A0–A4
A3, A4
WE# 1 56 LBA#
RESET# 2 55 VCC
RY/BY# 3 54 NC
A18 4 53 A19
A17 5 56-Pin SSOP 52 A8
A7 6 51 A9
A6 7 50 A10
A5 8 49 A11
A4 9 48 A12
A3 10 47 A13
A2 11 46 A14
A1 12 45 A15
A0 13 44 A16
CE# 14 43 NC
NC 15 42 NC
VSS 16 41 VSS
OE# 17 40 DQ15
DQ0 18 39 DQ7
DQ8 19 38 DQ14
DQ1 20 37 DQ6
DQ9 21 36 DQ13
DQ2 22 35 DQ5
DQ10 23 34 DQ12
DQ3 24 33 DQ4
DQ11 25 32 VCC
VSS 26 31 VCC
CLK 27 30 IND#
BAA# 28 29 NC
BAA#
Am29BL162C B 65R Z I
TEMPERATURE RANGE
I = Industrial (–40°C to +85°C)
E= Extended (–55°C to +125°C)
PACKAGE TYPE
Z= 56-Pin Shrink Small Outline Package (SSOP 056)
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am29BL162C
16 Megabit (1 M x 16-Bit)
CMOS 3.0 Volt-only High Performance Burst Mode Flash Memory
Valid Combinations
Valid Combinations
Valid Combinations list configurations planned to be sup-
Am29BL162CB-65R ZI, ZE ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
Am29BL162CB-70R ZI, ZE
to check on newly released combinations.
Am29BL162CB-90R ZI, ZE
Am29BL162CB-120R ZI, ZE
VCC ± VCC ±
Standby X X X X X X HIGH Z
0.3 V 0.3 V
Reset X X X L X X X X HIGH Z
Sector Address,
Sector Protect (Note 2) L H L VID X X X A6 = L, A1 = H, DIN
A0 = L
Sector Address,
Sector Unprotect (Note 2) L H L VID X X X A6 = H, A1 = H, DIN
A0 = L
Legend:
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Notes:
1. Addresses are A19:A0.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector
Protection/Unprotection” section.
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Note: The autoselect codes may also be accessed in-system via command sequences. See Table 8.
Sector Protection/Unprotection The primary method requires VID on the RESET# pin
only, and can be implemented either in-system or via
The hardware sector protection feature disables both
programming equipment. Figure 2 shows the algo-
program and erase operations in any sector. The hard-
rithms and Figure 24 shows the timing diagram. This
ware sector unprotection feature re-enables both pro-
method uses standard microprocessor bus cycle
gram and erase operations in previously protected
timing. For sector unprotect, all unprotected sectors
sectors.
must first be protected prior to the first sector unprotect
The device is shipped with all sectors unprotected. write cycle.
AMD offers the option of programming and protecting
The alternate method intended only for programming
sectors at its factory prior to shipping the device
equipment requires VID on address pin A9 and OE#.
through AMD’s ExpressFlash™ Service. Contact an
This method is compatible with programmer routines
AMD representative for details.
written for earlier 3.0 volt-only AMD flash devices. De-
It is possible to determine whether a sector is protected tails on this method are provided in a supplement, pub-
or unprotected. See “Autoselect Mode” for details. lication number 22240. Contact an AMD representative
to request a copy.
Sector protection/unprotection can be implemented via
two methods.
Yes Yes
Set up sector
No All sectors
address
protected?
Sector Protect:
Yes
Write 60h to sector
address with Set up first sector
A6 = 0, A1 = 1, address
A0 = 0
Sector Unprotect:
Wait 150 µs
Write 60h to sector
address with
Verify Sector A6 = 1, A1 = 1,
Protect: Write 40h A0 = 0
to sector address Reset
Increment with A6 = 0, PLSCNT = 1 Wait 15 ms
PLSCNT A1 = 1, A0 = 0
Verify Sector
Read from
Unprotect: Write
sector address
40h to sector
with A6 = 0,
address with
A1 = 1, A0 = 0 Increment A6 = 1, A1 = 1,
No PLSCNT A0 = 0
No
PLSCNT Data = 01h? Read from
= 25? sector address
with A6 = 1,
Yes A1 = 1, A0 = 0
Yes No
Set up
next sector
Yes No
PLSCNT address
Protect another Data = 00h?
Device failed = 1000?
sector?
No Yes Yes
Remove VID
from RESET# Last sector No
Device failed verified?
Write reset
Yes
command
Remove VID
Sector Protect Sector Protect
Sector Unprotect from RESET#
Sector Unprotect
complete
Logical Inhibit
Temporary Sector Write cycles are inhibited by holding any one of OE# =
Unprotect Completed VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
(Note 2) CE# and WE# must be a logical zero while OE# is a
logical one.
Notes:
Power-Up Write Inhibit
1. All protected sectors unprotected.
2. All previously protected sectors are protected once If WE# = CE# = VIL and OE# = VIH during power up, the
again. device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
Figure 2. Temporary Sector Unprotect Operation reset to reading array data on power-up.
The Common Flash Interface (CFI) specification out- The system can also write the CFI query command
lines device and host system software interrogation when the device is in the autoselect mode. The device
handshake, which allows specific vendor-specified enters the CFI query mode, and the system can read
software algorithms to be used for entire families of CFI data at the addresses given in Tables 4–7. The
devices. Software support can then be device-indepen- system must write the reset command to return the
dent, JEDEC ID-independent, and forward- and back- device to the autoselect mode.
ward-compatible for the specified flash device families. For further information, please refer to the CFI Specifi-
Flash vendors can standardize their existing interfaces cation and CFI Publication 100, available via the World
for long-term compatibility. Wide Web at http://www.amd.com/products/nvd/over-
This device enters the CFI Query mode when the view/cfi.html. Alternatively, contact an AMD represen-
system writes the CFI Query command, 98h, to tative for copies of these documents.
address 55h, any time the device is ready to read array To terminate reading CFI data, the system must write
data. The system can read CFI information at the the reset command.
10h 0051h
11h 0052h Query Unique ASCII string “QRY”
12h 0059h
13h 0002h
Primary OEM Command Set
14h 0000h
15h 0040h
Address for Primary Extended Table
16h 0000h
17h 0000h
Alternate OEM Command Set (00h = none exists)
18h 0000h
19h 0000h
Address for Alternate OEM Extended Table (00h = none exists)
1Ah 0000h
22h 0000h Typical timeout for full chip erase 2N ms (00h = not supported)
25h 0004h Max. timeout per individual block erase 2N times typical
26h 0000h Max. timeout for full chip erase 2N times typical (00h = not supported)
2Dh 0000h
2Eh 0000h Erase Block Region 1 Information
2Fh 0040h (refer to the CFI specification or CFI publication 100)
30h 0000h
31h 0001h
32h 0000h
Erase Block Region 2 Information
33h 0020h
34h 0000h
35h 0000h
36h 0000h
Erase Block Region 3 Information
37h 0080h
38h 0003h
39h 0006h
3Ah 0000h
Erase Block Region 4 Information
3Bh 0000h
3Ch 0004h
40h 0050h
41h 0052h Query-unique ASCII string “PRI”
42h 0049h
25 ns 25 ns 25 ns 25 ns 25 ns
CLK
LBA#
BAA#
Da Da +1 Da +2
Data
65 ns 18 ns 18 ns
OE#
Figure 3. Burst Mode Read with 40 MHz CLK, 65 ns tIACC, 18 ns tBACC Parameters
40 ns 40 ns 40 ns 40 ns 40 ns
CLK
LBA#
BAA#
Da Da +1 Da +2 Da +3
Data
70 ns 24 ns 24 ns 24 ns
OE#
Figure 4. Burst Mode Read with 25 MHz CLK, 70 ns tIACC, 24 ns tBACC Parameters
Reset Command The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Writing the reset command to the device resets the de-
Once in the autoselect mode, the reset command must
vice to reading array data. Address bits are don’t care
be written to return to reading array data (also applies
for this command.
to autoselect during Erase Suspend).
The reset command may be written between the se-
If DQ5 goes high during a program or erase operation,
quence cycles in an erase command sequence before
writing the reset command returns the device to read-
erasing begins. This resets the device to reading array
ing array data (also applies during Erase Suspend).
data. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete. See “AC Characteristics” for parameters, and to Figure
17 for the timing diagram.
The reset command may be written between the se-
quence cycles in a program command sequence be-
Autoselect Command Sequence
fore programming begins. This resets the device to
reading array data (also applies to programming in The autoselect command sequence allows the host
Erase Suspend mode). Once programming begins, system to access the manufacturer and devices codes,
however, the device ignores reset commands until the and determine whether or not a sector is protected.
operation is complete. Table 8 shows the address and data requirements.
Cycles
Command
Sequence First Second Third Fourth Fifth Sixth
(Note 1) Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 6) 1 RA RD
Reset (Note 7) 1 XXX F0
Manufacturer ID 4 555 AA 2AA 55 555 90 X00 01
Device ID, Bottom Boot Block 4 555 AA 2AA 55 555 90 X01 2203
Autoselect
(Note 8)
(SA) 0000
Sector Protect Verify (Note 9) 4 555 AA 2AA 55 555 90
X02 0001
0000
Burst Mode Status (Note 10) 4 555 AA 2AA 55 555 90 X03
0001
CFI Query (Note 11) 1 55 98
Program 4 555 AA 2AA 55 555 A0 PA PD
Unlock Bypass 3 555 AA 2AA 55 555 20
Unlock Bypass Program (Note 12) 2 XXX A0 PA PD
Unlock Bypass Reset (Note 13) 2 XXX 90 XXX 00
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Erase Suspend (Note 14) 1 XXX B0
Erase Resume (Note 15) 1 XXX 30
Burst Mode
Burst Mode Enable 4 555 AA 2AA 55 555 C0 XXX 01
Burst Mode Disable 4 555 AA 2AA 55 555 C0 XXX 00
Legend:
X = Don’t care PD = Data to be programmed at location PA. Data latches on the
RA = Address of the memory location to be read. rising edge of WE# or CE# pulse, whichever happens first.
RD = Data read from location RA during read operation. SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A19–A12 uniquely select any sector.
PA = Address of the memory location to be programmed.
Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.
Notes:
1. See Table 1 for description of bus operations. 10. The data is 00h if the device is in asynchronous mode and
2. All values are in hexadecimal. 01h if in synchronous (burst) mode.
3. Except for the read cycle and the fourth cycle of the 11. Command is valid when device is ready to read array data or
autoselect command sequence, all bus cycles are write when device is in autoselect mode.
cycles. 12. The Unlock Bypass command is required prior to the Unlock
4. Data bits DQ15–DQ8 are don’t cares for unlock and Bypass Program command.
command cycles. 13. The Unlock Bypass Reset command is required to return to
5. Address bits A19–A11 are don’t cares for unlock and reading array data when the device is in the unlock bypass
command cycles, unless SA or PA required. mode.
6. No unlock or command cycles required when reading array 14. The system may read and program in non-erasing sectors, or
data. enter the autoselect mode, when in the Erase Suspend
mode. The Erase Suspend command is valid only during a
7. The Reset command is required to return to reading array
sector erase operation.
data when device is in the autoselect mode, or if DQ5 goes
high (while the device is providing status data). 15. The Erase Resume command is valid only during the Erase
Suspend mode.
8. The fourth cycle of the autoselect command sequence is a
read cycle.
9. The data is 00h for an unprotected sector and 01h for a
protected sector. See “Reset Command” for more
information.
OPERATING RANGES
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C
Extended (E) Devices
Ambient Temperature (TA) . . . . . . . . –55°C to +125°C
VCC Supply Voltages
VCC for regulated voltage range. . . . . . . 3.0 V to 3.6 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
25 MHz 15 30 mA
VCC Burst Mode Read Current CE# = VIL,
ICC6 33 MHz 20 35 mA
(Notes 2, 5) OE# = VIH
40 MHz 25 40 mA
VIL Input Low Voltage –0.5 0.8 V
25
Supply Current in mA
20
15
10
0
0 500 1000 1500 2000 2500 3000 3500 4000
Time in ns
Figure 11. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
10
3.6 V
8
Supply Current in mA
2.7 V
0
1 2 3 4 5
Frequency in MHz
Note: T = 25 °C
Figure 12. Typical ICC1 vs. Frequency
Steady
Changing from H to L
Changing from L to H
3.0 V
Input 1.5 V Measurement Level 1.5 V Output
0.0 V
CE# = VIL
tAVQV tACC Address to Output Delay Max 65 70 90 120 ns
OE# = VIL
tELQV tCE Chip Enable to Output Delay OE# = VIL Max 65 70 90 120 ns
tGLQV tOE Output Enable to Output Delay Max 17 18 24 26 26 ns
Read Min 0 ns
Output Enable
tOEH Toggle and
Hold Time (Note 1) Min 10 ns
Data# Polling
Output Hold Time From Addresses, CE# or
tAXQX tOH Min 0 ns
OE#, Whichever Occurs First (Note 1)
Notes:
1. Not 100% tested.
2. See Figure 13 and Table 10 for test specifications
Note: Initial valid data will be output after second clock rising edge of LBA# assertion.
tRC
tDF
tOE
OE#
tOEH
WE# tCE
tOH
HIGH Z HIGH Z
Outputs Output Valid
RESET#
RY/BY#
0V
tCES tCEZ
CE#
CLK
tLBAS
LBA#
tLBAH tBAAS
BAA# tACS
tBAAH
A0: A18 Aa
tBDH tBACC
tACH
DQ0: DQ15
tIACC Da Da + 1 Da + 2 Da + 3 Da + 31
tOE tOEZ
OE#*
IND#
RY/BY#
CE#, OE#
tRH
RESET#
tRP
tReady
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
Program Command Sequence (last two cycles) Read Status Data (last two cycles)
tWC tAS
Addresses 555h PA PA PA
tAH
CE#
tCH
OE#
tWP tWHWH1
WE#
tWPH
tCS
tDS
tDH
tBUSY tRB
RY/BY#
VCC
tVCS
Note: PA = program address, PD = program data, DOUT is the true data at the program address.
tWC tAS
Addresses 2AAh SA VA VA
555h for chip erase
tAH
CE#
OE# tCH
tWP
WE#
tWPH tWHWH2
tCS
tDS
tDH
In
Data 55h 30h Progress Complete
tBUSY tRB
RY/BY#
tVCS
VCC
Note: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
tCH
tOE
OE#
tOEH tDF
WE#
tOH
High Z
DQ7 Complement Complement True Valid Data
High Z
DQ0–DQ6 Status Data Status Data True Valid Data
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array
data read cycle.
tRC
Addresses VA VA VA VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH tDF
WE#
tOH
High Z
DQ6/DQ2 Valid Status Valid Status Valid Status Valid Data
(first read) (second read) (stops toggling)
tBUSY
RY/BY#
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last
status read cycle, and array data read cycle.
DQ6
DQ2
Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.
tVIDR VID Rise and Fall Time (See Note) Min 500 ns
12 V
RESET#
0 or 3 V
tVIDR tVIDR
Program or Erase Command Sequence
CE#
WE#
tRSP
RY/BY#
VID
VIH
RESET#
SA, A6,
Valid* Valid* Valid*
A1, A0
Sector Protect/Unprotect Verify
CE#
WE#
OE#
Addresses PA
tWC tAS
tAH
tWH
WE#
tGHEL
OE#
tCP tWHWH1 or 2
CE#
tWS tCPH
tBUSY
tDS
tDH
DQ7# DOUT
Data
tRH A0 for program PD for program
55 for erase 30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data written to the
device.
2. Figure indicates the last two bus cycles of the command sequence.
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 3.0 V, 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See
Table 8 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1 million cycles.
LATCHUP CHARACTERISTICS
Description Min Max
Input voltage with respect to VSS on all pins except I/O pins
–1.0 V 12.5 V
(including A9, OE#, and RESET#)
Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V
Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter Test Conditions Min Unit
150°C 10 Years
Minimum Pattern Data Retention Time
125°C 20 Years
* For reference only. BSC is an ANSI standard for Basic Space Centering