Microelectronics Journal 43 (2012) 949–955

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Microelectronics Journal
journal homepage: www.elsevier.com/locate/mejo

Design of D-PHY chip for mobile display interface supporting MIPI standard
Doo-Hwan Kim, Beom-Dae Kim, Kyoungrok Cho n
Department of Information and Communication Engineering, Chungbuk National University, Cheongju 361-763, South Korea

a r t i c l e i n f o abstract

Article history: This paper presents a MIPI (Mobile Industry Processor Interface) D-PHY (physical layer) analog part that
Received 29 March 2012 meets the MIPI Alliance standard that supports high-speed (HS) transmitter (HS-TX) and receiver
Received in revised form (HS-RX) modes as well as low-power (LP)-TX, LP-RX, and LP-contention detection (CD) modes. MIPI is a
23 July 2012
flexible, source synchronous serial interface standard connecting a host processor to display and
Accepted 24 July 2012
Available online 7 September 2012
camera modules on mobile devices. The standard supports signal levels of 1.2 Vpp at 10 Mbps in LP
mode and 0.2 Vpp at 80–1000 Mbps in HS mode.
Keywords: In the design, we propose the use of special circuits: LP-TX controls the slew-rate and limits current
MIPI (Mobile Industry Processor Interface) with a push–pull driver that reduces electromagnetic interference, LP-RX maintains good noise
Small swing
immunity using a hysteresis comparator and a set/reset (SR) latch, HS-TX supports synchronous
LVDS
differential high-speed data transmission based on Scalable Low Voltage Signaling (SLVS), and HS-RX
SLVS
D-PHY stably receives transferred data with DC variations and AC noise using a very-wide-common-mode
range differential amplifier (VCDA). We implemented the MIPI D-PHY analog chip using 0:13 mm CMOS
process under a 1.2 V supply. We found that the HS-RX block shows a jitter of less than 5% at 1 Gbps
and a power consumption of 0.74 mW that is suitable for the standard.
& 2012 Elsevier Ltd. All rights reserved.

1. Introduction applications. It is an open, royalty-free standard to accelerate

Traditionally, display interfaces employ CMOS parallel busses
at low bit rates with slow edges to suppress electromagnetic
interference (EMI). The standardization of display interfaces is
seeing active progress. Most mobile devices today are multimedia
devices that function as cameras, MP3 players, Internet access
devices, Digital Multimedia Broadcasting (DMB) receivers, video
game platforms, etc., and so require higher data rates and more
data lines for the interfaces between the display driver IC and the
application processor (AP). For portable products, reductions in
the pin count and power consumption are highly required. These
requirements are shaping a new generation of interfaces for
mobile applications. There are several low-swing signaling
schemes that employ differential signaling methods such as those
that implement the differential current mode technique [1,2] and
a low-swing driver called the nLVSD driver [3].
MIPI (Mobile Industry Processor Interface) is a flexible, low-
cost, low-power, high-speed source synchronous serial interface
standard between the host processor and display peripherals,
typically found in mobile terminal systems. The MIPI solution
enables extension of the interface bandwidth for more advanced
n
Corresponding author. Tel.: þ82 43 261 2368; fax: þ 82 43 275 2616.
E-mail address: krcho@cbnu.ac.kr (K. Cho).
adoption and allows quick development of multiple interoperable
products. MIPI D-PHY is the physical layer circuit that covers all
electrical and timing aspects, as well as the lowest-level proto-
cols, signaling, and message transmissions in various operating
modes. D-PHYs communicate at approximately 500 Mbps. A
practical D-PHY configuration has a clock lane module and one
or more data lane modules. Each of these PHY lane modules
communicates via two-line point-to-point lane interconnects
with a complementary part at the other side of the lane inter-
connect. The MIPI D-PHY block is a high-speed (HS), low-power
(LP) serial transceiver that supports an HS mode for fast data
traffic and an LP mode for control signal transactions. This dual-
mode functionality requires a receiver (RX) architecture that is
different from those typically found in other HS serial technolo-
gies. The MIPI D-PHY block consists of a digital D-PHY and an
analog D-PHY that can be applied to any standard CMOS-based
fabrication process [4,5].
A MIPI D-PHY is somewhat unique in that one of its key
power-saving aspects [A4] is that the link utilizes switchable
resistive line termination at the receiver via communication of
special LP state control sequences. Switchable termination is
enabled during the HS mode and disabled to present an open
termination during the LP mode. The switching in and out of the
HS mode is typically called HS burst mode operation. Both
transmitter (TX) and RX must be shut off to conserve power
when no data is being transmitted.

0026-2692/$ - see front matter & 2012 Elsevier Ltd. All rights reserved.
http://dx.doi.org/10.1016/j.mejo.2012.07.018
950 D.-H. Kim et al. / Microelectronics Journal 43 (2012) 949–955
In this paper, Sections 2 and 3 present the MIPI standard and
the operations of the MIPI D-PHY analog blocks, respectively.
Measurement results for the chip follow in Section 4. Finally, the
conclusions are given in Section 5.
2. MIPI standards
Fig. 1 shows MIPI D-PHY universal lane module functions that
are included on a fully featured analog part. Each lane module has
a transceiver portion handling differential HS functions (HS-TX
and HS-RX), single-ended LP functions (LP-TXs and LP-RXs), and
LP contention detectors (LP-CD). Signal lines (Dp and Dn) are used
for both the HS differential signaling and the LP single-ended
signaling [4].
The HS-TX and the HS-RX transfer the differential data and
clock signals. The LP-mode is used for low-power signaling and
includes the LP-TX, LP-RX, and LP-CD. For EMI suppression, the LP
drivers control the output slew rate and limit the driving current
of the output. The LP-TX is only enabled for LP states. If the LP-RX
in the lane module is powered, it monitors the line levels. The LP-
CD function requires bi-directional operation.
The line levels in each mode of MIPI are shown in Fig. 2 and
Table 1. The HS mode supports HS data transmission in bursts
with synchronous non-return-to-zero (NRZ) signals based on
Scalable Low Voltage Signaling (SLVS) [6]; it transmits a low-
voltage-swing differential signal with a common-mode voltage of
0.2 V. A signaling pair has a bit rate from 80 Mbps to 1000 Mbps.
The LP mode is based on asynchronous LP data transmission using
a signal with large swing , e.g., 1.2 V at 10 Mbps, with low-voltage
CMOS circuits. The single-ended LP function is un-terminated and
is in pairs.
Fig. 1. MIPI D-PHY universal lane module function block.
Fig. 2. Line levels of MIPI.
Table 1
Each mode characteristics of MIPI.
HS mode LP mode
Purpose HSDT Control and LPDT
Transmission Differential Single-ended
Data rate(Mbps) 80–1000  10
Transfer tech. SLVS LVCMOS
VCM (V) 0.2 0.6
VDM (V) 0.2 1.2
CLK w/o CLK lane synchronous w/o CLK lane asynchronous
Data coding NRZ RZ
Termination Both-ends Un-termination
3. MIPI D-PHY analog block
3.1. Low-power transmitter (LP-TX)
The LP-TX controls the slew rate and limits current with a
push–pull driver for reducing dynamic power consumption, as
shown in Fig. 3. The CMOS drivers were divided into three parts
for EMI reduction during simultaneous switching of the output
and for controlling the slew rate [7]. The weighted inverters drive
different load capacitors. MPn and MNn are used to turn off the
weighted inverters quickly, while the transmission gates TGns are
used as resistive elements to turn each weighted inverter on
separately. The drivers are operated sequentially in the order
MPD3, MPD2, and MPD1.
Table 2 shows the simulation results for the LP-TX. TRLP and
TFLP are rise and fall times at 15–85% of the output, respectively,
when the LP-TX is driving a capacitive load CLOAD.
3.2. Low-power receiver (LP-RX)
The LP-RX is an un-terminated, single-ended RX circuit that is
used to detect the LP status on each data pin (Dp or Dn). The input
levels VIH (Min) and VIL (Max) of the LP mode should be
guaranteed for all devices among the different CMOS technolo-
gies. For high robustness, the LP-RX should filter out noise pulses
and RF interference. The LP low-level input threshold (VIL) is
greater than the maximum single-ended line voltage during HS
signaling. Therefore, the LP-RX always detects low levels on HS
signals.
The conventional LP-RX uses a Schmitt trigger circuit wherein
threshold voltages (VIH, VIL) of hysteresis exhibit process varia-
tions since both VIH and VIL are decided by threshold voltages and
the sizing ratio of metal–oxide–semiconductor field-effect tran-
sistors (MOSFETs). Fig. 4 shows the proposed accurate LP-RX,
which consists of two hysteresis comparators, an inverter, and a
set/reset (SR) latch that separates the input high- and low-level
voltages VIH and VIL, respectively.
In the design, the LP-RX acts successfully as an input signal
filter and meet all the specifications for interference and noise
with a peak amplitude VINT ( ¼Max 200 mV) and frequency
fINT( ¼Min 450 MHz). Table 3 shows the LP-RX operation. The
comparator outputs (va1 and va2) have only three states – 00, 01,
and 11 – because Vref1 is always higher than Vref2. Note that the
comparator output 01 means that the input is between Vref1 and
Vref2. The output is not changed from the previous LP-RX output
because of the hysteresis characteristic in the specification. The
SR latch keeps the output equal to the next input.
The reference voltages and hysteresis of the LP-RX are shown
in Fig. 5. The LP-RX output (Vo) is high when the input (Vi) is
higher than VIH (¼ Vref2), but (Vo) is low when (Vi) is lower than VIL
(¼ Vref1).
 D.-H. Kim et al. / Microelectronics Journal 43 (2012) 949–955 951

Fig. 3. LP-TX circuits.

Table 2 3.3. Line contention detection (LP-CD)

LP-TX specifications with simulation results.
The LP-RX is used in a bidirectional data lane to monitor the
LP-TX AC specifications CLOAD
line voltage on each LP signal. This is required to detect line
0 pF 5 pF 20 pF 70 pF contention situations. The LP-CD adjusts the switch to avoid data
conflict and has additional blocks: input MUX, output MUX,
SRð@V=@tÞ (nV/ns) enable delay block, and a power switch block as shown in Fig. 6.
Min 32 32 32 32
Max 500 200 100 100
The normal operation of the LP-CD is similar to that of an LP-
RX with lower threshold voltages (VIH and VIL). The AC specifica-
TRLP/TFLP (ns)
tions are also defined to match those of the LP-RX. Moreover,
Min 1.6 4 8 8
Max 25 25 25 25 it filters the input signal to avoid false triggering on short events.
Simulation results (ns)
Min 32 32 32 32
3.4. High-speed transmitter (HS-TX)
Max 500 200 100 100
The HS-TX is based on HS SLVS [6], which is a chip-to-chip
signaling protocol that uses differential voltage-mode signaling,
as shown in Fig. 7. The voltage-mode TX reduces the HS-TX power
consumption by 50% compared with a commonly used
impedance-matched current-mode TX.
In the designed circuit, mismatch of line impedance is not
extremely critical even at HS because the SLVS supports near-end
and far-end termination, in contrast to other systems that have
only far-end termination.
The HS-TX comprises an input MUX, a differential signal
generator, and a 0.4 V differential n-channel MOS (NMOS) H-
bridge driver. The H-bridge is controlled using a differential signal
generator, which is a booster buffer that drives the large gate
Fig. 4. LP-RX circuits. capacitance of the H-bridge transistors. The H-bridge is composed
only of NMOS transistors and does not have a passive resistor that
allows better impedance matching. The circuit requires an addi-
tional, nominal 0.4 V supply because the driver impedance must
Table 3
be matched to the line and termination impedances. The HS-TX
Principle of proposed LP-RX operation.
transmits a 0.4 V differential voltage with a nominal single-line
va1 va2 Meaning point Output swing (0.14–0.27 V) and a common mode voltage (0.15–0.25 V).
The differential signaling shows 15% higher noise immunity than
1 0 Forbidden X single-ended signaling [12]. This allows LP mode operation and
1 1 Input4 V IH:Max ð ¼ V ref 1 Þ 1
high noise immunity for mobile environments [8]. The proposed
0 0 Inputo V IL:Max ð ¼ V ref 2 Þ 0
0 1 V IL:Max ð ¼ V ref 2 Þ o input o V IH:Max ð ¼ V ref 1 Þ Not change HS-TX supports data communications over up to 50 cm long strip
lines on printed wiring boards (PWB) with a 0.2 V signal swing.
952 D.-H. Kim et al. / Microelectronics Journal 43 (2012) 949–955

Fig. 5. Reference voltages and simulation result of LP-RX hysteresis characteristic.

Fig. 6. LP-CD circuits.

Fig. 7. HS-TX circuits.

Additional options using pre-emphasis, DC-balanced data, and
equalization would extend the interconnection length substan-
tially [9]. The HS-TX sends data at a high frequency with
common-mode voltage variations that do not exceed 15 mVRMS
and 25 mVPEAK at 50–450 MHz.
The power consumption of the HS-TX is directly proportional
to the 0.4 V supply and is speed independent because of the
constant current ( ¼2 mA) in SLVS [10]. Further, the NMOS
transistors in the H-bridge reduce capacitive loading, making
power consumption independent of data rate. The minimum
power to drive the 0.4 V differential swing into a connecting
cable is 2 mA  0.4 V¼0.8 mW with 100 O termination at the HS-
RX. Depending on the implementation techniques, the differential
signal generator and the 0.4-V supply voltage circuit also con-
sume a small amount of additional power. However, the power
consumption goes to zero when the HS-TX is disabled in the LP
mode. Fig. 8 shows simulation results for the HS-TX at 2 Gbps.
Transient analysis results for the HS-TX are shown in Fig. 8(a).
 D.-H. Kim et al. / Microelectronics Journal 43 (2012) 949–955 953

Dp and Dn are the HS-TX outputs with a single-line swing of 0.2 V

and a common-mode voltage of 0.2 V for a 1 GHz input pulse
vi_ht. Fig. 8(b) shows an eye pattern for the HS-TX outputs when
given a 210  1 pseudo random bit sequence (PRBS). The jitter is
0.05 ns at 2 Gbps.

3.5. High-speed receiver (HS-RX)

In this study, we designed an HS-RX with a multistage

configuration. It is a differential line RX similar to a conventional
HS serial interface RX. The proposed HS-RX consists of a termina-
tion resistor (ZID), CMOS differential amplifiers (a very-wide-
common-mode range differential amplifier (VCDA) and an opera-
tional transconductance amplifier (OTA)), and a buffer stage, as
shown in Fig. 9. The detail circuit at the transistor level is shown
in Fig. 10. The HS-RX receives HS data correctly while rejecting
common-mode DC variations V CMRXðDCÞ ( ¼70–330 mV) and AC
interference DV CMRXðHFÞ (¼ Max 100 mV beyond 450 MHz), and
DV CMRX ðLFÞð ¼ 50250 mV at 502450 MHzÞ. The power switch
block controls input data of the output MUX when the HS-RX is
enabled.
In Fig. 10, the first-stage VCDA suppresses fluctuations in VCMRX
and VOD. The circuit of the VCDA differs from that of an ordinary
Fig. 8. Simulation results of HS-TX at 2 Gbps (a) transient analysis and (b) eye
CMOS differential amplifier with fully complementary configura-
pattern. tions and is entirely self-biased through negative feedback. The
VCDA has a wide dynamic range as a result of its large drain–
source voltage drop for fully complementary input pairs. This
voltage drop keeps the input pairs in the active region even for a
large swing in the input signal. By connecting all of the bias inputs
to a single internal node, VBIAS, we can stabilize the operating point
of the VCDA through the negative feedback [8]. The second stage is
a single-ended OTA that amplifies the output of the VCDA. A class
AB output buffer with a current mirror is sufficient to maintain a
50% duty cycle. The third stage is an inverter buffer chain that
drives a large capacitor load. The termination resistor in the
termination block consists of two resistors (ZIDa and ZIDb) with
capacitive coupling to ground at the center. ZID is disabled when
Fig. 9. Multistage configuration of HS-RX. the module is not in the HS-RX mode.

Fig. 10. HS-RX circuits.

954 D.-H. Kim et al. / Microelectronics Journal 43 (2012) 949–955
Fig. 11. Simulated eye pattern of the HS-RX output when 210  1 PRBS input with
1 Gbps data rate in the worst condition.
Fig. 11 shows simulated eye patterns of the HS-RX outputs for
a 210  1 PRBS input at a 1 Gbps data rate. The circuit was
simulated under the worst conditions: low temperature
( ¼  501), SS model ( ¼PMOS: slow, NMOS: slow), and the max-
imum common mode DC and AC noises (¼ VCMRX (DC) and VCMRX
(HF), respectively) in the specification. The improvements in
signal integrity at each stage can be easily noticed from the eye
patterns. The output jitter is 0.1 ns at 1 Gbps, which corresponds
to 5% jitter.
4. Measurements of MIPI D-PHY chip
The MIPI D-PHY chip was fabricated using a commercial
0:13 mm n-well CMOS process supported by IDEC [11]. Fig. 12
shows a microphotograph of the MIPI D-PHY chip. The active chip
area of the analog part is 260  260 mm2 . The capacitors were
implemented utilizing the metal–insulator–metal (MIM)
structure.
Fig. 13 shows the measured waveforms of the MIPI D-PHY chip
in HS mode with a 100 Mbps input at a supply voltage of 1.2 V.
The waveforms on the left are the HS-TX outputs, V op_ht and
V om_ht , and their corresponding voltage difference. The HS-RX
successfully recovers the original HS-TX input data, as shown in
the waveforms on the right. The measured HS-RX output has a
delay of 10 ns, which is the sum of the T-line delay and the HS-RX
propagation delay.
Fig. 12. Microphotograph of MIPI D-PHY chip.
HS-TX differential outputs
HS-RX output
0.2V
difference of HS-TX outputs
0.2V
HS-TX input
1V HS-TX input
50n/div
Fig. 13. Measured waveform of MIPI D-PHY chip HS-mode operation at 100 Mbps.
Fig. 14 shows the measured eye patterns of the MIPI D-PHY
chip with 210 1 PRBS input data. The eye patterns of the LP-TX
output and LP-RX output at 10 Mbps are shown in Fig. 14(a) and
(b), respectively. Fig. 14(c) shows the eye patterns of the HS-TX
differential output (VDp–VDn) at 200 Mbps. The eye opening and
width of the HS-TX are 0.3 V and 3.5 ns, respectively.
Fig. 14(d) shows the eye patterns of the HS-RX output at
100 Mbps and a jitter of 3.5 ns.
5. Conclusions
This paper presented a MIPI D-PHY analog part that meets the
MIPI standard and supports HS and LP modes. The designed D-
PHY analog part consists of HS-mode blocks (HS-TX and HS-RX)
and LP-mode blocks (LP-TX, LP-RX, and LP-CD). The LP signals
have a 1.2 V swing within 10 Mbps, while the HS signals have a
0.2 V swing at 80–1000 Mbps. The LP-TX controls the slew rate of
the output and uses a current-limited push–pull driver to sup-
press EMI. The weighted inverters, shown in Fig. 3, drive a
 D.-H. Kim et al. / Microelectronics Journal 43 (2012) 949–955 955

Table 4
Specification of MIPI D-PHY chip.

Block Characteristics Measurement

LP-TX tpd: 2–24 ns @ 0–70 pF CLOAD 10 Mbps operation

Pdiss: 0.18 mW @ 10 Mbps, 20 pF
LP-RX tpd: 5 ns
Pdiss: 0.46 mW @ 10 Mbps
HS-TX tpd: 0.2 ns, Max 4 Gbps Up to 400 Mbps
Pdiss: 0.52 mW @ 1 Gbps with CLK pattern
HS-RX tpd: 1 ns, Max 1 Gbps Up to 500 Mbps
Pdiss: 0.74 mW @ 1 Gbps with CLK pattern
Under 5% jitter(0.1 ns @ 1 Gbps)

implemented the MIPI D-PHY analog chip using a 0:13 mm CMOS

process under a 1.2 V supply. For this device, the HS-RX block
showed less than 5% jitter at 1 Gbps and 0.74 mW power
consumption. Table 4 summarizes the measurement results of
the MIPI D-PHY chip.

Acknowledgments

This work was supported by Industrial Strategic Technology

Development Program funded by the Ministry of Knowledge
Economy (MKE, Korea) (10039173, Design of Core SoCs for
Multimedia Mobiles).

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capacitor load of 0–70 pF while keeping the slew rate ð@v=@tÞ at

less than 100 nV/nS. A simple noise immunity circuit comprising
a hysteresis comparator and an SR latch is proposed for the LP-RX.
The HS-TX supports synchronous differential HS data transmis-
sion based on SLVS. The HS-RX stably receives transferred
data despite DC variations and AC noise through a VCDA. We
Further reading
[1] M. Bazes, Two novel fully complementary self-biased CMOS differential
amplifiers, IEEE J. Solid State Circ. 26 (February (2)) (1991) 165–168.