Computer Architecture

Fall, 2022
Week 12
2022.11.28

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[group4]
Which of the following statements is (are) true for the forwarding unit used in a
five-stage pipelined processor?
a. The forwarding unit is used to bypass the write-back result due to RAW hazards.
b. The forwarding unit is used to forward data to the register file.
c. The forwarding unit compares the source register number of the instructions in
the MEM and WB stages with the destination register number of the instruction
in EX stage.
d. The forwarding unit can be used to resolve load-use data hazard directly.

Ans: a
b. forward data to ALU
c. compare destination register of MEM and WB with source register in EX
stage
d. load-use data hazard can be solved by stall, not forwarding unit
[group6]
True or False

a. In MIPs 5-stage pipeline, R-Type-use data hazard can be handled by

Forwarding technique.
b. In MIPs 5-stage pipeline, forwarding technique is not enough to handle
load-use data hazard since it takes longer time to read memory than register.
c. The main reason why inserting NOP is not preferred is that software runs
slower than hardware.
d. Using Forwarding technique, we always need to forward data if
EX/MEM.RegisterRD == ID/EX.RegisterRS.
e. There is a register which will be written by instruction 1 and then read by
instruction 2. Without forwarding, 3 stalls or NOPs will be inserted in
instruction 2 to avoid hazard and to make sure that the ins2. will read the right
data from the pipeline register.
f. The main difference between inserting NOP and Stalls is that the
previous one is controlled by the compiler and the latter one is controlled by
hardware.

Ans: TFFFFT
b): since memory-read ends after the next instruction using ALU.
c): only inserting NOP will waste many cycle times.
d): not necessary if EX/MEM.RegisterRD == $0.
e): 2 stalls or NOPS will be used.
[group9]
In MIPS pipeline, which of the following program segments will require a NOP
bubble (require stalling)? Please explain why or why not?
Hint:
If (ID/EX.MemRead and ((ID/EX.RegisterRt = IF/ID.RegisterRs) and
ID/EX.RegisterRt != $0 or (ID/EX.RegisterRt = IF/ID.RegisterRt))): stall the
pipeline

(A)
lw $1, 60($2)
add $2, $1, $3
and $1, $2, $3
(B)
add $1, $2, $3
add $1, $1, $2
add $1, $1, $3
(C)
lw $2, 60($1)
add $2, $1, $3
and $1, $2, $3
(D)
lw $0, 60($2)
add $1, $0, $2
sub $2, $0, $1

Ans: (A)
Explanation:
(A)
lw $1, 60($2)
add $2, $1, $3
and $1, $2, $3
(B)No lw
(C)Didn’t meet the condition
(D)$0 is always zero, cannot be modify
[group10]
Consider the following MIPS code. Please find ALL the hazards in there and
rearrange it to make it right.
lw $t1, 4($t0)
add $t3, $t1, $t2
sub $t6, $t7, $t8
lw $t4, 8($t0)
add $t5, $t1, $t4
and $t8, $t6, $t6

Ans:
For better understanding, we indexed the two lw instructions and the two add
instructions.

cycle 1 2 3 4 5 6 7 8 9 10

lw1 IF ID EX MEM WB

add1 IF ID EX MEM WB

sub IF ID EX MEM WB

lw2 IF ID EX MEM WB

add2 IF ID EX MEM WB

and IF ID EX MEM WB

Both of the two add instructions have hazard. “add1” will take the old $t1 value at
cycle4 (lw1 haven’t WB yet), and “add2” will take the old $t4 value at cycle7. (lw2
haven’t WB yet)
The rearranged MIPS code should look something like this.
lw $t1, 4($t0)
lw $t4, 8($t0)
sub $t6, $t7, $t8
add $t3, $t1, $t2
add $t5, $t1, $t4
and $t8, $t6, $t6
 cycle 1 2 3 4 5 6 7 8 9 10

lw1 IF ID EX MEM WB

lw2 IF ID EX MEM WB

sub IF ID EX MEM WB

add1 IF ID EX MEM WB

add2 IF ID EX MEM WB

and IF ID EX MEM WB

[group2]
Fred set a list of MIPS instructions.

(1) add $s0, $s1, $s2

(2) and $s3, $s0, $s1
(3) lw $s4, 12($s3)
(4) addi $s5, $s4, 2

Please help him answer the following question:

(a) List all the data dependencies between the above instructions.
(Ex: (1)、(2) -> $s0)
(b) What kind of hazard may occur in the list of instructions?
(c) Please insert NOP between instructions to solve the hazard.
(Assume the hardware Fred is using has no forwarding design, but it
has internal forwarding in the register file.)
Ans：
(a)
(1)、(2) -> $s0
(2)、(3) -> $s3
(3)、(4) -> $s4

(b)
data hazard

(c)
add $s0, $s1, $s2
NOP
NOP
and $s3, $s0, $s1
NOP
NOP
lw $s4, 12($s3)
NOP
NOP
addi $s5, $s4, 2
[group1]
Please select the correct options and explain the incorrect ones.
a. We can always resolve hazards by waiting.
b. The hazard, which tries to make a decision before evaluating a
condition, occurs most often in branch instructions.
c. In MIPS, if there is data dependency, there must be a data
hazard.
d. By using more than one memory we can solve the data hazard.
e. The forwarding logic requires extra units to achieve.

Ans. a, b, e
Explanation:
c. It must be RAW data dependency and instruction distance should
be <=2.
d. Not data hazard, it solves structural hazard.

[group5]
Which of the following statements are correct?
(A) We don’t care “write after read” and “write after read” hazards in
MIPS.
(B) At the MEM stage, if EX/MEM.RegRd = ID/EX.RegRs, it always
forwards.
(C) If both WB and MEM can forward , we let MEM forward.
(D) We don’t have to forward if the destination register is $0.
(E) When stalling, PC still updates.
(F) the insertions of Nops can speed up the pipeline

Ans : (A),(C),(D)
(B)Still need to check if Regwrite is asserted
(E)PC can’t be replaced when stalling.
(F)slow down