Introduction to Fabrication of Electronic Components/Devices:

Semiconductor Wafer:

In electronics, a wafer (also called a slice or substrate) is a thin slice of semiconductor, such as:
crystalline silicon (c-Si), used for the fabrication of integrated circuits and, in photovoltaics, to
manufacture solar cells.

The semiconductor or silicon wafer industry, the term wafer appeared in the 1950s to describe a thin
round slice of semiconductor material, typically germanium or silicon. The round shape
characteristic of these wafers comes from single-crystal ingots usually produced using
the Czochralski method. Silicon wafers were first introduced in the 1940s.

An integrated circuit is a small but sophisticated device implementing several electronic functions. It
is made up of two major parts: a tiny and very fragile silicon chip (die) and a package which is
intended to protect the internal silicon chip and to provide users with a practical way of handling the
component. This note describes the various “front-end” and “back-end” manufacturing processes
and takes the transistor as an example, because it uses the MOS technology. This technology is used
for most of the ICs manufactured at STMicroelectronics. There are five steps of wafer forming

1. Slicing

The circumference of the monocrystalline ingot is ground down to a uniform diameter. Based on the
resistivity desired by the customer, the ingot is then cut into slices of around 1mm thickness, using
an inner-diameter saw or wire saw, to form the wafers.

2. Lapping

The sliced wafers are polished by alumina abrasive in a lapping machine to the desired thickness,
while improving the surface parallelism.
3. Etching

Mechanical damage to the wafer surface resulting from the earlier steps is removed by chemical
etching.

Polishing

The wafer surfaces are made perfectly flat and given a mirror finish by means of mechano-chemical
polishing using colloidal silica.

5. Cleaning and inspection

After cleaning, stringent inspections are performed, and the SUMCO polished wafer is completed.
The exceptionally high quality of the polished wafers manufactured by SUMCO ensures they are
favoured by customers all over the world.
The Fabrication Of A Semiconductor Device

The manufacturing phase of an integrated circuit can be divided into two steps. The first, wafer
fabrication, is the extremely sophisticated and intricate process of manufacturing the silicon chip.
The second, assembly, is the highly precise and automated process of packaging the die. Those two
phases are commonly known as “Front-End” and “Back-End”. They include two test steps: wafer
probing and final test. The main steps for the fabrication of a die are summarized in the following
table. Some of them are repeated several times at different stages of the process. The order given
here does not reflect the real order of fabrication process.

Wafer properties

Standard wafer sizesSilicon

Silicon wafers are available in a variety of diameters from 25.4 mm (1 inch) to 300 mm
(11.8 inches). Semiconductor fabrication plants, colloquially known as fabs, are defined by the
diameter of wafers that they are tooled to produce. The diameter has gradually increased to improve
throughput and reduce cost with the current state-of-the-art fab using 300 mm, with a proposal to
adopt 450 mm.[15][16] Intel, TSMC, and Samsung were separately conducting research to the advent
of 450 mm "prototype" (research) fabs, though serious hurdles remain.
Wafers grown using materials other than silicon will have different thicknesses than a silicon
wafer of the same diameter. Wafer thickness is determined by the mechanical strength of the
material used; the wafer must be thick enough to support its own weight without cracking during
handling. The tabulated thicknesses relate to when that process was introduced, and are not
necessarily correct currently, for example the IBM BiCMOS7WL process is on 8-inch wafers, but
these are only 200 μm thick. The weight of the wafer goes up along with its thickness and diameter.

Photo-Masking: This step shapes the different components. The principle is quite simple (see
drawing on next page). Resin is put down on the wafer which is then exposed to light through a
specific mask. The lighten part of the resin softens and is rinsed off with solvents (developing step).

Etching: This operation removes a thin film material. There are two different methods: wet (using a
liquid or soluble compound) or dry (using a gaseous compound like oxygen or chlorine).

Diffusion: This step is used to introduce dopants inside the material or to grow a thin oxide layer
onto the wafer. Wafers are inserted into a high temperature furnace (up to 1200° C) and doping
gazes penetrate the silicon or react with it to grow a silicon oxide layer.

Ionic Implantation: It allows to introduce a dopant at a given depth into the material using a high
energy electron beam.

Metal Deposition: It allows the realization of electrical connections between the different cells of
the integrated circuit and the outside. Two different methods are used to deposit the metal:
evaporation or sputtering.

Passivation:Wafers are sealed with a passivation layer to prevent the device from contamination or
moisture attack. This layer is usually made of silicon nitride or a silicon oxide composite.

Back-lap: It’s the last step of wafer fabrication. Wafer thickness is reduced (for microcontroller
chips, thickness is reduced from 650 to 380 microns), and sometimes a thin gold layer is deposited
on the back of the wafer.

Historical increases of wafer size

A unit of waferfabrication step, such as an etch step, can produce more chips proportional to the
increase in wafer area, while the cost of the unit fabrication step goes up more slowly than the wafer
area. This was the cost basis for increasing wafer size. Conversion to 300 mm wafers from 200 mm
wafers began in early 2000, and reduced the price per die for about 30–40%. Larger diameter wafers
allow for more die per wafer.

In order to minimize the cost per die, manufacturers wish to maximize the number of dies that can be
made from a single wafer; dies always have a square or rectangular shape due to the constraint
of wafer dicing. In general, this is a computationally complex problem with no analytical solution,
dependent on both the area of the dies as well as their aspect ratio (square or rectangular) and other
considerations such as the width of the scribe line or saw lane, and additional space occupied by
alignment and test structures. Note that gross DPW formulas account only for wafer area that is lost
because it cannot be used to make physically complete dies; gross DPW calculations do not account
for yield loss due to defects or parametric issues.

Wafer map showing fully patterned dies, and partially patterned dies which do not fully lie within
the wafer. Nevertheless, the number of gross die per wafer (DPW) can be estimated starting with
the first-orderapproximation or floorfunction of wafer-to-die area ratio, Where,

DPW = A=π r 2 / S

 d is the wafer diameter (typically in mm)

 S the size of each die (mm2) including the width of the scribe line (or in the case of a saw
lane, the kerf plus a tolerance).

This formula simply states that the number of dies which can fit on the wafer cannotexceed the area
of the wafer divided by the area of each individual die. It will always overestimate the true best-case
gross DPW, since it includes the area of partially patterned dies which do not fully lie on the wafer
surface (see figure). These partially patterned dies don't represent complete ICs, so they cannot be
sold as functional parts.