ECE319 – CMOS VLSI DESIGN LABARATORY

HARISH NAYAK - 12112873

ROLL NO: REM216B35

DEPARTMENT: VLSI DESIGN

harishnayak1080@gmail.com
Experiment 1:
Design and implementation of CMOS inverter

ABSTRACT

This study presents the design and implementation of a 3-bit full adder circuit using 1-bit full
adders designed on a 45nm technology node in Cadence. The full adder is a fundamental
building block in digital circuits, and optimizing its performance is crucial for various
applications in modern computing systems. The 45nm technology node represents an advanced
semiconductor manufacturing process that offers improved performance and power efficiency.

The research consists of the following components:

Designing a 1 Bit Full Adder: Using the Cadence platform and the 45nm technology node we
develop a 1 bit adder. Our design aims to achieve power consumption, high speed operation
and a compact footprint. We explore transistor’ sizes and logical configurations to optimize its
performance.

Implementing a 3 Bit Full Adder: We utilize the designed 1 bit adder, as a foundational building
block to create a seamless integration of three bits into a complete adder circuit.

Analysis: We conduct evaluations of the designed 3 bit adders performance through various
analyses including transient, DC, delay and power analysis. Transient analysis helps us
understand how the circuit behaves with inputs while DC analysis provides insights into its
characteristics. Delay analysis focuses on determining propagation delay, which's crucial for
high speed computing applications. Power analysis quantifies energy consumption for systems.

The obtained results from these analyses play a role in assessing the efficiency and reliability of
the 3 bit adder circuit, in real world applications.

This study makes a contribution, to the progress of circuit design particularly in the field of
energy efficient and high performance computing. It also sets the groundwork for investigations
and improvements, in circuits using advanced semiconductor technologies.
INTRODUCTION
Designing and implementing effective arithmetic components, such complete adders, is crucial
in the constantly evolving field of digital integrated circuits. Full adders serve as the essential
building blocks for a wide range of digital applications, including microprocessors and arithmetic
units. This project focuses on designing and implementing a 3-bit full adder employing 1-bit full
adders, all of which were painstakingly created using Cadence's cutting-edge 45nm technology
node.

Design of 1-Bit Full Adder: We will start by designing a high-performance 1-bit full adder
using complementary metal-oxide-semiconductor (CMOS) technology. The design will be
optimized for speed, area, and power efficiency.

A combinational circuit known as a full adder adds two bits plus a carry and outputs a sum bit
and a carry bit as a result. The LSBs can be added using a half adder when two binary values
with two or more bits each need to be added. The carry that occurred from the addition of the
LSBs is added to the two bits in the subsequent significant column. The two data bits of that
column and the carry bit produced by the addition in the preceding column must thus be added
in the second and higher columns.

The sum bit (S) and the carry bit, known as the carry out (Cout), are produced by the full adder
after adding the bits A and B and the carry from the preceding column. The value of the sum's
least significant bit is provided by the variable S. The outout carry is provided by the variable
Cout.

Logic circuit of 1bit full adder:

The following above Logic diagram shows how 1bit Full Adder is implemented using AND,OR
and XOR gates.

Truth table of 1bit full adder:

The above truth table shows all possible combination of 1's and 0's that these variable may
have. The 1's and 0's for output variables are determined from the arithmetic sum of the input
bits. When all input bits are 0, the output is 0. The S output is equal to one when only one input
is equal to 1 or three inputs are equal to 1. The c output has carry of 1 if two or three inputs are
equal to 1.
1bit full adder transistor level:

Transient waveform:
Symbol for 1bit full adder:

Cascading 1-Bit Full Adders: Three instances of the 1-bit full adder will be cascaded to form
the 3-bit full adder. Careful attention will be paid to interconnections and signal integrity.

3 bit full adder:

A 3-bit full adder is constructed using three 1-bit full adders and additional logic to handle the
carry propagation between stages. It allows you to add three 3-bit binary numbers by chaining
them together. The carry-out from one stage serves as the carry-in (Cin) for the next stage.

In a 3-bit full adder, you would have three sets of A, B, and Cin inputs (A1, B1, Cin1; A2, B2,
Cin2; A3, B3, Cin3) and obtain three sets of sum outputs (S1, S2, S3) and carry-out outputs
(Cout1, Cout2, Cout3).

The carry-out from the first stage (Cout1) becomes the carry-in (Cin2) for the second stage, and
so on. This cascading of carry-out and carry-in allows you to perform addition on three 3-bit
binary numbers.
TOOLS DESCRIPTION:

Cadence Virtuoso is an electronic design automation (EDA) tool widely used for the
design and verification of integrated circuits (ICs). Developed by Cadence Design
Systems and widely used by chip designers and engineers in the semiconductor
industry. Virtuoso is a suite of tools that provide a complete custom IC design flow,
from schematic capture to physical layout and verification. This tool offers a wide
range of functions and possibilities for the design, simulation and analysis of analog
and mixed-signal circuits. Virtuoso's main features are:

1. Schematic editor: It allows users to create and edit schematics through a graphical
user interface.

2. Layout Editor: This allows the user to create and edit the physical layout of her IC
design.

3. Circuit simulator: It allows users to simulate and analyze the behavior of analog
and mixed-signal circuits.
4. Design Rule Checker (DRC): Validate IC designs against manufacturing rules and
constraints.

5. Layout Versus Schematic (LVS) Checker: Verify that the layout matches the
schematic.

6. Design for Manufacturing (DFM) Checker: Identify potential manufacturing issues

in IC designs.
7. Analog Design Environment (ADE): It provides a powerful platform for creating
and testing analog and mixed-signal designs.

8. 45nm Technology Node: We will utilize the Cadence design environment to create
the circuit layout and simulate it in a 45nm technology node, which represents a state-of-
the-art fabrication process.
RESULT AND DISCUSSION:

Schematic of 3bit full adder using 1bit full adder:

Transient Analysis:
This analysis will provide insights into the circuit's dynamic behaviour. we will evaluate the
response of the 3-bit full adder to input changes over time.
DC Characteristics:
DC analysis will examine the steady-state behaviour of the circuit, including voltage levels,
current flow, and logic levels.

Delay Analysis:
We will measure the propagation delay of the 3-bit full adder to assess its speed performance.
Power Analysis: power consumption is a critical consideration in modern IC design. We will
evaluate both static and dynamic power dissipation.
CONCLUSION

In conclusion, the design and implementation of a 3-bit full adder using 1-bit full adders
designed on the 45nm technology node in Cadence has been successfully carried out. This
project involved several key steps, including the design and layout of the 1-bit full adder, the
integration of these 1-bit adders to create a 3-bit full adder, and subsequent analysis for
transient response, DC characteristics, delay, and power consumption.
The transient analysis showed that the 3-bit full adder operates as expected, providing accurate
sum and carry-out results when subjected to varying input conditions over time. This indicates
the functionality and correctness of the design.
In terms of DC analysis, the design met the voltage and current requirements of the 45nm
technology node, ensuring that it operates within the specified voltage and power supply
parameters.
Delay analysis revealed the propagation delay of the 3-bit full adder, which is a crucial
parameter for determining the speed of the circuit. The delay was found to be within an
acceptable range for most applications, meeting the desired performance criteria.
Power analysis is a critical aspect of modern integrated circuit design, and this project evaluated
the power consumption of the 3-bit full adder. It is important to note that power consumption
can be optimized further through techniques like power gating and voltage scaling, depending
on specific application requirements.
In summary, the design and implementation of the 3-bit full adder using 1-bit full adders on the
45nm technology node in Cadence have been successful. The circuit performs accurately under
transient conditions, meets DC requirements, exhibits acceptable delay characteristics, and
provides a foundation for further power optimization. This project demonstrates the successful
application of semiconductor technology to create an essential building block for digital circuits.