UNIT 7: RAMP CONVERTERS

SENSORS IN INTEGRATED TECHNOLOGIES

Mario Palmero Delgado

MICROELECTRONICS: DESIGN AND APPLICATIONS OF MICRO/NANOMETRIC SYSTEMS.
 Unit 7: Ramp Converters
Sensors in Integrated Technologies

Index
1. The Ramp Converter ............................................................................................................. 2
1.1. Summarize the system operation. ................................................................................ 2
1.2. What is the input voltage range that the ADC can convert? ........................................ 3
1.3. Plot in detail the transient signal 𝑽𝑫𝑨𝑪 for several ADC outputs ............................... 3
1.4. What is the target of the source follower? ................................................................... 4
1.5. When are the signals 𝑬𝑶𝑪 < 𝒊 > activated? ............................................................... 4
1.6. Complete the timeline by adding control signals.......................................................... 4
1.7. What are the design trade-offs involving the resistor implementation? ..................... 5
1.8. When the ramp transitions between 𝑽𝒕𝒐𝒑 and 𝑽𝒔𝒕𝒂𝒏𝒅𝒃𝒚 the ADC is not
converting, why? ....................................................................................................................... 5
1.9. Propose circuit modifications to implement a double ramp converter........................ 5

Figure Index
FIGURE 1: BLOCK DIAGRAM OF THE RAMP CONVERTER.............................................................................................. 2
FIGURE 2: SIMULATION OF THE 𝑉𝐷𝐴𝐶 EVOLUTION ................................................................................................. 3
FIGURE 3: DETAIL OF THE 𝑉𝐷𝐴𝐶 EVOLUTION ......................................................................................................... 4
FIGURE 4: COMPLETE TIMELINE OF CONTROL SIGNALS............................................................................................... 4

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 MICROELECTRONICS: DESIGN AND APPLICATIONS OF MICRO/NANOMETRIC SYSTEMS.

1. The Ramp Converter

In Figure 1, you can find a particular implementation of an 8-bit ramp converter. The ramp is
generated with a DAC implemented with a resistive ladder and some control logic. The
converter is intended to digitize simultaneously 128 analog inputs. This kind of implementation
is suitable for reading out the outputs of sensor arrays with multiple outputs. Particularly, this
converter architecture was implemented in an image sensor.

Figure 1: Block diagram of the ramp converter.

1.1. Summarize the system operation.

The 8-bit ramp converter is a type of analog-to-digital converter (ADC) that can be used to
simultaneously digitize multiple analog inputs. This type of converter is commonly used in
sensor arrays, such as image sensors, where there are multiple outputs that need to be
converted to digital values.

The 8-bit ramp converter uses a DAC (digital-to-analog converter) implemented with a resistive
ladder and some control logic to generate a voltage ramp that increases linearly with time. The
resistive ladder is a network of resistors arranged in a ladder-like configuration. Each resistor is
connected to a digital switch, which can be turned on or off by the control logic.

The control logic generates a clock signal that controls the operation of the converter. The
clock signal triggers the ramp generator, which starts producing a voltage ramp that starts at 0
volts and increases linearly with time.

The analog input voltages are connected to the inputs of the resistive ladder. As the ramp
voltage increases, it is compared to the input voltage for each analog input. When the ramp
voltage exceeds the input voltage for a given analog input, a comparator detects this and
triggers a latch.

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 Unit 7: Ramp Converters
Sensors in Integrated Technologies
The latched value is then stored in a register, which holds the digital output value
corresponding to that analog input voltage. The clock signal continues to trigger the ramp
generator, causing the ramp voltage to increase further. The process repeats for each analog
input voltage until all 128 inputs have been digitized.

At the end of the conversion process, the digital output values are available for further
processing, such as storing in memory or transmitting to a computer.

Overall, the 8-bit ramp converter with a resistive ladder and control logic is a method for
simultaneously digitizing multiple analog input signals. By using a ladder of resistors and a
ramp generator, this converter architecture is able to convert multiple analog signals
simultaneously, producing digital outputs that can be processed further.

1.2. What is the input voltage range that the ADC can convert?
The input voltage that this ADC can convert will be defined by the range of the ramp
generator, which is [𝑉𝑏𝑜𝑡 , 𝑉𝑡𝑜𝑝 ]

1.3. Plot in detail the transient signal 𝑽𝑫𝑨𝑪 for several ADC outputs
Making a SIMULINK file that allows us to represent the behavior of the 𝑉𝐷𝐴𝐶 we obtain:

Figure 2: Simulation of the 𝑉𝐷𝐴𝐶 evolution

In the graph we can see that when the conversion finishes the signal (𝑉𝐷𝐴𝐶 ) resets to the
𝑉𝑠𝑡𝑎𝑛𝑑𝑏𝑦 just for a CLK period, and then the voltage starts growing again in a ramp shape.

The value of the step taken for every ramp step is:

(𝑉𝑡𝑜𝑝 − 𝑉𝑏𝑜𝑡 )
𝑉𝑠𝑡𝑒𝑝 = = 0.01015625 𝑉
256

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 MICROELECTRONICS: DESIGN AND APPLICATIONS OF MICRO/NANOMETRIC SYSTEMS.

Figure 3: Detail of the 𝑉𝐷𝐴𝐶 evolution

1.4. What is the target of the source follower?

The aim of the source follower is to provide isolation between the signal generation stage and
the comparator stage so that there is no disturbance or noise of the 128 comparators gates
that can affect our 𝑉𝐷𝐴𝐶 signal.

1.5. When are the signals 𝑬𝑶𝑪<𝒊> activated?

The 𝐸𝑂𝐶<𝑖> signals are activated whenever the voltage 𝑉𝐷𝐴𝐶 reaches its corresponding 𝑉𝑖𝑛<𝑖> .
When it’s activated its corresponding latch is triggered in order to save the conversion made in
the register.

1.6. Complete the timeline by adding control signals.

Figure 4: Complete timeline of control signals

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 Unit 7: Ramp Converters
Sensors in Integrated Technologies
When the voltage 𝑉𝐷𝐴𝐶 is higher than the value of the voltage 𝑉𝑖𝑛 the signal 𝐸𝑂𝐶 goes HIGH.

When the 𝐸𝑂𝐶 is triggered the first 8 bits of the signal 𝑅𝑂𝑊_𝐴𝐷𝐶_𝑂𝑈𝑇𝑆 change their values
to the value obtained in the conversion, and this value is saved to the registers.

The signal 𝑅𝐸𝐴𝐷 is used to obtain the lecture of the register.

1.7. What are the design trade-offs involving the resistor

implementation?
The main problem is about the ramp generator, since it’s required to have a good matching in
the resistance so that the ramp generator works properly. Also, resistors are a great source of
noise.

1.8. When the ramp transitions between 𝑽𝒕𝒐𝒑 and 𝑽𝒔𝒕𝒂𝒏𝒅𝒃𝒚 the ADC is
not converting, why?
When our circuit is transitioning from 𝑉𝑡𝑜𝑝 to 𝑉𝑠𝑡𝑎𝑛𝑑𝑏𝑦 , there should not be any conversion
since this transition will take time. This is because the ramp makes that each step of voltage is
small so that there are no problems with transition times and the value between phases.

However, whenever we reset the circuit a great change in the voltage is made from 𝑉𝑡𝑜𝑝 to
𝑉𝑠𝑡𝑎𝑛𝑑𝑏𝑦 and also at a high operation speed so this clock cycle between conversions is needed
for the circuit to correctly reset.

1.9. Propose circuit modifications to implement a double ramp

converter.
A double ramp converter is a kind of analog-to-digital converter that employs two voltage
ramps, one positive and one negative, to transform an analog input signal into a digital output
value. Compared to the single ramp converter with a resistive ladder and control logic that we
had before, the double ramp converter has several benefits:

• Enhanced linearity: The use of two ramps can enhance the linearity of the conversion
process, resulting in greater accuracy and precision in the digital output values.
• Decreased sensitivity to noise: The use of two ramps can also decrease the
converter’s sensitivity to noise and variations in the input signal, resulting in more
stable and dependable digital output values.

To implement a double ramp converter, we would need to modify the existing circuit by
adding a second resistive ladder and a second ramp generator. The second resistive ladder and
ramp generator would generate a negative voltage ramp that would be compared to the input
signal in the same manner as the positive ramp.

When the positive ramp voltage exceeds the input voltage for a given analog input, a positive
comparator triggers a latch, which stores the digital output value corresponding to that analog
input voltage. When the negative ramp voltage exceeds the input voltage for the same analog
input, a negative comparator triggers a second latch, which stores a sign bit indicating whether
the input voltage is positive or negative.

The use of two ramps allows for the determination of both the magnitude and sign of the input
voltage, resulting in a signed digital output value that can represent both positive and negative
input voltages.