A UVM Based Methodology for

Processor Verification
Abhineet Bhojak, Stephan Herrmann
Tejbal Prasad
Freescale Semiconductor

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 Processor Verification Challenges
• Different kind of instructions and excessive number of GPRs
leading to massive functional space and we need to target the
pertinent
• Presence of asymmetric and out-of-order pipelines
– Various hazards (e.g. RAW ,WAR,WAW, Branches)
• Dedicated Hardware Accelerators in parallel with pipeline
• Debug hooks for the ease of debug

Debug
Stimuli Generator

Program generation

• Most important • Hazard scenario •Debug Hooks for

• Need of multiple • Accelerator localization of failure
tests • Jump & Loop cmd

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 Existing Technologies
• Random test pattern generators (RTPG) and Test plan automation tools
• Define a specific scenario description language and take as declarative
input architecture and micro-architecture
• Uses sophisticated CSP solver with bias to generate test programs
• there is a significant learning curve involved to leverage these RTPG’s in
a project schedule along with a considerable cost factor

• Formal verification
• Useful and efficient in some cases
• it requires significant mathematics skill and computational resources to
relate to the scenarios and analyze them

• Pure directed testing

• Gives confidence on different functionalities
• Achieving desired coverage may take large amount of time

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 PROPOSED METHODOLOGY
• Efficient constrained
random stimuli
generation mechanism
for creating
meaningful and highly
reusable scenarios

• Focus on running top

level use cases with
minimum efforts to
achieve high
confidence

• Reducing the debug

time for better time-
to-market

• A methodology for
processor verification
using the open sources
UVM , SV & C/C++.

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 Proposed Stimulus Generation Flow
• A fine blend of Top Down control and Bottom layer intelligence
• Better control over random stimuli and high reuse

Program Generator Atomic Transaction

Scenario

• Skeleton of the • It does the • It randomizes all the

decision making fields and pack them
program is into one instruction.
generated based on Scenario
• Bottom layer
• Size of the program level information intelligence
is controlled • It Randomizes • Takes care of infinite
• Data for the atomic transaction loop
program is based on • Does instruction
controlled fixed/random operand interlinking
type or to a fixed • Extension for
• Provides the Top instruction grouping for
/random
Down Control better reuse
instruction

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 Bottom Layer Intelligence
How to put in this
Interesting intelligence w/o
scenario complicating
load address1, R3
constraint solver ?
load address2, R4
add R3, R4, R5
store R5, address3 Potential Hazard Candidate
Innovative Way
Conventional Way

Randomize one instruction at a time.

Randomize the whole program

Keep copy of last few instruction.

Use foreach constraint to make
relation between instruction
operand
While randomizing current instruction 1st decide to
what depth (rel_depth) you want to link it
Use last instruction copy & rel_depth to decide the
current instruction operand

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Bottom Layer Intelligence

Operand Interlinking
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 Proposed flow in action
MOV R1,VAL Jump Length
Loop: constraints

JMP LEN1

LEN1
INSTRUCTION GROUPS
BRANCH ALU W-
•BEQ •ADD FILL SUB R1,1 MARK
•BLT •SUB BZ End
•BGT •XOR

LEN2
•BN •OR
•BC •CMP JMP LEN2

LENGT
SUB R1,1 H
BNZ Loop
End: HALT

Infinite Loop Avoidance

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 Debugging Hooks
• Zero time • Out-of-order • To get the
Reference model execution of desired
Vs pipelined pipeline Vs In- confidence
processor order execution running directed
• Checking only at of model use cases is a
interfaces is not • Need checker must
enough for based on • Switch based
complex register content flow for directed
scenarios change – Data stimulus which
• Register trace trace checker uses program ,
queue based data/images and
Checker configuration as
file based input
Debug cannot be Localization of Scenario
an afterthought. Failure Replication

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 Debugging Hooks

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Evaluation of the Proposed Flow
Design Complexity
Scalar, Vector & Matrix operation, 9 ALUs, 4 Multiplier, ~256 GPRs
& Hardware Accelerator like SORT, HISTOGRAM etc

Verification
30 man weeks of effort, Verification Environment created from
Scratch, ~200 test /15 K runs, ~10 k functional cover points, 200
odd defects were found

First Pass Success

No additional bugs found after IP signoff.
Silicon has been evaluated - considered to be a first pass success.

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 Thank You
Q&A

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