1.

9 REFERENCES
R. Geiger, P. Allen, and N. Strader. VLSI: Design Techniques for Analog and Digital Circuits. McGraw-Hill, New York, 1990.
P. Gray, P. J. Hurst, S. H. Lewis, and R. G. Meyer. Analysis and Design of Analog Integrated Circuits, 5th. ed. John Wiley &
Sons, New York, 2009.
D. Hodges and H. Jackson. Analysis and Design of Digital Integrated Circuits, 2nd ed. McGraw-Hill, New York, 1988.
D. Roulston. Semiconductor Devices. McGraw-Hill, New York, 1990.
C. G. Sodini, P.-K. Ko, and J. L. Moll, “The effect of High Fields on MOS Device and Circuit Performance,” IEEE Trans. Electron
Devices, Vol. 31, pp. 1386-1393, October 1984.
S. M. Sze. Physics of Semiconductor Devices. Wiley Interscience, New York, 1981.
Y. Tsividis. Operation and Modeling of the MOS Transistor. McGraw-Hill, New York, 1987.
S. Wolf. Silicon Processing for the VLSI Era—Volume 3: The Submicron MOSFET. Lattice Press, Sunset Beach, California, 1995.

2.1.2 Photolithography and Well Definition

Photolithography is a technique in which selected portions of a silicon wafer can be masked so that some type of
processing step can be applied to the remaining areas. Although photolithography is used throughout the manufacture
of an integrated circuit, here we describe this photographic process in the context of preparing the wafer for
defining the well regions.1
Selective coverage for well definition is performed as follows. First, a glass mask, M1, is created, which
defines where the well regions will be located. The glass mask is created by covering the mask in photographic
materials and exposing it to an electron beam, or e beam, in the regions corresponding to the well locations. Such
exposure results in the well regions on the glass mask turning opaque, or dark. As a result, the glass mask can be
thought of as a negative of one layer of the microcircuit. In a typical microcircuit process, ten to twenty different
masks might be required. The cost for these masks varies considerably depending upon the minimum feature sizes
to be patterned on the microcircuit. For example, currently a set of masks for a 0.35-μm CMOS process might cost
roughly $30,000, whereas the cost of a mask set for the most advanced modern processes approaches $1,000,000.
Because a high degree of precision is required in manufacturing these masks, often (but not always) a company
other than the integrated circuit processing company makes the masks. The creation of the opaque regions of the
mask by the electron beam is controlled by a computer dependent on the contents of a database. The database
required for the e beam is derived from the layout database produced by the designer, using a computer-aided
design (CAD) software program.
The first step in masking the surface of the wafer is to thermally grow a thin layer of silicon-dioxide (SiO2) to
protect the surface of the microcircuit. Details of this step are discussed later. On top of the SiO2, a negative photoresist,
PR1, is evenly applied to a thickness of around 1 μm while spinning the microcircuit. Photoresist is a lightsensitive
polymer (similar to latex). In the next step, the mask, M1, is placed in close proximity to the wafer, and
ultraviolet light is projected through the mask onto the photoresist. Wherever the light strikes, the polymers crosslink,
or polymerize. This change makes these regions insoluble to an organic solvent. This step is shown in Fig. 2.1

1. Wells are doped regions that will contain one of the two types of transistors realized in a CMOS process. For example, wells that are n type contain -channel
transistors

The regions where the mask was opaque (i.e., the well regions) are not exposed. The photoresist is removed in these
areas using an organic solvent. Next, the remaining photoresist is baked to harden it. After the photoresist in the
well regions is removed, the uncovered SiO2 may also be removed using an acid etch. (However, in some processes
where this layer is very thin, it may not be removed.) In the next step, the dopants needed to form the well are
introduced into the silicon using either diffusion or ion implantation (directly through the thin oxide, in cases where
it has not been removed). The procedure just described involves a negative photoresist, where the exposed photoresist remains after the
masking. There are also positive photoresists,in which the exposed photoresist is dissolved by the organic solvents. In this case, the
photoresist remains where the mask was opaque. By using both positive and negative resists, a single mask can sometimes be used for two
steps—first, to protect one region and implant the complementary region and second, to protect the complementary region and implant the
original region. The feature sizes that may be patterned using photolithography are influenced by the wavelength of light used. When the
integrated circuit features are smaller than the wavelength of light (currently 193-nm ultraviolet light is used), the wave nature of light results
in patterns on the photoresist that do not precisely match those of the mask. Fortunately, these effects can be partially compensated for by
modifying the mask pattern so that the resulting geometries more closely match those intended by the designer. This technique is referred to
as “optical proximity correction” and is a common practice to realize feature sizes below 100 nm. Further improvements have been made by
immersing the photolithography in a liquid bath. Doing so changes the path of light resulting in improved resolution and improved tolerance
to unevenness of the substrate surface. Efforts are ongoing to reduce the minimum feature sizes that may be patterned by using shorter
wavelengths for photolithography (extreme ultraviolet light or even X-rays).

Key Point: Most features on integrated circuits are patterned using photolithography whereby
light is passed through a mask to cast patterns onto the underlying silicon wafer, ultimately
defining the circuit's physical features such as transistor sizes and wiring.