Reinforcement: 05-10 Years' relevant CIE answers.

Section 1.10

Past Papers with Examiner Comments:

Oct/NOV 2011. P11
Question:
9 (a) Complete the table to show the outputs for the possible inputs to this circuit.

[2]

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Section 1.10

(b) Complete the table to show the outputs for the possible inputs to this circuit.

[4]

Answer:
(a)

[2]

[4]

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Section 1.10

Examiner Comment:
(a) This was well answered by most candidates.
(b) This was well answered by most candidates.
3
Cambridge International Advanced Level
9691 Computing November 2011
Principal Examiner Report for Teachers
© 2011

Oct/NOV 2011. P12

Question:
9 (a) Complete the table to show the outputs for the possible inputs to this circuit.

[5]
(b) State a possible use for this circuit in a processor. [1]

Answer:
(a)

(1 for C column and 4 for S column) [5]

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Section 1.10

(b) – Adds together two single bits/A half adder [1]

Examiner Comment:
(a) This was well answered by most candidates.
(b) The better candidates realised that the logic circuit was a half adder.

Oct/NOV 2011. P13

Question:

9 (a) Complete the table to show the outputs for the possible inputs to this circuit.

[2]
(b) Complete the table to show the outputs for the possible inputs to this circuit.

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Section 1.10

[4]
Answer:
(a)

(1 for C and 1 for D) [2]

(b)

(1 per pair, max 4) [4]

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Section 1.10

Examiner Comment: (a) This was well answered by most candidates.

(b) This was well answered by most candidates.

May/June 2012. P11/12

Question:
9 (a) Complete the truth table to show the output from the logic gate shown.

[2]
(b) Complete the truth table to show the outputs from the logic circuit shown.

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Section 1.10

[4]
Answer:

Examiner Comment:
(a) Most candidates correctly completed the truth table for a NOR gate.
(b) Most candidates correctly completed the truth table for the given logic circuit.

May/June 2012. P13

Question:
9 (a) Complete the truth table to show the output from the logic gate shown. [2]

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Section 1.10

(b) Complete the truth table to show the outputs from the logic circuit shown.

[4]

Answer:
(a) ABX
001
011
101
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Section 1.10

110
(1 mark for the 1,1 and 1 mark for 1, 0) [2]
(b) ABCDY
00011
01000
10011
11101
(1 mark for each row). [4]

Examiner Comment:
(a) Most candidates correctly completed the truth table for a NAND gate.
(b) Most candidates correctly completed the truth table for the given logic circuit.

Oct/NOV 2012. P11

Question:
10 (a) (i) Complete the truth table for this logic circuit. [1]

(ii) State a single logic gate which would have the same final outcome as this pair of
logic gates. [1]

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Section 1.10

[4]
Answer:
(a) (i) 10.

1 mark for both columns correct [1]

(ii) NAND gate [1]
(b)

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Section 1.10

(1 for each bold box) no follow through [4]

Examiner Comment:

(a) The vast majority of candidates correctly completed the truth table and realised that the two given
logic gates could be replaced by a NAND gate.
(b) The majority of candidates correctly completed the first part of the truth table. Only a minority of
candidates knew how to complete the remaining input values for A, B and C and the output values
for D, E and F. Candidates need to understand that input values for a truth table should ‘count up’
in binary from all inputs as 0 until all inputs are 1.

Oct/NOV 2012. P12

Question:
10 (a) (i) Complete the truth table for this logic circuit. [1]

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Section 1.10

(ii) State a single logic gate which would have the same final outcome as this pair of
logic gates. [1]
(b) Complete the truth table for this logic circuit.

[4]

Answer:
(a) (i)

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Section 1.10

1 mark for both columns correct [1]

(ii) A NOR gate [1]
(b)

(1 for each bold box) [4]

Examiner Comment:
(a) The vast majority of candidates correctly completed the truth table and realised that the two given
logic gates could be replaced by a NOR gate.
(b) The majority of candidates correctly completed the first part of the truth table. Only a minority of
candidates knew how to complete the remaining input values for A, B and C and the output values
for D, E and F. Candidates need to understand that input values for a truth table should ‘count up’
in binary from all inputs as 0 until all inputs are 1.

Oct/NOV 2012. P13

Question:
10 (a) (i) Complete the truth table for this logic circuit.

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Section 1.10

[1]
(ii) State a single logic gate which would have the same final outcome as this pair of
logic gates. [1]
(b) Complete the truth table for this logic circuit.

[4]
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Section 1.10

Answer:
(a) (i) A B C D

[1]
(ii) NAND gate [1]
(b)

(1 mark for each bold box) [4]

Examiner Comment:
(a) The vast majority of candidates correctly completed the truth table and realised that the two given
logic gates could be replaced by a NAND gate.
(b) The majority of candidates correctly completed the first part of the truth table. Only a minority of
candidates knew how to complete the remaining input values for A, B and C and the output values
for D, E and F. Candidates need to understand that input values for a truth table should ‘count up’
in binary from all inputs as 0 until all inputs are 1.

May/June 2013. P11/P12

Question:
9 (a) Draw the logic circuit corresponding to the following logic statement:
X = 1 IF (A is 1 AND B is 1) OR (B is 1 OR C is NOT 1)

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Section 1.10

[4]
(b) Complete the truth table for the above logic statement:

[4]

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Section 1.10

Answer:

Examiner Comment:
(a) This question was very well answered; however, some of the drawings of the logic gates needed
further improvement. Candidates need to realise that Examiners have to interpret the shapes of the
logic gates that are drawn – for example, if the gate drawn was a mixture of an AND gate and an
OR gate (which was unfortunately fairly common) then no mark could be awarded. Also marks
were lost for careless mistakes such as not drawing the NOT gate properly. Some candidates
used circles with the words NOT, AND and OR inside the circles; this is acceptable at the moment.
(b) This question was very well answered with marks from 0 to 4 seen.

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Section 1.10

May/June 2013. P13

Question:
6 (a) Draw the logic circuit corresponding to the following logic statement:
X = 1 IF ( (A is NOT 1 AND B is 1) OR (B is 1 AND C is 1) ) OR (C is 1)

[5]
(b) Complete the truth table for the above logic statement:

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Section 1.10

[4]

Answer:

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Section 1.10

Examiner Comment:
(a) This question was very well answered; however, some of the drawings of the logic gates needed
further improvement. Candidates need to realise that Examiners have to interpret the shapes of the
logic gates that are drawn – for example, if the gate drawn was a mixture of an AND gate and an
OR gate (which was unfortunately fairly common) then no mark could be awarded. Also marks
were lost for careless mistakes such as not drawing the NOT gate properly. Some candidates
used circles with the words NOT, AND and OR inside the circles; this is acceptable at the moment.
It was also common to see inputs to AND gates and OR gates being joined together so effectively
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Section 1.10

these gates were one input gates.

(b) Very well answered with the marks from 0 to 4 seen.

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