5 4 3 2 1

DESIGN CURRENT 0.1A +3VL

DESIGN CURRENT 0.1A +5VL
B+
Ipeak=8.13A, Imax=5.69A, Iocp min=8.7 DESIGN CURRENT 5A +5VALW
SUSP#
D D
DESIGN CURRENT 2A +1.8VS
SY8033BDBC
PXS_PWREN#
DESIGN CURRENT 2A +1.8VGS
SUSP FDS6676AS

N-CHANNEL DESIGN CURRENT 4A +5VS

SI4800
ODD_EN#
DESIGN CURRENT 1.6A +5VS_ODD
P-CHANNEL
AO-3413
RT8205LZQW
VCCP_PWRGOOD

Ipeak=6A, Imax=4.A, Iocp min=8 DESIGN CURRENT 6A +VCCSA

SY8037

PXS_PWREN
DESIGN CURRENT 3.8A +VDDCI
SY8033BDBC

Ipeak=5A, Imax=3.5A, Iocp min=6.2A DESIGN CURRENT 5A +3VALW

C WOL_EN# C

P-CHANNEL DESIGN CURRENT 330mA +3V_LAN

AO-3413

AOAC_EN#
DESIGN CURRENT 1A +3V_WLAN
P-CHANNEL
SUSP AO-3413

N-CHANNEL DESIGN CURRENT 4A +3VS

SI4800 LCD_ENVDD

P-CHANNEL DESIGN CURRENT 1.5A +LCD_VDD

AO-3413

PXS_PWREN
DESIGN CURRENT 60mA +3VGS
P-CHANNEL
VR_ON AO-3413

DESIGN CURRENT 94A +CPU_CORE

NCP6132A DESIGN CURRENT 33A +GFX_CORE

SUSP#

B
Ipeak=20.53A, Imax=14.37A, Iocp min=23.91A +1.05VS_VCCP B
TPS51212
+1.05VS_PCIE
PJP404
PXS_PWREN

DESIGN CURRENT 4.2A +1.0VGS

APL5916

SYSON
Ipeak=15A, Imax=10.5A, Iocp min=18A DESIGN CURRENT 10A +1.5V
RT8207M SUSP

N-CHANNEL DESIGN CURRENT 2A +1.5V_CPU

FDS6676AS

DESIGN CURRENT 2A +1.5VS

PJ1

SUSP or 0.75VR_EN#
DESIGN CURRENT 1.5A +0.75VS
PX_MODE

A DESIGN CURRENT 8.6A A

N-CHANNEL +1.5VGS
FDS6676AS
SUSP#

Ipeak=33.8A, Imax=23.4A, Iocp min=40A DESIGN CURRENT 20.5A +VGA_CORE

TPS51518RUKR

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/11/11 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Tree
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QCLA4 LA-8861P M/B
Date: Tuesday, February 14, 2012 Sheet 3 of 58
5 4 3 2 1
 A B C D E

( O MEANS ON X MEANS OFF )

Voltage Rails Platform SKU CPU PCH VGA
+5VS
+RTCVCC B+ +5VL +5VALW +1.5V
+3VS HM76ES2/HM70C0 Themes/Chlsea
+3VL +3VALW Chief River Clarksfield
+1.8VS (PCHB0@/HM70C0@) (TH@/CH@)
+VSB
power +1.5VS
plane +1.05VS
+0.75VS
1
BTO Option Table 1

+CPU_CORE
+VGA_CORE
Function SKU MIC LAN TPM
+GFX_CORE
+VTT description SKU MIC LAN TPM
State
+VRAM_1.5VS
explain PX4(reserve) Dig Mic Analog Mic 10/100M Giga 9635 9655
+3VS_DGPU
+1.05VS_DGPU BTO PX4@ CAM@ AMIC@ 8105ELDO@ 8111FVB@ TPM9635@ TPM9655@

S0
O O O O O O
S1
O O O O O O
S3
O O O O O X
2
S5 S4/AC
Function 2
O O O O X X
description
S5 S4/ Battery only
O O O X X X explain
S5 S4/AC & Battery BTO
don't exist
O X X X X X
Function
PCH SM Bus Address description
explain
Power Device HEX Address
BTO
+3VS DDR SO-DIMM 0 A0 H 1010 0000 b
+3VS DDR SO-DIMM 1 A4 H 1010 0100 b
+3VS Clock Generator D2 H 1101 0010 b Function
description
3
+3VS WLAN/WIMAX 3

+3VS Clock Generator explain

BTO

SIGNAL
EC SM Bus1 Address EC SM Bus2 Address STATE SLP_S3# SLP_S4# SLP_S5#

Full ON HIGH HIGH HIGH

Power Device HEX Address Power Device HEX Address
S1(Power On Suspend) HIGH HIGH HIGH
+3VL Smart Battery 16 H 0001 0110 b +3VS PCH 96 H 1001 0110 b
+3VS ATI GPU 82 H 1000 0010 b S3 (Suspend to RAM) LOW HIGH HIGH

S4 (Suspend to Disk) LOW LOW HIGH

Power Device HEX Address S5 (Soft OFF) LOW LOW LOW

G3 LOW LOW LOW

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/11/11 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QCLA4 LA-8861P M/B
Date: Tuesday, February 14, 2012 Sheet 4 of 58
A B C D E
 A B C D E

Power-Up/Down Sequence !5+.?@%AB9>?@;82

!5+.?@5**AB9>?@5;
All the ASIC supplies, except for VDDR3, must full y reach their respective
nominal voltages within 20 ms of the start of the r amp-up sequence, though a
shorter ramp-up duration is preferred. There is no timing requirement on the !5+B9>?@;821056
!5+.?@5**AB9>?@5;18CB9>6
ramp up of VDDR3 relative to other power rails.
The external pull-up resistors on the DDC/AUX sign als (if applicable) should "89 :/ 05
ramp up before or after both VDDC and VDD_CT have r amped up. !"##$ !"##%$&'"##$"##%($"##!&$ " 5** 5;
1 VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC # !"##$#)*+ ,!"##$#)#+,!"##$ 1

should reach 90% before VDD_CT starts to ramp up (o r vice versa). #)#+,!"##$"##$"###$"##-$"###$
For power down, reversing the ramp-up sequence is recommended. #..!"##$"$'"
#)*+ ,!"##$#)#+,!"##$#..!"##$ " 5** 5;
'"
!"## " 5** 5;
VDDR3(3.3VGS) "##%/ //" 5** 5;
0*!"##1234"$ ' 5** 5;
PCIE_VDDC(1.0V) 056 "## '
!"##
"##% " 5** 5**
VDDR1(1.5VGS) "##7"## &0# 5** 5**

VDDC/VDDCI(1.12V)

VDD_CT(1.8V)
PE_GPIO0(PXS_RST#) PX_EN 05'>
2 2

PERSTb BIF_VDDC

PE_GPIO1(PXS_PWREN)

REFCLK PX_mode

<//".= MOS
<//"'
Straps Reset
<" SI4800
<"'
Straps Valid <" LDO
<"'

Global ASIC Reset

<0 Regulator
<"!5%
<".= Regulator
<"'
T4+16clock

PWRGOOD
Note:
3 3
PX4.0 +VGA_CORE,VDDCI,+1.5VGS ON
PX4.0 +3VGS, +1.0VGS,+1.8VGS OFF
PX5.0 +3VGS,+VGA_CORE,VDDCI,+1.5VGS,+1.0VGS,+1.8VGS OFF

Power Seguence of Thames and Chelsea

+3VGS

+VGA_CORE

+VDDCI

+1.5VGS
4 4
+1.0VGS

+1.8VGS <20ms
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/03/11 Deciphered Date 2012/03/11 Title
GPU Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 14, 2012 Sheet 5 of 58
A B C D E
 A B C D E

JCPUB

100 MHz +1.05VS_VCCP

@ A28 CLK_CPU_DMI

CLOCKS
BCLK CLK_CPU_DMI <27>
1000P_0402_50V7K 2 1 CC62 PM_DRAM_PWRGD_R H_SNB_IVB# C26 A27 CLK_CPU_DMI#

MISC
<12,31> H_SNB_IVB# PROC_SELECT# BCLK# CLK_CPU_DMI# <27> DPLL_REF_CLK# RC1571 2 1K_0402_5%
@
1000P_0402_50V7K 2 1 CC63 H_PWRGOOD_R T1 PAD TP_SKTOCC# AN34 DPLL_REF_CLK RC1581 2 1K_0402_5%
SKTOCC# A16 DPLL_REF_CLK
DPLL_REF_CLK A15 DPLL_REF_CLK#
DPLL_REF_CLK#

T2 PAD H_CATERR# AL33 @

CATERR# H_DRAMRST# 1 2
1 CC34 180P_0402_50V8J 1

THERMAL
H_PECI AN33 R8 H_DRAMRST#
+1.05VS_VCCP <41> H_PECI PECI SM_DRAMRST# H_DRAMRST# <8>
by ESD requestion and place near CPU

DDR3
MISC
RC159
RC44 2 1 62_0402_5% H_PROCHOT# 1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP_0 RC56 2 1 140_0402_1% DDR3 Compensation Signals
<41> H_PROCHOT# PROCHOT# SM_RCOMP[0]
56_0402_5% A5 SM_RCOMP_1 RC59 2 1 25.5_0402_1% Layout Note:Place these
SM_RCOMP[1] A4 SM_RCOMP_2 RC61 2 1 200_0402_1%
SM_RCOMP[2] resistors near Processor
RC45 2 1 10K_0402_5% H_PWRGOOD H_THERMTRIP#_R AN32
<31> H_THERMTRIP# THERMTRIP#

AP29
PRDY# AP27

PWR MANAGEMENT
PREQ#
AR26 XDP_TCK_R PAD T18
TCK AR27 XDP_TMS_R PAD T27
H_PM_SYNC AM34 TMS AP30 XDP_TRST#_R 2 1 51_0402_5%

JTAG & BPM

@ <28> H_PM_SYNC RC55
1000P_0402_50V7K 2 1 CC70 H_PECI PM_SYNC TRST#
AR28 XDP_TDI_R PAD T28
@ RC183 TDI AP26 XDP_TDO_R PAD T29
1000P_0402_50V7K 2 1 CC67 H_PM_SYNC 1 2 H_PWRGOOD_R AP33 TDO
<31> H_PWRGOOD UNCOREPWRGOOD
0_0402_5%
@
1000P_0402_50V7K 2 1 CC66 BUF_CPU_RST# AL35
PM_SYS_PWRGD_BUF 1 2 PM_DRAM_PWRGD_R V8 DBR#
RC170 130_0402_5% SM_DRAMPWROK
AT28
BPM#[0] AR29
2 Please place near JCPU BPM#[1] AR30 2
BUF_CPU_RST# AR33 BPM#[2] AT30
RESET# BPM#[3] AP32
BPM#[4] AR31
BPM#[5] AT31
+3VALW_PCH BPM#[6] AR32
BPM#[7]
2 1 DRAMPWROK +3VALW_PCH
RC11 200_0402_5% +1.5V_CPU

2 1 TYCO_2013620-2_IVY BRIDGE
1

10K_0402_5% 0.1U_0402_10V7K @
2 RC13 1 CC33 RC14
+3VS
UC1 200_0402_5%
5

74AHC1G09GW_TSSOP5
2

1 2 1
P

<28,41> PM_PWROK
RC12 @ 0_0402_5% B 4 PM_SYS_PWRGD_BUF
2 O
<28> DRAMPWROK A
G

1
3

RC25
39_0402_5%
@
1 @ 2 0_0402_5%
1 2

RC184
D
SUSP 2 QC2
<10,44> SUSP
G 2N7002_SOT23-3
S
3

@
3 3

Buffered Rest to CPU FAN Control Circuit (RPM)

+3VS

+5VS JFAN @
1 0.1U_0402_10V7K 1A +FAN2 1
CC36 2 1
+1.05VS_VCCP @ 2 3 2
PLT_RST# <30,36,37,38,41,42> 3

1
C13 C15
2 10U_0805_6.3V6M 4
GND
1

UC2 1000P_0402_50V7K 5

2
PLT_RST# 1 RC38 U1 1 GND
OE# 5 75_0402_5% 1 8
VCC EN GND ACES_85204-0300N
2 7
2 RC35 +FAN2 3 VIN GND 6 R24 10K_0402_5%
2

IN 43_0402_1% 4 VOUT GND 5 2 1

<41> EN_DFAN1 VSET GND +3VS
4 BUFO_CPU_RST# 1 2 BUF_CPU_RST# 10mil
OUT

1
3 APL5607KI-TRG_SO8 FAN_SPEED1
GND FAN_SPEED1 <41>
1

C17 1
74AHC1G125GW_SOT353-5 RC40 10U_0805_6.3V6M C14

2
0_0402_5% 0.01U_0402_25V7K
@ @
2
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/11/11 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Ivy Bridge_JTAG/XDP/FAN
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QCLA4 LA-8861P M/B
Date: Tuesday, February 14, 2012 Sheet 6 of 58
A B C D E
 A B C D E

+GFX_CORE

1
+GFX_CORE

JCPUG
POWER RC105
10_0402_1%
Close to CPU

33A

2
SENSE
AT24 AK35 VCC_AXG_SENSE
VAXG1 VCC_AXG_SENSE <52>

LINES
AT23 VAXG_SENSE AK34 VSS_AXG_SENSE
AT21 VAXG2 VSSAXG_SENSE VSS_AXG_SENSE <52>
AT20 VAXG3 1 RC106 2
1 AT18 VAXG4 10_0402_1% 1
AT17 VAXG5
AR24 VAXG6
AR23 VAXG7 +V_SM_VREF should +1.5V_CPU
AR21 VAXG8 have 20 mil trace width RC120
AR20 VAXG9 1 1K_0402_0.5%
2
AR18 VAXG10 AL1 +V_SM_VREF
AR17 VAXG11 SM_VREF 1 1K_0402_0.5%
2
VAXG12

VREF
AP24 1 RC109
AP23 VAXG13
AP21 VAXG14 CC65
AP20 VAXG15 B4 0.1U_0402_10V7K
VAXG16 SA_DIMM_VREFDQ +VREF_DQA_M3 2
AP18 D1
VAXG17 SB_DIMM_VREFDQ +VREF_DQB_M3
AP17
AN24 VAXG18
AN23 VAXG19 +1.5V_CPU Decoupling:
VAXG20
AN21
AN20 VAXG21 +1.5V_CPU
1X 330U (6m ohm), 6X 10U
AN18 VAXG22
AN17 VAXG23 5A

GRAPHICS
AM24 VAXG24 AF7 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K
AM23 VAXG25 VDDQ1 AF4 1 ESR 6mohm

DDR3 -1.5V RAILS

AM21 VAXG26 VDDQ2 AF1
VAXG27 VDDQ3 1 1 1 1 1 1
AM20 AC7 CC57 CC51 CC52 CC55 CC54 CC56 + CC53
AM18 VAXG28 VDDQ4 AC4 @
AM17 VAXG29 VDDQ5 AC1 330U_D2_2VM_R6M
AL24 VAXG30 VDDQ6 Y7 2 2 2 2 2 2 2
AL23 VAXG31 VDDQ7 Y4
AL21 VAXG32 VDDQ8 Y1 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K
AL20 VAXG33 VDDQ9 U7
AL18 VAXG34 VDDQ10 U4
AL17 VAXG35 VDDQ11 U1
2 AK24 VAXG36 VDDQ12 P7 2
AK23 VAXG37 VDDQ13 P4
AK21 VAXG38 VDDQ14 P1
AK20 VAXG39 VDDQ15
AK18 VAXG40 +VCCSA Decoupling:
VAXG41
AK17
AJ24 VAXG42 1X 330U (6m ohm), 3X 10U
AJ23 VAXG43
AJ21 VAXG44 +VCCSA
VAXG45 Bottom Socket Cavity Co-lay for Cost Down Plan VCCSA_VID0 VCCSA_VID1 +VCCSA
AJ20
AJ18 VAXG46 6A
AJ17 VAXG47 M27
VAXG48 VCCSA1
10U_0805_10V6K 10U_0805_10V6K 0 0 0.90 V
AH24 M26 For Sandy Bridge
VAXG49 VCCSA2
SA RAIL

AH23 L26 1 2 +VCCSA_SENSE

AH21 VAXG50 VCCSA3 J26
VAXG51 VCCSA4 1 1 1 1 1 RC200 0_0402_5% 0 1 0.80 V
AH20 J25 CC42 CC41 CC43 CC40
AH18 VAXG52 VCCSA5 J24 + CC44
AH17 VAXG53 VCCSA6 H26
VAXG54 VCCSA7 2 2 2
@
2
@ 1 0 0.725 V
H25 330U_D2_2VM_R6M
VCCSA8 2
10U_0805_10V6K 10U_0805_10V6K 1 1 0.675 V
VCCPLL Decoupling: Bottom Socket Edge
+1.8VS
1X 330U (6m ohm), 1X 10U, 2x1U H23
VCCSA_SENSE +VCCSA_SENSE <51>
1.2A
1.8V RAIL

RC119 1 @ 2
2 1 10U_0805_10V6K +1.8VS_VCCPLL B6 RC111 0_0402_5%
0_0805_5% A6 VCCPLL1 C22 H_VCCSA_VID0
MISC

A2 VCCPLL2 VCCSA_VID[0] C24 H_VCCSA_VID0 <51>

VCCPLL3 VCCSA_VID[1]
H_VCCSA_VID1
H_VCCSA_VID1 <51>
Please kindly check whether
1 1 1 there is pull-down resister
CC59 CC60 CC61 in PWR-side or HW-side
3 3
1U_0402_6.3V6K A19
2 2 2 VCCIO_SEL

1U_0402_6.3V6K TYCO_2013620-2_IVY BRIDGE

@
+1.5V_CPU +1.5VS C464
PJ1 @ 4.7U_0805_10V4Z
2 1 1 2
+1.5V_CPU +1.5V 2 1
JUMP_43X118 C463
Vgs=10V,Id=14.5A,Rds=6mohm +1.5V 1 2
CC46 1 2 0.1U_0402_10V7K QC4
1 8 1U_0402_6.3V6K
CC47 1 2 0.1U_0402_10V7K 2 S D 7 1 2
S D

2
1 3 6 C469
CC48 1 2 0.1U_0402_10V7K RC203 CC68 4 S D 5 4.7U_0805_10V4Z
470_0805_5% 10U_0805_10V6K G D
CC45 1 2 0.1U_0402_10V7K FDS6676AS_SO8 RC204
2 RUN_ON_CPU1.5VS3 1 2
+VSB

3 1
220K_0402_5%

6
2N7002KDWH_SOT363-6 1
QC5B CC69 RC205 QC5A
SUSP 5 0.1U_0402_25V6 820K_0402_5%
2 SUSP
2 SUSP <6,44>

1
2N7002KDWH_SOT363-6
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/11/11 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Ivy Bridge_POWER-2
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QCLA4 LA-8861P M/B
Date: Tuesday, February 14, 2012 Sheet 10 of 58
A B C D E
 A B C D E

JCPUH JCPUI JCPUE CFG Straps for Processor

(CFG[17:0] internal pull high 5~15K to VCCIO)
AT35 AJ22
AT32 VSS1 VSS81 AJ19
AT29 VSS2 VSS82 AJ16 T35 F22 AH27 PAD T3 CFG2
AT27 VSS3 VSS83 AJ13 T34 VSS161 VSS234 F19 T17 PAD CFG0 AK28 VCC_DIE_SENSE AH26
VSS4 VSS84 VSS162 VSS235 CFG[0] VSS_DIE_SENSE

1
AT25 AJ10 T33 E30 T16 PAD CFG1 AK29
AT22 VSS5 VSS85 AJ7 T32 VSS163 VSS236 E27 CFG2 AL26 CFG[1] RC79
AT19 VSS6 VSS86 AJ4 T31 VSS164 VSS237 E24 T5 PAD CFG3 AL27 CFG[2] 1K_0402_1%
AT16 VSS7 VSS87 AJ3 T30 VSS165 VSS238 E21 CFG4 AK26 CFG[3] L7
AT13 VSS8 VSS88 AJ2 T29 VSS166 VSS239 E18 CFG5 AL29 CFG[4] RSVD28 AG7

2
AT10 VSS9 VSS89 AJ1 T28 VSS167 VSS240 E15 CFG6 AL30 CFG[5] RSVD29 AE7
AT7 VSS10 VSS90 AH35 T27 VSS168 VSS241 E13 CFG7 AM31 CFG[6] RSVD30 AK2
1 AT4 VSS11 VSS91 AH34 T26 VSS169 VSS242 E10 T19 PAD CFG8 AM32 CFG[7] RSVD31 1

CFG
AT3 VSS12 VSS92 AH32 P9 VSS170 VSS243 E9 T12 PAD CFG9 AM30 CFG[8] W8
AR25 VSS13 VSS93 AH30 P8 VSS171 VSS244 E8 CFG10 AM28 CFG[9] RSVD32
VSS14 VSS94 VSS172 VSS245
T14 PAD
CFG[10] PEG Static Lane Reversal - CFG2 is for the 16x
AR22 AH29 P6 E7 T20 PAD CFG11 AM26
AR19 VSS15 VSS95 AH28 P5 VSS173 VSS246 E6 T21 PAD CFG12 AN28 CFG[11] AT26
VSS16 VSS96 VSS174 VSS247 CFG[12] RSVD33
AR16
VSS17 VSS98
AH25 P3
VSS175 VSS248
E5 T22 PAD CFG13 AN31
CFG[13] RSVD34
AM33 1: Normal Operation; Lane # definition
AR13 AH22 P2 E4 T23 PAD CFG14 AN26 AJ27
AR10 VSS18 VSS99 AH19 N35 VSS176 VSS249 E3 AM27 CFG[14] RSVD35 matches socket pin map definition
VSS19 VSS100 VSS177 VSS250
T26 PAD CFG15
CFG[15] CFG2
AR7 AH16 N34 E2 T24 PAD CFG16 AK31
VSS20 VSS101 VSS178 VSS251 CFG[16]
AR4 AH7 N33 E1 T25 PAD CFG17 AN29 0:Lane Reversed
AR2
AP34
AP31
VSS21
VSS22
VSS23
VSS102
VSS103
VSS104
AH4
AG9
AG8
N32
N31
N30
VSS179
VSS180
VSS181
VSS252
VSS253
VSS254
D35
D32
D29
CFG[17]

T8
*
CFG4
AP28 VSS24 VSS105 AG4 N29 VSS182 VSS255 D26 RSVD37 J16
VSS25 VSS106 VSS183 VSS256 RSVD38

1
AP25 AF6 N28 D20 AJ31 H16
AP22 VSS26 VSS107 AF5 N27 VSS184 VSS257 D17 AH31 VAXG_VAL_SENSE RSVD39 G16 RC82
AP19 VSS27 VSS108 AF3 N26 VSS185 VSS258 C34 AJ33 VSSAXG_VAL_SENSE RSVD40 1K_0402_1%
AP16 VSS28 VSS109 AF2 M34 VSS186 VSS259 C31 AH33 VCC_VAL_SENSE @
AP13 VSS29 VSS110 AE35 L33 VSS187 VSS260 C28 VSS_VAL_SENSE

2
AP10 VSS30 VSS111 AE34 L30 VSS188 VSS261 C27
VSS31 VSS112 VSS189 VSS262

RESERVED
AP7 AE33 L27 C25 AJ26 AR35
AP4 VSS32 VSS113 AE32 L9 VSS190 VSS263 C23 RSVD5 RSVD_NCTF1 AT34
AP1 VSS33 VSS114 AE31 L8 VSS191 VSS264 C10 RSVD_NCTF2 AT33
AN30 VSS34 VSS115 AE30 L6 VSS192 VSS265 C1 RSVD_NCTF3 AP35
VSS35 VSS116 VSS193 VSS266 RSVD_NCTF4 Embedded Display Port Presence Strap
AN27 AE29 L5 B22 AR34
AN25 VSS36 VSS117 AE28 L4 VSS194 VSS267 B19 RSVD_NCTF5
AN22
AN19
VSS37
VSS38
VSS39
VSS VSS118
VSS119
VSS120
AE27
AE26
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15 F25
RSVD8 *
1 : Disabled; No Physical Display Port
attached to Embedded Display Port
AN16 AE9 L1 B13 F24
AN13 VSS40 VSS121 AD7 K35 VSS198 VSS271 B11 F23 RSVD9
VSS41 VSS122 VSS199 VSS272 RSVD10 CFG4
AN10
VSS42 VSS123
AC9 K32
VSS200 VSS273
B9 D24
RSVD11 RSVD_NCTF6
B34 0 : Enabled; An external Display Port
AN7 AC8 K29 B8 G25 A33
2 AN4 VSS43 VSS124 AC6 K26 VSS201 VSS274 B7 G24 RSVD12 RSVD_NCTF7 A34 device is connected to the Embedded 2
AM29 VSS44 VSS125 AC5 J34 VSS202 VSS275 B5 E23 RSVD13 RSVD_NCTF8 B35 Display Port
AM25 VSS45 VSS126 AC3 J31 VSS203 VSS276 B3 D23 RSVD14 RSVD_NCTF9 C35
AM22 VSS46 VSS127 AC2 H33 VSS204 VSS277 B2 C30 RSVD15 RSVD_NCTF10
AM19 VSS47 VSS128 AB35 H30 VSS205 VSS278 A35 A31 RSVD16
AM16 VSS48 VSS129 AB34 H27 VSS206 VSS279 A32 B30 RSVD17
AM13 VSS49 VSS130 AB33 H24 VSS207 VSS280 A29 B29 RSVD18
AM10 VSS50 VSS131 AB32 H21 VSS208 VSS281 A26 D30 RSVD19 AJ32
AM7 VSS51 VSS132 AB31 H18 VSS209 VSS282 A23 B31 RSVD20 RSVD51 AK32
AM4 VSS52 VSS133 AB30 H15 VSS210 VSS283 A20 A30 RSVD21 RSVD52
AM3 VSS53 VSS134 AB29 H13 VSS211 VSS284 A3 C29 RSVD22
AM2 VSS54 VSS135 AB28 H10 VSS212 VSS285 RSVD23
AM1 VSS55 VSS136 AB27 H9 VSS213 AN35
AL34 VSS56 VSS137 AB26 H8 VSS214 J20 BCLK_ITP AM35
AL31 VSS57 VSS138 Y9 H7 VSS215 B18 RSVD24 BCLK_ITP#
AL28 VSS58 VSS139 Y8 H6 VSS216 RSVD25
AL25 VSS59 VSS140 Y6 H5 VSS217 CFG7
AL22 VSS60 VSS141 Y5 H4 VSS218
VSS61 VSS142 VSS219

1
AL19 Y3 H3 J15 AT2
AL16 VSS62 VSS143 Y2 H2 VSS220 RSVD27 RSVD_NCTF11 AT1 RC85
AL13 VSS63 VSS144 W35 H1 VSS221 RSVD_NCTF12 AR1 1K_0402_1%
AL10 VSS64 VSS145 W34 G35 VSS222 RSVD_NCTF13 @
AL7 VSS65 VSS146 W33 G32 VSS223

2
AL4 VSS66 VSS147 W32 G29 VSS224
AL2 VSS67 VSS148 W31 G26 VSS225 B1 PAD T64
AK33 VSS68 VSS149 W30 G23 VSS226 KEY
AK30 VSS69 VSS150 W29 G20 VSS227
AK27 VSS70 VSS151 W28 G17 VSS228
VSS71 VSS152 VSS229 PEG DEFER TRAINING
AK25 W27 G11
AK22 VSS72 VSS153 W26 F34 VSS230
VSS73 VSS154 VSS231
AK19 U9 F31 TYCO_2013620-2_IVY BRIDGE 1: (Default) PEG Train immediately
3
AK16
AK13
AK10
VSS74
VSS75
VSS76
VSS155
VSS156
VSS157
U8
U6
U5
F29 VSS232
VSS233
@ CFG7 * following xxRESETB de assertion 3

VSS77 VSS158
AK7
VSS78 VSS159
U3 0: PEG Wait for BIOS for training
AK4 U2
AJ25 VSS79 VSS160
VSS80 CFG6

CFG5

1
TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE
RC83 RC84
@ @ 1K_0402_1% 1K_0402_1%
@ @

2
PCIE Port Bifurcation Straps

11: (Default) x16 - Device 1 functions 1 and 2

* disabled

CFG[6:5] 10: x8, x8 - Device 1 function 1 enabled;

function 2 disabled

01: Reserved - (Device 1 function 1 disabled;

function 2 enabled)
4 4

00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/11/11 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Ivy Bridge_GND/RSVD/CFG
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QCLA4 LA-8861P M/B
Date: Tuesday, February 14, 2012 Sheet 11 of 58
A B C D E
 A B C D E

UH1B 2 RH72 1 2.2K_0402_5%

+3VALW_PCH +3VS
PCIE_PRX_C_LANTX_N1 BG34 2 RH70 1 2.2K_0402_5% RH102 4.7K_0402_5%
<37> PCIE_PRX_C_LANTX_N1 PERN1

5
PCIE_PRX_C_LANTX_P1 BJ34 E12 PCH_SMBALERT# RH103 4.7K_0402_5%
<37> PCIE_PRX_C_LANTX_P1 PERP1 SMBALERT# / GPIO11
LAN <37> PCIE_PTX_C_LANRX_N1 CH13 2 1 0.1U_0402_10V7K PCIE_PTX_LANRX_N1 AV32
CH11 2 1 0.1U_0402_10V7K PCIE_PTX_LANRX_P1 AU32 PETN1 H14 PCH_SMBCLK PCH_SMBDATA 3 4
<37> PCIE_PTX_C_LANRX_P1 PETP1 SMBCLK PM_SMBDATA <12,13,36>

2
PCIE_PRX_WLANTX_N2 BE34 C9 PCH_SMBDATA
<36> PCIE_PRX_WLANTX_N2 BF34 PERN2 SMBDATA QH3B
PCIE_PRX_WLANTX_P2
<36> PCIE_PRX_WLANTX_P2 PERP2 12N7002KDWH_SOT363-6
WLAN <36> PCIE_PTX_C_WLANRX_N2 CH14 2 1 0.1U_0402_10V7K PCIE_PTX_WLANRX_N2 BB32 PCH_SMBCLK 6
PETN2 PM_SMBCLK <12,13,36>
CH17 2 1 0.1U_0402_10V7K PCIE_PTX_WLANRX_P2 AY32

SMBUS
<36> PCIE_PTX_C_WLANRX_P2 PETP2 A12 DRAMRST_CNTRL_PCH
BG36 SML0ALERT# / GPIO60 DRAMRST_CNTRL_PCH <8,12> QH3A
BJ36 PERN3 C8 PCH_SMLCLK0 2N7002KDWH_SOT363-6
1 AV34 PERP3 SML0CLK 1
AU34 PETN3 G12 PCH_SMLDATA0 2 RH78 1 2.2K_0402_5%
PETP3 SML0DATA +3VALW_PCH +3VS
BF36 2 RH74 1 2.2K_0402_5%
PERN4

5
BE36
AY34 PERP4 C13 LAN_EN
BB34 PETN4 SML1ALERT# / PCHHOT# / GPIO74 LAN_EN <37> PCH_SMLDATA1 3 4
PETP4 E14 PCH_SMLCLK1 EC_SMB_DA2 <15,41>
SML1CLK / GPIO58

2
BG37
PERN5 QH4B

PCI-E*
BH37 M16 PCH_SMLDATA1
AY36 PERP5 SML1DATA / GPIO75 PCH_SMLCLK1 6 12N7002KDWH_SOT363-6
BB36 PETN5 EC_SMB_CK2 <15,41>
PETP5
BJ38 QH4A
BG38 PERN6 2N7002KDWH_SOT363-6
AU36 PERP6 M7
AV36 PETN6 CL_CLK1
PETP6
Control Link only for support Intel IAMT.

Controller
BG40 T11
PERN7 CL_DATA1

Link
BJ40
AY40 PERP7 +3VALW_PCH
+3VS BB40 PETN7 P10
PETP7 CL_RST1#
RH99 1 2 10K_0402_5% PCH_GPIO20 BE38 PCH_SMBALERT# RH2621 2 10K_0402_5%
BC38 PERN8
RH1041 2 10K_0402_5% CLKREQ_WLAN# AW38 PERP8 DRAMRST_CNTRL_PCH RH76 1 2 1K_0402_5%
AY38 PETN8
RH95 1 210K_0402_5% CLKREQ_LAN# PETP8 LAN_EN RH75 1 2 10K_0402_5%
M10 CLK_REQ_VGA#
PEG_A_CLKRQ# / GPIO47 CLK_REQ_VGA# <15>
Intel Spec: CLK_LAN# Y40 PCH_SMLCLK0 RH73 2 1 2.2K_0402_5%
<37> CLK_LAN# CLK_LAN Y39 CLKOUT_PCIE0N
PCIECLK_RQ0# is suspend well, LAN <37> CLK_LAN CLKOUT_PCIE0P AB37 CLK_PCIE_VGA# PCH_SMLDATA0 RH77 2 1 2.2K_0402_5%

CLOCKS
2 J2 CLKOUT_PEG_A_N AB38 CLK_PCIE_VGA# <14> 2
but we pull high to +3VS <37> CLKREQ_LAN#
CLKREQ_LAN#
PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P
CLK_PCIE_VGA
CLK_PCIE_VGA <14> VGA
for LAN en/disable function
CLK_WLAN# AB49 AV22 CLK_CPU_DMI# +3VALW_PCH
<36> CLK_WLAN# CLK_WLAN AB47 CLKOUT_PCIE1N CLKOUT_DMI_N AU22 CLK_CPU_DMI CLK_CPU_DMI# <6>
WLAN @ @
<36> CLK_WLAN CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI <6> 2 1 CLK_REQ_VGA# 2 1
CLKREQ_WLAN# M1 RH275 10K_0402_5% RH89 10K_0402_5%
<36> CLKREQ_WLAN# PCIECLKRQ1# / GPIO18 AM12
CLKOUT_DP_N AM13
AA48 CLKOUT_DP_P
AA47 CLKOUT_PCIE2N
CLKOUT_PCIE2P BF18 PCH_CLK_DMI# PCH_CLK_DMI# RH79 1 2 10K_0402_5%
PCH_GPIO20 V10 CLKIN_DMI_N BE18 PCH_CLK_DMI PCH_CLK_DMI RH82 1 2 10K_0402_5%
PCIECLKRQ2# / GPIO20 CLKIN_DMI_P
CLKIN_GND1# RH85 1 2 10K_0402_5%
Y37 BJ30 CLKIN_GND1# CLKIN_GND1 RH86 1 2 10K_0402_5%
Y36 CLKOUT_PCIE3N CLKIN_GND1_N BG30 CLKIN_GND1
CLKOUT_PCIE3P CLKIN_GND1_P CLK_DOT# RH80 1 2 10K_0402_5%
PCH_GPIO25 A8 CLK_DOT RH81 1 2 10K_0402_5%
PCIECLKRQ3# / GPIO25 G24 CLK_DOT#
CLKIN_DOT_96N E24 CLK_DOT From Clock Gen. CLK_SATA# RH83 1 2 10K_0402_5%
Y43 CLKIN_DOT_96P CLK_SATA RH84 1 2 10K_0402_5%
Y45 CLKOUT_PCIE4N
CLKOUT_PCIE4P AK7 CLK_SATA# CLK_14M_PCH RH87 1 2 10K_0402_5%
PCH_GPIO26 L12 CLKIN_SATA_N AK5 CLK_SATA
PCIECLKRQ4# / GPIO26 CLKIN_SATA_P

V45 K45 CLK_14M_PCH

For EMI
V46 CLKOUT_PCIE5N REFCLK14IN
CLKOUT_PCIE5P @
PCH_GPIO44 L14 H45 CLK_PCILOOP CLK_PCILOOP 2 @ 1 2 1
PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCILOOP <30>
+3VALW_PCH RH124 10_0402_5% CH28 22P_0402_50V8J
3 3
RH1071 210K_0402_5% PCH_GPIO26 AB42 V47 PCH_X1
AB40 CLKOUT_PEG_B_N XTAL25_IN V49 PCH_X2
RH1101 210K_0402_5% PCH_GPIO25 CLKOUT_PEG_B_P XTAL25_OUT
PASSWORD_CLEAR# E6
RH1121 210K_0402_5% PCH_GPIO44 PEG_B_CLKRQ# / GPIO56 RH37
1

JPW Y47 XCLK_RCOMP 1 2 1 2 PCH_X1

XCLK_RCOMP +1.05VS_VCCDIFFCLKN <36> PCH_X1_R
@ V40 RH115 90.9_0402_1% 0_0402_5%
RH1191 210K_0402_5% PANEL_SEL V42 CLKOUT_PCIE6N GCLK@
2

CLKOUT_PCIE6P
RH1141 210K_0402_5% PASSWORD_CLEAR# LVDS_SEL T13 Placement near to YH2
<23> LVDS_SEL PCIECLKRQ6# / GPIO45
V38 K43 CLK_FLEX0
CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64 T72 PAD
FLEX CLOCKS

V37 NOGCLK@
CLKOUT_PCIE7P F47 CLK_FLEX1 RH117 2 1 1M_0402_5%
CLKOUTFLEX1 / GPIO65 T74 PAD
PANEL_SEL K12
PCIECLKRQ7# / GPIO46 H47 CLK_FLEX2 NOGCLK@YH2 25MHZ_20PF_7V25000016
CLKOUTFLEX2 / GPIO66 T73 PAD
AK14
AK13 CLKOUT_ITPXDP_N K49 DGPU_PRSNT# PCH_X1 1 3 PCH_X2
CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67 1 3
GND GND
1 1
PCHB0@ PANTHER-POINT_FCBGA989 Compal common design SW request to CH26 CH27
2 4
add DGPU_Present on this GPIO67
27P_0402_50V8J 27P_0402_50V8J
2 2 NOGCLK@
+3VALW_PCH LVDS_SEL PANEL_SEL NOGCLK@

DGPU_PRSNT#
1 2 10K_0402_5% LVDS_SEL LVDS_SEL PANEL_SEL
RH116
H L H L
DGPU_PRSNT# H L
Single DGPU_PRSNT# 1 @ 2
+3VS
4
Channel (Default) Dual Channel LVDS EDP RH227 10K_0402_5%
4

M/B SKU UMA DIS/OPT 1 2

RH261 10K_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/11/11 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH_PCI-E/SMBUS/CLK
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QCLA4 LA-8861P M/B
Date: Tuesday, February 14, 2012 Sheet 27 of 58
A B C D E
 A B C D E

UH1C

DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0

<7> DMI_CTX_PRX_N0 DMI0RXN FDI_RXN0 FDI_CTX_PRX_N0 <7>
DMI_CTX_PRX_N1 BE20 AY14 FDI_CTX_PRX_N1
<7> DMI_CTX_PRX_N1 DMI1RXN FDI_RXN1 FDI_CTX_PRX_N1 <7>
DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2
<7> DMI_CTX_PRX_N2 DMI2RXN FDI_RXN2 FDI_CTX_PRX_N2 <7>
DMI_CTX_PRX_N3 BG20 BH13 FDI_CTX_PRX_N3
<7> DMI_CTX_PRX_N3 DMI3RXN FDI_RXN3 FDI_CTX_PRX_N3 <7>
BC12 FDI_CTX_PRX_N4
DMI_CTX_PRX_P0 BE24 FDI_RXN4 BJ12 FDI_CTX_PRX_N5 FDI_CTX_PRX_N4 <7>
+3VALW_PCH <7> DMI_CTX_PRX_P0 DMI0RXP FDI_RXN5 FDI_CTX_PRX_N5 <7>
DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6
1 <7> DMI_CTX_PRX_P1 DMI1RXP FDI_RXN6 FDI_CTX_PRX_N6 <7> 1
DMI_CTX_PRX_P2 BJ18 BG9 FDI_CTX_PRX_N7
<7> DMI_CTX_PRX_P2 DMI2RXP FDI_RXN7 FDI_CTX_PRX_N7 <7>
DMI_CTX_PRX_P3 BJ20
<7> DMI_CTX_PRX_P3 DMI3RXP
2 1 PCH_SUSPWRDN#_R BG14 FDI_CTX_PRX_P0
AW24 FDI_RXP0 BB14 FDI_CTX_PRX_P0 <7>
RH234 10K_0402_5% DMI_PTX_CRX_N0 FDI_CTX_PRX_P1
2 1 RI# <7> DMI_PTX_CRX_N0 DMI_PTX_CRX_N1 AW20 DMI0TXN FDI_RXP1 BF14 FDI_CTX_PRX_P2 FDI_CTX_PRX_P1 <7>
<7> DMI_PTX_CRX_N1 BB18 DMI1TXN FDI_RXP2 BG13 FDI_CTX_PRX_P2 <7>
RH157 10K_0402_5% DMI_PTX_CRX_N2 FDI_CTX_PRX_P3
2 1 PCH_LOW_BAT# <7> DMI_PTX_CRX_N2 DMI_PTX_CRX_N3 AV18 DMI2TXN FDI_RXP3 BE12 FDI_CTX_PRX_P4 FDI_CTX_PRX_P3 <7>
<7> DMI_PTX_CRX_N3 DMI3TXN FDI_RXP4 FDI_CTX_PRX_P4 <7>

DMI
RH155 10K_0402_5% BG12 FDI_CTX_PRX_P5 PCH_DPWROK 1 2 PCH_RSMRST#

FDI
DMI_PTX_CRX_P0 AY24 FDI_RXP5 BJ10 FDI_CTX_PRX_P6 FDI_CTX_PRX_P5 <7>
RH128 0_0402_5%
<7> DMI_PTX_CRX_P0 AY20 DMI0TXP FDI_RXP6 BH9 FDI_CTX_PRX_P6 <7>
DMI_PTX_CRX_P1 FDI_CTX_PRX_P7
<7> DMI_PTX_CRX_P1 AY18 DMI1TXP FDI_RXP7 FDI_CTX_PRX_P7 <7>
<7> DMI_PTX_CRX_P2
DMI_PTX_CRX_P2
DMI2TXP Stuff R222 if do not support DeepSX state
DMI_PTX_CRX_P3 AU18
2 1 PCH_RSMRST# <7> DMI_PTX_CRX_P3 DMI3TXP AW16 FDI_INT
FDI_INT FDI_INT <7>
RH163 10K_0402_5%
2 1 PM_PWROK 1 2 DMI_COMP BJ24 AV12 FDI_FSYNC0
+1.05VS_PCH DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 <7>
RH279 10K_0402_5% RH126 49.9_0402_1%
2 1 SYS_PWROK BG25 BC10 FDI_FSYNC1
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 <7>
RH280 10K_0402_5%
1 2 RBIAS_CPY BH21 AV14 FDI_LSYNC0 +RTCVCC
DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 <7>
RH127 750_0402_1%
BB10 FDI_LSYNC1
FDI_LSYNC1 FDI_LSYNC1 <7> DSWVREN 2 1 330K_0402_5%
RH150
Reserve 0 ohm for cost down plan
2010/08/25 RH151 2 @ 1 330K_0402_5%
0_0402_5% Reserve this signal to EC by SW demand DSWVRMEN
A18 DSWVREN
1 @ RH2812
@RH281 2011/10/18a
+3VS 1 @ 2 SUSACK#_R C12 E22 PCH_DPWROK DSWVREN must be always pulled high to +RTCVCC
<41> SUSACK# SUSACK# DPWROK
0.1U_0402_10V7K RH133 0_0402_5%

System Power Management

1 2 DSWVREN - Internal Deep Sleep 1.05V regulator
CH103 RH88 1 2 1K_0402_5% XDP_DBRESET# K3 B9 EC_SWI#
+3VS SYS_RESET# WAKE# EC_SWI# <36,37> * H Enable
5

UH5
2 1 L Disable 2
P

<41,52> VGATE IN1 4 SYS_PWROK P12 N3 PCH_GPIO32

PM_PWROK 2 O SYS_PWROK CLKRUN# / GPIO32
<6,41> PM_PWROK IN2
G

SN74AHC1G08DCKR_SC70-5 PM_PWROK 1 2 PM_PWROK_R L22 G8 SUS_STAT# T76 PAD

3

RH131 0_0402_5% PWROK SUS_STAT# / GPIO61

32.768 KHz
L10
APWROK SUSCLK / GPIO62
N14
CLK_EC <41> Follow EC check list demand,
but don't implement CLKRUN# this fuction
DRAMPWROK B13 D10 PM_SLP_S5#
<6> DRAMPWROK DRAMPWROK SLP_S5# / GPIO63 PM_SLP_S5# <41>
SUSACK#_R 2 @ 1 PCH_SUSPWRDN#_R +3VS
RH282 0_0402_5% PCH_RSMRST# C21 H4 PM_SLP_S4#
<41> PCH_RSMRST# RSMRST# SLP_S4# PM_SLP_S4# <41>
PCH_GPIO32 RH2561 @ 2 8.2K_0402_5%
Stuff R137 if EC does not want to 1 @ 2 PCH_SUSPWRDN#_R K16 F4 PM_SLP_S3#
<41> PCH_SUSPWRDN# SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# PM_SLP_S3# <41>
RH132 0_0402_5%
involve in the handshake mechanism 1 2
for the DeepSX state entry and exit <41> PBTN_OUT#
PBTN_OUT# E20
PWRBTN# SLP_A#
G10 PM_SLP_A# T77 PAD RH160 10K_0402_5%

1 2 PCH_ACIN H20 G16 PM_SLP_SUS# T78 PAD +3VALW_PCH

+3VALW_PCH ACPRESENT / GPIO31 SLP_SUS#
RH161 330K_0402_5%

DH2 PCH_LOW_BAT# E10 AP14 H_PM_SYNC EC_SWI# RH1591 2 10K_0402_5%

1 2 BATLOW# / GPIO72 PMSYNCH H_PM_SYNC <6>
<15,41,46> ACIN
CH751H-40PT_SOD323-2 RI# A10 K14 PCH_GPIO29 PCH_GPIO29 RH1621 @ 2 10K_0402_5%
RI# SLP_LAN# / GPIO29

Reserve this signal to EC by SW demand PANTHER-POINT_FCBGA989

3 3
2011/10/18a
PCHB0@

DH5
PM_PWROK 2 1 PCH_RSMRST#

CH751H-40PT_SOD323-2

DH6
1 2
<45,47> POK
CH751H-40PT_SOD323-2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/11/11 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH_DMI/FDI/PM
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QCLA4 LA-8861P M/B
Date: Tuesday, February 14, 2012 Sheet 28 of 58
A B C D E
 A B C D E

UL1 +3V_LAN CL3 to CL6 close to Pin 27,39,47,48

+LAN_VDD10 CL7 to CL8 close to Pin 12,42
CL1 1 2 0.1U_0402_10V7K PCIE_PRX_LANTX_P1 22 31
<27> PCIE_PRX_C_LANTX_P1 HSOP LED3/EEDO 37 PAD TL1 LL1
8111FVB@ 1 2
CL2 1 2 0.1U_0402_10V7K PCIE_PRX_LANTX_N1 23 LED1/EESK 40 +LAN_REGOUT 1 2 CL3 0.1U_0402_10V7K
<27> PCIE_PRX_C_LANTX_N1 HSON LED0 @ 2.2UH +-5% NLC252018T-2R2J-N 1 2
PCIE_PTX_C_LANRX_P1 17 30 RL2 2 1 10K_0402_5% 1 1 CL4 0.1U_0402_10V7K
<27> PCIE_PTX_C_LANRX_P1 PCIE_PTX_C_LANRX_N1 18 HSIP EECS 32 Layout Note: LL1 must be
LAN_EN RL1 2 1 10K_0402_5% 1 2
<27> LAN_EN <27> PCIE_PTX_C_LANRX_N1 HSIN EEDI

2
within 200mil to Pin36, CL9

G
@ CL13 CL5 0.1U_0402_10V7K
8105ELDO@ 2N7002_SOT23-3 CL13,CL9 must be within 4.7U_0603_6.3V6K 0.1U_0402_10V7K 1 2
CLKREQ_LAN# 1 3 LANCLK_REQ# 16 1 LAN_MDI0+ 200mil to LL1 8111FVB@ 2 2 8111FVB@ CL6 0.1U_0402_10V7K
<27> CLKREQ_LAN# CLKREQB MDIP0 2 LAN_MDI0- 1 2
QL53

S
PLT_RST# 25 MDIN0 4 LAN_MDI1+ 8111FVB@ CL7 0.1U_0402_10V7K
<6,30,36,38,41,42> PLT_RST# PERSTB MDIP1 5 1 2
LAN_MDI1-
1 CLK_LAN 19 MDIN1 7 LAN_MDI2+ 8111FVB@ CL8 0.1U_0402_10V7K 1
<27> CLK_LAN CLK_LAN# 20 REFCLK_P NC/MDIP2 8 LAN_MDI2-
18111FVB@2 <27> CLK_LAN# REFCLK_N NC/MDIN2 10 LAN_MDI3+
RL28 0_0402_5% NC/MDIP3 11 LAN_MDI3-
LAN_X1 43 NC/MDIN3
CKXTAL1 +LAN_VDD10 +LAN_EVDD10
LAN_X2 44 13 +LAN_VDD10 CL19, CL20,CL21 close to pin 13,29,45, respectively
CKXTAL2 DVDD10 +LAN_VDD10
29 1 2 CL22 close to pin 3, respectively
DVDD10 41 LL2 0_0603_5%
DVDD10 CL23,CL24,CL25 close to pin 6,9,41, respectively
EC_SWI# 28 1 1
<28,36> EC_SWI# LANWAKEB 1 2
+3VS RL24 2 1 10K_0402_5% LANCLK_REQ# ISOLATE# 26 27 CL18 CL17 CL19 0.1U_0402_10V7K
ISOLATEB DVDD33 +3V_LAN
8105ELDO@ 39 1U_0402_6.3V6K 0.1U_0402_10V7K 1 2
DVDD33 2 2 CL20 0.1U_0402_10V7K
+3V_LAN RL25 2 @ 1 10K_0402_5% EC_SWI# @ 14 12 1 2
NC/SMBCLK AVDD33 +3V_LAN
RL21 2 1 10K_0402_5% 15 42 CL21 0.1U_0402_10V7K
RL22 1 2 1K_0402_5% 38 NC/SMBDATA AVDD33 47 1 2
+3V_LAN GPO/SMBALERT AVDD33 Close to Pin 21
@ 48 8111FVB@ CL22 0.1U_0402_10V7K
AVDD33 1 2
ENSWREG 33 8111FVB@ CL23 0.1U_0402_10V7K
+3VS LAN_EN 18111FVB@2 ENSWREG 21 +3V_LAN +LAN_VDDREG 1 2
EVDD10 +LAN_EVDD10
RL26 0_0402_5% 34 8111FVB@ CL24 0.1U_0402_10V7K
+LAN_VDDREG VDDREG
35 3 1 2 1 2
VDDREG AVDD10 +LAN_VDD10
6 8111FVB@ LL3 0_0603_5% 1 1 8111FVB@ CL25 0.1U_0402_10V7K
AVDD10
1

9
1 2 46 AVDD10 45 CL28 CL29
1K_0402_5% RL5 2.49K_0402_1% RSET AVDD10 4.7U_0603_6.3V6K 0.1U_0402_10V7K
RL6 24 36 +LAN_REGOUT 8111FVB@ 2 2 8111FVB@
49 GND REGOUT
@ 60 mils
2

PGND
ISOLATE# 1 2 WOL_EN#
RL433 0_0402_5% RTL8111F-CGT_QFN48_6x6 RL8 GCLK@
2 8111FVB@ 1 2 LAN_X2 D99 @ 2
<36> LAN_X1_R LAN_MDI1+ 6 3 LAN_MDI0+
0_0402_5%
I/O4 I/O2
RL7 CL43 10P_0402_50V8J
15K_0402_5% RTL8105E RTL8111E/F 1 2 1 2
Sx Enable Sx Disable S0 RL29 22_0402_5% 5 2
+3V_LAN VDD GND
Wake up Wake up Pin14 NC NC GCLK@ GCLK@ 8105E-VL/VD 8105E-VL/VD
Placement near to YH2 +3V_LAN
Pin15 NC 10K ohm PD
EMI request 11/06 8111F/F-VB
WOL_EN# LOW HIGH HIGH PWM Mode LDO Mode LAN_MDI1- 4 1 LAN_MDI0-
I/O3 I/O1

1
Pin38 NC 1K ohm PH NOGCLK@ YL1 25MHZ_20PF_7V25000016 RL4 0 ohm NC
RL4 (Pull High) AZC099-04S.R7G_SOT23-6
LAN_X1 1 3 LAN_X2 0_0402_5%
1 3 8111FVB@ NC 0 ohm
+3VALW TO +3V_LAN Reserve +3VALW_PCH GND GND
RL23 (Pull Down) D100 @

2
1 1 ENSWREG LAN_MDI2+ 6 3 LAN_MDI3+
Vgs=-4.5V,Id=3A,Rds<97mohm to +3V_LAN for saving CL26 2 4 CL27 I/O4 I/O2

1
+3VALW power consumption on DVT 27P_0402_50V8J 27P_0402_50V8J
NOGCLK@ NOGCLK@ RL23
+3VALW 2 2 0_0402_5% 5 2
+3VALW_PCH +3V_LAN VDD GND
8105ELDO@ For P/N and footprint
Please place them to ISPD page

2
1

2
RL147 CL483 PAD-OPEN 2x2m LAN_MDI2- 4 1 LAN_MDI3-
I/O3 I/O1
2

100K_0402_5% @
@ 0.1U_0402_10V7K PJ31 UL1 AZC099-04S.R7G_SOT23-6
2
2

1 @
2

S
@ RL432 @ QL51
G PJ29
1

1 2 2 2/9: Add for ESD request

<41> WOL_EN#
@
1

47K_0402_5% AO3413_SOT23 D +3V_LAN

2
1

@ PAD-OPEN 2x2m 8105E-VD 10/100M

LAN Conn.
1

3 CL482 8105ELDO@ 3

0.01U_0402_25V7K
1 UL3
2
1 JRJ45
CL682 LAN_MDI0+ 1 16 RJ45_MIDI0+ RJ45_MIDI0+ 1
CL681 LAN_MDI0- 2 TD+ TX+ 15 RJ45_MIDI0- CL39 1000P_0402_50V7K PR1+
1U_0402_6.3V6K TD- TX-
4.7U_0805_10V4Z 1 3 14 2 1 1 2 RJ45_MIDI0- 2
@ 2 4 CT CT 13 RL11 75_0402_1% PR1-
5 NC NC 12 3
NC NC
CL40 1000P_0402_50V7K RJ45_MIDI1+
PR2+ For ESD

1
6 11 2 1 1 2
LAN_MDI1+ 7 CT CT 10 RJ45_MIDI1+ RL12 75_0402_1% RJ45_MIDI2+ 4 D92
1

1
@ LAN_MDI1- 8 RD+ RX+ 9 RJ45_MIDI1- PR3+
RD- RX- AZC199-02SPR7G_SOT23-3
CL35 RJ45_MIDI2- 5
PR3-

3
0.1U_0402_25V6 @
+3V_LAN rising time (10%~90%) need > 1ms and <100m s. 2 10/100M transformer_NS681695 RJ45_MIDI1- 6

3
Place CL35 colse UL4 8111FVB@ PR2-
to UL3 RJ45_MIDI3+ 7 9
LAN_MDI2+ 1 16 RJ45_MIDI2+ PR4+ GND 10
LAN WOL LAN_EN ISOLATEB LAN_MDI2- 2 TD+ TX+ 15 RJ45_MIDI2-
8111FVB@
CL41 1000P_0402_50V7K 8111FVB@ RJ45_MIDI3- 8 GND
TD- TX- PR4-
S0 Sx S0 Sx 3
CT CT
14 2 1 1 2

2
4 13 RL13 75_0402_1% SANTA_130452-S
---------------------------------------------- 5 NC NC 12 CL42 1000P_0402_50V7K D93

2
6 NC NC 11 2 1 1 2 AZC199-02SPR7G_SOT23-3
0 0 0 0 1 1 LAN_MDI3+ 7 CT CT 10 RJ45_MIDI3+ RL15 75_0402_1%
@
@
RD+ RX+

1
LAN_MDI3- 8 9 RJ45_MIDI3- 8111FVB@ 8111FVB@
0 1 0 0 1 1 RD- RX-

1
1 0 1 1 1 1 10/100M transformer_NS681695
For ESD
1 1 1 1 1 0* 1 RJ45_GND 1 2 LANGND
CL36 1000P_1808_3KV7K 1 1
CL34 CL37 CL38
0.1U_0402_25V6 @
4 * 2 220P_0402_50V6K 4.7U_0603_6.3V6K 4
2 2
S3: after SUSP# assert low over 100ms Place CL34 colse
to LAN chip
S4/S5: after SYSON assert low over 100ms

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/11/11 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCIe-LAN-RTL8105E/8111F
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom QCLA4 LA-8861P M/B 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 14, 2012 Sheet 37 of 58
A B C D E
 A B C D E

CardReader Conn.

@ JCRIO

450mA 14
R2957 13 GND
1 2 +3VS_CR 12 GND
+3VS 12
0_0603_5% 11
USB20_N8_R 10 11
1 USB20_P8_R 9 10 1
8 9
HP_R 7 8 USB20_P8 1 2 RR67 USB20_P8_R
<40> HP_R 6 7 <30> USB20_P8
HP_L 0_0402_5%
<40> HP_L 5 6 WCM-2012-900T_0805
MIC1_L 4 5 2 1
<40> MIC1_L MIC1_R 3 4 2 1
<40> MIC1_R MIC_SENSE 2 3 @
<40> MIC_SENSE NBA_PLUG 1 2 3 4
<40> NBA_PLUG 1 3 4
ACES_88058-120N LR9
USB20_N8 1 2 RR66 USB20_N8_R
<30> USB20_N8
0_0402_5%

2 2

CT2 CT4
0.1U_0402_10V7K 0.1U_0402_10V7K
TPM9655@ TPM9655@
CT5
0.1U_0402_10V7K
TPM1.2 on board 0.1U_0402_10V7K
TPM9655@

0.1U_0402_10V7K
+3VS

+VSB_TPM RT12 2 1 0_0603_5%

+3VS
TPM9655@

1
1 2 TPM_XTALI 2 2 2 RT13 2 RT10 2 1 0_0603_5%
+3VALW
CT1 22P_0402_50V8J 0_0603_5% TPM9635@
TPM9635@ CT2 CT4 CT5 TPM9655@ CT8
TPM9635@ TPM9635@ TPM9635@ TPM9635@

2
1
1 1 1 +VDD_TPM 1 0.1U_0402_10V7K CT8

2
@ RT1 0.1U_0402_10V7K
YT1 10M_0402_5% TPM9655@
32.768KHZ_12.5P_1TJF125DP1A000D +VSB_TPM
TPM9635@ 0.1U_0402_10V7K

2
UT1

24
19
10

5
1 2 TPM_XTALO
CT6 22P_0402_50V8J

VSB
VDD
VDD
VDD
TPM9635@ LPC_AD0 26
3 <26,41,42> LPC_AD0 23 LAD0 3
LPC_AD1
<26,41,42> LPC_AD1 20 LAD1
LPC_AD2
<26,41,42> LPC_AD2 LPC_AD3 17 LAD2 6 TPM_GPIO PAD @ T61
<26,41,42> LPC_AD3 LPC_FRAME# 22 LAD3 GPIO 2 TPM_GPIO2 PAD @ T62
<26,41,42> LPC_FRAME# 16 LFRAME# GPIO2
<6,30,36,37,41,42> PLT_RST# PLT_RST# Base I/O Address
LPC_PD# 28 LRESET#
LPCPD#
0 = 02Eh
SERIRQ 27 1 = 04Eh
* +3VS
<26,41> SERIRQ 21 SERIRQ
<30> CLK_PCI_TPM_PCH LCLK TPM9635@

1
@ 1 2 1 @ 2 0_0402_5%
+VSB_TPM 10P_0402_50V8J CT7 RT4 10_0402_5% 15 8 RT5 1 2 TPM9635@
RT11 1 2 0_0402_5% CLKRUN# TEST1 9 RT3
TPM9635@ TESTB1/BADD 4.7K_0402_5%
1

2
PP
RT7 3
NC

2
@ 4.7K_0402_5% TPM_XTALO 14 12 TPM9655@
XTALO NC 1 0_0402_5% RT6
2

+3VS TPM_XTALI 13 NC RT14 1 2 PLT_RST#

XTALI/32K IN 4.7K_0402_5%
@
1

GND
GND
GND
GND

1
1

RT8
RT2 TPM9635@ RT8 TPM9655@
TPM9635@ 0_0402_5% 0_0402_5% SLB 9635 TT 1.2_TSSOP28

25
18
11
4
4.7K_0402_5% TPM9635@
2
2

LPC_PD#

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/11/11 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB-CardReader RTS5129/TPM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom QCLA4 LA-8861P M/B 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 14, 2012 Sheet 38 of 58
A B C D E
 A B C D E

+3VL +3VL
RB1
0.1U_0402_10V7K 0.1U_0402_10V7K 1000P_0402_50V7K CB3 0_0402_5%
1 1 1 1 1 1 0.1U_0402_10V7K 1 2 H_PROCHOT# <6>
1 2 <52> VR_HOT#
CB1 CB2 CB5 CB7 1
0.1U_0402_10V7K D
For EMI 2 2
CB4
2 2
CB6
2 2
QB1 1
H_PROCHOT#_EC 2 CB8

111
125
0.1U_0402_10V7K 1000P_0402_50V7K G 47P_0402_50V8J

22
33
96

67
9
CLK_PCI_EC UB1
SSM3K7002F_SC59-3 S 2

EC_VDD0
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC

EC_VDD/VCC

EC_VDD/AVCC
1
3
RB3
10_0402_5%
@ GATEA20 1 21 WL_BT_LED#
1 <31> GATEA20 KB_RST# 2 GATEA20/GPIO00 GPIO0F 23 EC_BEEP# WL_BT_LED# <43> BATT_TEMPA 1 2 1
2
<31> KB_RST# SERIRQ 3 KBRST#/GPIO01 BEEP#/GPIO10 26 EC_BEEP# <40>
1 CB9 100P_0402_50V8J
<26,38> SERIRQ LPC_FRAME# 4 SERIRQ GPIO12 27
CB11
<26,38,42> LPC_FRAME# 5 LPC_FRAME# ACOFF/GPIO13 1 2
22P_0402_50V8J LPC_AD3 ACIN_D
<26,38,42> LPC_AD3 LPC_AD2 7 LPC_AD3
@ PWM Output CB10 100P_0402_50V8J
2 <26,38,42> LPC_AD2 8 LPC_AD2 63
LPC_AD1 BATT_TEMPA
<26,38,42> LPC_AD1 10 LPC_AD1 BATT_TEMP/GPIO38 64 BATT_TEMPA <45>
<26,38,42> LPC_AD0
LPC_AD0
LPC_AD0LPC & MISC GPIO39
PU by each project
65 ADP_I function decide
12 ADP_I/GPIO3A 66 ADP_I <45,46>
<30> CLK_PCI_EC
CLK_PCI_EC
CLK_PCI_EC AD Input GPIO3B TV tuner +3VS
PLT_RST# 13 75
<6,30,36,37,38,42> PLT_RST# EC_RST# 37 PCIRST#/GPIO05 GPIO42 76 EC_ENBKL temperature
+3VL EC_SCI# 20 EC_RST# IMON/GPIO43 EC_ENBKL <29>
RB2
<31> EC_SCI# 38 EC_SCII#/GPIO0E
47K_0402_5%
1 2 <36> AOAC_WLAN_PWR_EN# GPIO1D 68
EC_RST#
DAC_BRIG/GPIO3C 70 EN_DFAN1
1 2 EN_DFAN1/GPIO3D 71 EN_DFAN1 <6>
DA Output PCH_SUSPWRDN# PCH_SUSPWRDN# <28>
CB12 0.1U_0402_10V7K KSI0 55 IREF/GPIO3E 72 SUSACK#
KSI1 56 KSI0/GPIO30 CHGVADJ/GPIO3F SUSACK# <28> H_PROCHOT#_EC 1 2
@
KSI1/GPIO31
KSI2 57
KSI2/GPIO32
Reserve this signal to EC by SW demand RB6 10K_0402_5%
KSI3 58 83 EC_MUTE# 2011/10/18a
59 KSI3/GPIO33 EC_MUTE#/GPIO4A 84 EC_MUTE# <40>
KSI4 USB_EN#
KSI5 60 KSI4/GPIO34 USB_EN#/GPIO4B 85 USB_EN# <35,39>
KSI6 61 KSI5/GPIO35 CAP_INT#/GPIO4C 86
KSI6/GPIO36 PS2 Interface EAPD/GPIO4D
KSI7 62 87 TP_CLK
KSO0 39 KSI7/GPIO37 TP_CLK/GPIO4E 88 TP_DATA TP_CLK <43> +3VL
40 KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <43>
KSO1
KSO2 41 KSO1/GPIO21
KSO3 42 KSO2/GPIO22 97 VGATE
43 KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 98 VGATE <28,52>
KSO4 WOL_EN#
44 KSO4/GPIO24 WOL_EN/GPXIOA01 99 WOL_EN# <37> 1 2
KSO5 PWRME_CTRL LID_SW#
KSO6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109 VCIN0_PH PWRME_CTRL <26>
RB35 47K_0402_5%
KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 VCIN0_PH <45>
VCIN0_PH connect to
2 KSO7/GPIO27 SPI Device Interface 2
KSO8 47 power portion (9012 only) +5VS
KSO9 48 KSO8/GPIO28 119
KSI[0..7] KSO10 49 KSO9/GPIO29 SPIDI/GPIO5B 120 TP_CLK 1 2
<42> KSI[0..7] 50 KSO10/GPIO2A SPIDO/GPIO5C 126
KSO11 SPI Flash ROM RB8 4.7K_0402_5%
KSO[0..15] KSO12 51 KSO11/GPIO2B SPICLK/GPIO58 128
<42> KSO[0..15] KSO13 52 KSO12/GPIO2C SPICS#/GPIO5A TP_DATA 1 2
KSO14 53 KSO13/GPIO2D RB9 4.7K_0402_5%
KSO15 54 KSO14/GPIO2E 73
RB12 2.2K_0402_5% 81 KSO15/GPIO2F ENBKL/GPIO40 74
1 2 EC_SMB_CK1 82 KSO16/GPIO48 PECI_KB930/GPIO41 89 SYSON 1 2
+3VL
1 2 EC_SMB_DA1 KSO17/GPIO49 FSTCHG/GPIO50 90 BATT_FULL_LED# DRAMRST_CNTRL_EC <26> Reserved for DS3 feature RB10 4.7K_0402_5%
BATT_CHG_LED#/GPIO52 91 BATT_FULL_LED# <43>
RB13 2.2K_0402_5%
77 CAPS_LED#/GPIO53 92 WLAN_RST# <36>
EC_SMB_CK1 GPIO
<45,46> EC_SMB_CK1 EC_SMB_DA1 78 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54 93 BATT_CHG_LOW_LED#
RB15 2.2K_0402_5%
1 2 EC_SMB_CK2 <45,46> EC_SMB_DA1 EC_SMB_CK2 79 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 95 SYSON BATT_CHG_LOW_LED# <43>
+3VS <15,27> EC_SMB_CK2 SM
EC_SMB_CK2/GPIO46 Bus SYSON/GPIO56 SYSON <48>
1 2 EC_SMB_DA2 EC_SMB_DA2 80 121 VR_ON
<15,27> EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 127 VR_ON <52>
RB16 2.2K_0402_5% PM_SLP_S4#
PM_SLP_S4#/GPIO59 PM_SLP_S4# <28>

PM_SLP_S3# 6 100 PCH_RSMRST#

<28> PM_SLP_S3# PM_SLP_S5# 14 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 101 EC_LID_OUT# PCH_RSMRST# <28>
<28> PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 EC_LID_OUT# <31>
<31> EC_SMI#
EC_SMI# 15 102 PROCHOT_IN
PROCHOT_IN <45>
PROCHOT_IN connect VCOUT0_PH_L 1 2
VS_ON <47>
16 EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 103 H_PROCHOT#_EC RB34 0_0402_5%
GPIO0A H_PROCHOT#_EC/GPXIOA06 to power portion (9012 only)
<30> EC_PXCONTROL
EC_PXCONTROL 17 104 VCOUT0_PH_L VCOUT0_PH connect to power portion (9012 only)
GPIO0B VCOUT0_PH/GPXIOA07
PX5 current leakage <39> USB_CHG_EN#
USB_CHG_EN# 18
GPIO0C GPO BKOFF#/GPXIOA08
105 BKOFF#
BKOFF# <23>
BT_ON 19 GPIO 106 PBTN_OUT# RB18
<36> BT_ON 25 GPIO0D PBTN_OUT#/GPXIOA09 107 PBTN_OUT# <28>
PCH_PWR_EN 330K_0402_5%
28 EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 108 PCH_PWR_EN <44> 2 1
FAN_SPEED1 SA_PGOOD
<6> FAN_SPEED1 FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11 SA_PGOOD <51> +3VL
1 2 PM_PWROK_EC WL_OFF# 29
<6,28> PM_PWROK <36> WL_OFF# E51_TXD 30 EC_PME#/GPIO15
RB32 0_0402_5%
<36> E51_TXD E51_RXD 31 EC_TX/GPIO16 110 ACIN_D ACIN_D 2 1
<36> E51_RXD PM_PWROK_EC 32 EC_RX/GPIO17 AC_IN/GPXIOD01 112 EC_ON_R ACIN <15,28,46>
RB751V40_SC76-2 DB1
3 PWR_SUSP_LED# 34 PCH_PWROK/GPIO18 EC_ON/GPXIOD02 114 ON/OFFBTN# 3
<43> PWR_SUSP_LED# 36 SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 115 ON/OFFBTN# <35>
GPI LID_SW#
NUM_LED#/GPIO1A LID_SW#/GPXIOD04 116 SUSP# LID_SW# <43>
SUSP#/GPXIOD05 117 VGA_SEL SUSP# <44,48,49,50>
GPXIOD06 118 EC_PECI 1 2 H_PECI
PECI_KB9012/GPXIOD07 H_PECI <6>
AGND/AGND

122 RB19 43_0402_1% SUSP# 1 2

123 XCLKI/GPIO5D 124 +EC_V18R RB21 10K_0402_5%
GND/GND
GND/GND
GND/GND
GND/GND

<28> CLK_EC XCLKO/GPIO5E V18R

1
GND0

VR_ON 1 2
CB15 RB23 10K_0402_5%
1

1 4.7U_0805_10V4Z
@ RB22 CB16 KB9012QF-A3_LQFP128_14X14 2
11
24
35
94
113

69

1 2 SUSP# 100K_0402_5% 20P_0402_50V8

CB14 180P_0402_50V8J
2
2

RB36
Close to EC EC_ON_R 1 2 +3VL
EC_ON <47>
2.2K_0402_5% 1

1
1U_0402_6.3V6K RB25
CB50 TH@ 10K_0402_5% VGA_SEL High Low
2
(for thermal sensor)

2
VGA_SEL
Pin117 Thames Chelsea

1
For KB9012 EC_ON low pulse work around
RB24
CH@ 10K_0402_5%
4 4
Address 82h 9Ah
RB27 Voltage Comparator Pins FOR 9012 A3 2
100K_0402_5%
1 2 E51_TXD
VCIN0 pin109 >1.2V <1.2V
VCIN1 pin102
Security Classification Compal Secret Data Compal Electronics, Inc.
VCOUT0 pin104 HIGH LOW Issued Date 2011/11/11 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LPC-EC-KB9012&930
VCOUT1 pin103 LOW HIGH Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 14, 2012 Sheet 41 of 58
A B C D E
 5 4 3 2 1

Touchpad Connector

+3VL +5VS +5VALW

JTP
1
2 1
TP_CLK 3 2
<41> TP_CLK 3
TP_DATA 4
<41> TP_DATA 5 4
LID_SW# 6 5
D <41> LID_SW# 6 D
BATT_FULL_LED# 7
<41> BATT_FULL_LED# 7
BATT_CHG_LOW_LED# 8
<41> BATT_CHG_LOW_LED# 8
PWR_SUSP_LED# 9
<41> PWR_SUSP_LED# 9
HDD_LED# 10
1 2 WL_BT_LED_R# 11 10 13
<41> WL_BT_LED# 11 G1
R801 0_0402_5% 12 14
12 G2
WIMAX_LED# 1 2 ACES_50504-0120N-001
R803 @ 0_0402_5% @

CPU VGA PCH

ESD solution Screw Hole H1
H_4P2
H2
H_4P6
H3
H_4P2x4P6
H4
H_3P5
H5
H_3P0
H8
H_3P0
@ @ @ @ @ @
WiMAX LED

1
LED_WIMAX#
LED_WIMAX# <36>
2

@
R819
+3VS
2 1 6 1
10K_0402_5%
5

@
Q156A
3 4 2N7002KDWH_SOT363-6
C C

@
Q156B
2N7002KDWH_SOT363-6
WIMAX_LED#

PTH
NPTH

H7 H10 H11 H12 H13 H14 H15 H20 H9 H16

H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0x4P0N H_3P0N
@ @ @ @ @ @ @ @ @ @

1
SATA LED
SATA_LED# <26>
2

R820
+3VS
2 1 6 1
10K_0402_5%
PCB Fedical Mark PAD
5

HDD_LED# 3
Q5534A
4 2N7002KDWH_SOT363-6
EMI solution
H21 H22
FD1 FD2 FD3 FD4 H_3P0N H_3P0N
Q5534B @ @
2N7002KDWH_SOT363-6 @ @ @ @

1
1 2

1
B @ 0_0402_5% B
R4534

ISPD
UV1 CH@ ZZZ

CHELSEA PRO PCB LA-8861P

PJP1 45@

UH1 HM70C0@
PJP1

Panther Point 82HM70 C-0 HM70

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/11/11 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR/TP/LED/LP/LS/Screw
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QCLA4 LA-8861P M/B
Date: Tuesday, February 14, 2012 Sheet 43 of 58
5 4 3 2 1
 A B C D E

+3VALW TO +3VS +5VALW TO +5VS

Vgs=10V,Id=9A,Rds=18.5mohm +1.8VS
+3VALW +3VS Vgs=10V,Id=9A,Rds=18.5mohm +5VALW +5VS

2
4.7U_0805_10V4Z +5VS +5VALW
1 1 1 1 R470
Q29 C459 C460 4.7U_0805_10V4Z Q30 C461 C462 470_0805_5%

2
470_0805_5%

470_0805_5%
8 1 8 1 For EMI
D S 2 D S 2

2
7 7 1U_0402_6.3V6K R5545

1
D S 3 2 2 D S 3 2 2

0.1U_0402_10V7K

0.1U_0402_10V7K
6 R406 6 R407 10K_0402_5%
5 D S 4 5 D S 4
D G D G 2 2
1U_0402_6.3V6K C822 C821

1
D

1
SI4800BDY_SO8 1 R409 2 +VSB SI4800BDY_SO8 1 R410 2 +VSB <32,33> PCH_PWR_EN# PCH_PWR_EN# Q190

3 1

3 1
0.022U_0402_25V7K

0.01U_0402_25V7K
4.7U_0805_10V4Z

4.7U_0805_10V4Z
1 1 1 120K_0402_5% 1 1 200K_0402_5% @ @ 2 SUSP 1

6
C466 1 1 G
C465 R412 Q10A Q10B C467 C468 R413 Q11A S 2N7002_SOT23-3

3
D

1
820K_0402_5% 820K_0402_5% Q11B
2 2 2 SUSP 5 2 2 @ 2 SUSP 5 2N7002KDWH_SOT363-6 2 Q5527
<41> PCH_PWR_EN
2N7002KDWH_SOT363-6 G
2

1
2N7002KDWH_SOT363-6 S SB570020110

3
2N7002KDWH_SOT363-6 2N7002E-T1-E3_SOT23-3
R5529
100K_0402_5%

2
change R409 to 120k 5%

+5VALW +0.75VS +1.05VS_VCCP

For S3 CPU Power Saving

2
R422 R421 R468
100K_0402_5% 22_0805_5% 470_0805_5%

1
SUSP
<6,10> SUSP

6
<49,51> VCCP_PWRGOOD 1 2 0.75VR_EN
0.75VR_EN <48> D D

1
Q189 Q60
R158 220K_0402_5% Q6A 2 SUSP 2 2N7002_SOT23-3

3
2 2N7002KDWH_SOT363-6 G G
<41,48,49,50> SUSP#
S 2N7002_SOT23-3 S

3
2 2
Q6B

1
SUSP 5 2N7002KDWH_SOT363-6

4
+5VS TO +5VS_ODD +5VS

+5VS_ODD
+3VS +5VS

2
C471 Vgs=-4.5V,Id=3A,Rds<97mohm
R457 R441 0.1U_0402_10V7K
470_0805_5% 10K_0402_5%

2
1

3
S
R440 Q45 PJ28

2
6 1

1
G
4 3 1 2 2 JUMP_43X79
<31> ODD_EN#
@ +5VS_ODD

1
47K_0402_5% 2
D

1
Q53A Q53B AO3413_SOT23

1
2N7002KDWH_SOT363-6 2 ODD_EN# 2N7002KDWH_SOT363-6 C217
0.01U_0402_25V7K
1
1

1
1
C680
3 C679 1U_0402_6.3V6K 3
4.7U_0805_10V4Z 2
@ 2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/11/11 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC-DC INTERFACE
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QCLA4 LA-8861P M/B
Date: Tuesday, February 14, 2012 Sheet 44 of 58
A B C D E
 A B C D

PL1
HCB2012KF-121T50_0805 PH1 under CPU botten side :
1 2
VIN CPU thermal protection at 93 +-3 degree C Please locate these parts
Near EC chip
PL2
HCB2012KF-121T50_0805 Recovery at 56 +-3 degree C
ADPIN 1 2

@ PJP1
1
+3VL

1000P_0402_50V7K

1000P_0402_50V7K
100P_0402_50V8J
+

100P_0402_50V8J
1

1
2 <41,46> ADP_I
1
+ 1

PC1

PC2

PC3

PC4

12.1K_0402_1%
2

1
1K_0402_1%
3

2
-

PR4
PR1
4
-
SINGA_2DW -0005-B03

2
PR2 PR5
0_0402_5% 0_0402_5%
1 2 1 2

100K_0402_1%_TSM0B104F4251RZ
<41> PROCHOT_IN <41> VCIN0_PH

1
20K_0402_1%
PR3

PH1
1

2
PL3
HCB2012KF-121T50_0805
1 2

VMB
PJP2 PL4
1 HCB2012KF-121T50_0805
1 2 1 2
2 3 BATT+
EC_SMCA PQ1
3 4 EC_SMDA TP0610K-T1-GE3_SOT23-3
4 5 TS_A

0.01U_0402_25V7K
5 6

10U_0805_25V6K
6

S
7

D
2
3 1 2
PJSOT24CW_SOT323-3

7
B+ +VSBP
1

1
PC6

PC7
CCM_C250137GR007M262ZR PC5

0.22U_0603_25V7K

0.1U_0603_25V7K
PD1

1000P_0402_50V7K

100K_0402_1%
2

PC9
G
1
PR6

2
@

PC8
2

2
VL

2
2
@ PD2 PR7
PJSOT24CW _SOT323-3 22K_0402_1%
2 1 2 VSB_N_001

1VSB_N_003
1
3 PR8
100K_0402_1%

1 2 PR9
EC_SMB_CK1 <41,46>

1
PR10 100_0402_1% 0_0402_5% D
1 2VSB_N_002 2 PQ2
1 2 <28,47> POK
G SSM3K7002FU_SC70-3
EC_SMB_DA1 <41,46>
PR11 100_0402_1%

.1U_0402_16V7K
S

3
1

PC10
PJP3
1 2 2 1
PR12 6.49K_0402_1%
+3VL +VSBP +VSB

2
PAD-OPEN 2x2m
1 2
BATT_TEMPA <41>
PR13 1K_0402_1%

3 3

RTC Battery

- PBJ1 + PR14
560_0603_5%
PR15
560_0603_5%
2 1 1 2 1 2 +RTCBATT

@ MAXEL_ML1220T10

SP093MX0000

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 2010/01/23 Title
Deciphered Date
PWR-DCIN / BATT CONN / OTP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS SAMSUNG
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 14, 2012 Sheet 45 of 58
A B C D
 5 4 3 2 1

0.75Volt +/- 5%
TDC 0.7A
Peak Current 1A
PL151
HCB1608KF-121T30_0603
D B+ 1 2 1.5V_B+ D
PR155
BST_1.5V 1 2 BOOT_1.5V +1.5V
2.2_0402_5%

2200P_0402_50V7K

10U_0805_25V6K
0.1U_0402_25V6

4.7U_0805_25V6-K
DH_1.5V +0.75VSP

0.22U_0402_10V6K
PC153

PC154

PC157

PC158

2
SW _1.5V

PC155

10U_0805_6.3V6K

10U_0805_6.3V6K

10U_0805_6.3V6K
2

1
@

PC260

PC261

PC262
1
5
DL_1.5V

16

17

18

19

20
PU150

2
VLDOIN
PHASE

UGATE

BOOT

VTT
21 @
PAD
4 15 1
LGATE VTTGND

PQ151 PR152 14 2
PL152 AON7408L 20K_0402_1% PGND VTTSNS

1
2
3
1UH_FDSD0630-H-1R0M-P3_11A_20% 1 2CS_1.5V
2 1 13 3
+1.5VP PC159 CS RT8207MZQW _W QFN20_3X3 GND

5
1U_0603_10V6K
1 2 12 4 VTTREF_1.5V
PR157 VDDP VTTREF
1

1 5.1_0603_5%
C 1 2 VDD_1.5V 11 5 +1.5VP C
390U_2.5V_M

+ VDD VDDQ

PGOOD
PR156 4
PC152

1
4.7_1206_5%

TON
PQ152 +5VALW PC161

FB
S5

S3
2

1
2 FDMC7692S_MLP8-5 0.033U_0402_16V7K

2
SNUB_+1.5VP

PC160

1
2
3

10

6
1U_0603_10V6K
+5VALW

2
PR154
10.2K_0402_1%
FB_1.5V 2 1 +1.5VP

TON_1.5V
1

PC156
680P_0402_50V7K
2

Mode Level +0.75VSP VTTREF_1.5V

2
PR158
S5 L off off

1
887K_0402_1% PR160 PC162
S3 L off on PR159 1.5V_B+ 1 2 10K_0402_1% .1U_0402_16V7K
0_0402_5%
S0 H on on

2
1 2 EN_1.5V
<41> SYSON

1
Note: S3 - sleep ; S5 - power off

EN_0.75VSP
1 @ PC163 @ PR161
0.1U_0402_10V7K 0_0402_5%
B 2 1 B
2

<44> 0.75VR_EN

PR162
0_0402_5%
PJP152 2 1
1 2 <41,44,49,50> SUSP#
PAD-OPEN 4x4m

1
PJP153

+1.5VP
1 2
+1.5V (12A,480mils ,Via NO.= 24) @ PC164
0.1U_0402_10V7K

2
PAD-OPEN 4x4m

PJP76

+0.75VS (1A,40mils ,Via NO.= 3)

1 2
+0.75VSP
PAD-OPEN 3x3m

A A

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2010/07/20 Deciphered Date 2012/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-1.5VP / +0.75VSP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom SAMSUNG 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 14, 2012 Sheet 48 of 58
5 4 3 2 1
 5 4 3 2 1

PL401
HCB1608KF-121T30_0603
+1.05VSP_B+ 2 1
B+
+3VS

2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
1

1
PC401

PC403

PC407

PC408
D D

2
PR401

5
100K_0402_1%

2
PR405 PC405
2.2_0402_5% 0.22U_0402_10V6K 4 PQ401
<44,51> VCCP_PWRGOOD
PU400 1 2 BST1_+1.05VSP 1 2 AON7518
TPS51212DSCR_SON10_3X3

PR402 1 10 BST_+1.05VSP

3
2
1
60.4K_0402_1% PGOOD VBST
1 2 TRIP_+1.05VSP 2 9 UG_+1.05VSP UG_+1.05VSP1 PL402
TRIP DRVH 0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
EN_+1.05VSP 3
EN SW
8 SW _+1.05VSP 1 2 +1.05VSP

5
PR404 FB_+1.05VSP 4 7
0_0402_5% VFB V5IN
+5VALW

330U_D2_2.5VY_R15M
1
1 2 RF_+1.05VSP 5 6 LG_+1.05VSP 1
<41,44,48,50> SUSP# TST DRVL

1
11 PR406 +

PC402
TP
1

PC410 4 4.7_1206_5%
1

1U_0603_10V6K PQ402

1SNUB_+1.05VSP2
@ PC411 PR407 MDU1512RH 2
0.1U_0402_16V7K 470K_0402_1%
2

1
PC412
2

3
2
1
C .1U_0402_16V7K C

2
@ PC413 @ PR408 PC406
1000P_0402_50V7K 1.2K_0402_1% 680P_0402_50V7K

2
1 2 +1.05VSP1 1 2 +1.05VSP

PR409 PR410
4.99K_0402_1% 100_0402_1%
2 1 VCCIO_SENSE1 2 1
VCCIO_SENSE <9>
2

PR414
10K_0402_1%
1

PJP402
1 2

PAD-OPEN 4x4m

PJP403
+1.05VS_VCCP(12A,480mils ,Via NO.= 24)
1 2
B +1.05VSP B
PAD-OPEN 4x4m

PJP404
1 2
+1.05VS_VCCP +1.05VS_PCIE
PAD-OPEN 4x4m

A A

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2010/07/20 Deciphered Date 2012/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-V1.05SP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom SAMSUNG 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 14, 2012 Sheet 49 of 58
5 4 3 2 1
 A B C D

1 1

PU180
SY8033BDBC_DFN10_3X3

PL181 PL182

4
HCB1608KF-121T30_0603 1UH_NRS4018T1R0NDGJ_3.2A_30%
1 2 VIN_1.8VSP 10 2 LX_1.8VSP 1 2

PG
+5VALW PVIN LX +1.8VSP
9 3

68P_0402_50V8J
PVIN LX

1
1

1
PC188
PC184 8

4.7_1206_5%
SVIN

PR186
22U_0805_6.3V6M PR181
6 20K_0402_1%

2
5 FB

22U_0805_6.3V6M

22U_0805_6.3V6M
2

2
EN

1
NC

NC
TP

PC182

PC183
FB_1.8VSP

11

2
<41,44,48,49> SUSP#

SNUB_1.8VSP
1 2 EN_1.8VSP

1
PR183
0_0402_5% PR182

0.1U_0402_10V7K
1
10K_0402_1%

PC187

2
@ PR184

680P_0603_50V7K
47K_0402_5%

PC186
2
@ PJP182
1 2 (3A,120mils ,Via NO.= 6)
+1.8VS

2
2 +1.8VSP 2

PAD-OPEN 4x4m

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-1.8VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS SAMSUNG 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, February 14, 2012 Sheet 50 of 58
A B C D
www.s-manuals.com