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Alcatel-Lucent OmniPCX Enterprise

Communication Server

NDDI2-2 (LS/GS)
Legal notice:

Alcatel, Lucent, Alcatel-Lucent and the Alcatel-Lucent logo are trademarks of


Alcatel-Lucent. All other trademarks are the property of their respective
owners.

The information presented is subject to change without notice.

Alcatel-Lucent assumes no responsibility for inaccuracies contained herein.

Copyright © 2012 Alcatel-Lucent. All rights reserved.

The CE mark indicates that this product conforms to the following Council
Directives:
- 2004/108/EC (concerning electro-magnetic compatibility)
- 2006/95/EC (concerning electrical safety)
- 1999/5/EC (R&TTE)
 
  

Chapter 1
Hardware description

 Presentation ............................................................................................. 1.1


 Environment ............................................................................................. 1.1
 Functional blocks ................................................................................... 1.2
 QLSLAC ........................................................................................................ 1.3
 Analog interfaces ........................................................................................... 1.4
 DSP module .................................................................................................. 1.4
 Common part ................................................................................................. 1.5
 Power supply ................................................................................................. 1.5

Chapter 2
Hardware configuration

 Reference .................................................................................................. 2.1


 Overview .................................................................................................... 2.1
 Assembling NDDI2–2 board ............................................................... 2.2
 Assembling QATI–2 daughter board ............................................... 2.4
 Jumpers on NDDI2–2 and QATI-2 boards ..................................... 2.5
 NDDI2–2 LED ............................................................................................ 2.6

  0-1
 

Chapter 3
External connections

 Connection ............................................................................................... 3.1


 Output pins on NDDI2–2 board ......................................................... 3.2

Chapter 4
CLIPIA Daugtherboard - Operation

 Overview .................................................................................................... 4.1


 CLIP function ........................................................................................... 4.1
 Metering function ................................................................................... 4.1

Chapter 5
CLIPIA Daughterboard - Configuration

 Reference .................................................................................................. 5.1


 Board assembly ...................................................................................... 5.1

Chapter 6
Ground Start (GS) Daughterboard - Operation

 Overview .................................................................................................... 6.1


 Operation ................................................................................................... 6.1

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Chapter 7
Metering Detection Daughter Board

 Overview .................................................................................................... 7.1

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0-4  
 

     

1.1 Presentation
The Loop Start / Ground Start (LS/GS) board is also called Non Direct Dialing In (NDDI2-2)
board. It is an analog board which allows the Private Automatic Branch eXchange (PABX) to
be connected to most public networks. Furthermore, this board allows the PABX to be
connected to a pager system according to the ESPA standard.
The NDDI2-2 board can connect up to eight 2-wire analog lines. Lines 1 to 4 are processed on
the mother board and lines 5 to 8 are processed on the QATI-2 daughter board.
The NDDI2-2 board can handle the following optional daughter boards :
- Calling Line Identification Protocol Interface Adaptor (CLIPIA) board:
This board allows the line impedance to be modified to identify the caller and to detect the
metering pulses.
For more information on the CLIPIA board, see NDDI2-2(LS/GS) - CLIPIA Daugtherboard -
Operation .
- Tax Metering board:
This board is used to detect 12/16 KHz metering pulses.
For more information on the Tax Metering board, see NDDI2-2(LS/GS) - Metering
Detection Daughter Board .
- Ground Start board:
This board is used to seize the line via the ground and to detect incoming calls via
grounding a line wire.
Note:
The Ground Start board is only available in the US market.
Each daughter board is dedicated to 4 network lines, i.e. 2 daughter boards are necessary to
handle 8 lines of an NDDI2-2 board.
For more information on the NDDI2-2 board configuration, see NDDI2-2(LS/GS) - Hardware
configuration .
For more information on the NDDI2-2 board connection, see NDDI2-2(LS/GS) - External
connections .

1.2 Environment
The following figure shows the front and back panel connections of the NDDI2-2 board.
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Chapter 1 #$!%$!  &!'()'*

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Figure 1.1: Input/Output diagram - NDDI2–2 (LS/GS) board

1.3 Functional blocks


The NDDI2-2 board is made up of the following functional blocks:
- Quad Low voltage Subscriber Line Audio - processing Circuit (QLSLAC),
- Analog interfaces,
- Digital Signal Processing (DSP) module,
- Common part,
- Power supply.
The following figure shows how the functional blocks of the NDDI2-2 board are organized.
___change-begin___
1-2       ! "  #$!%$!  &!'()'*
#$!%$!  &!'()'*

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Figure 1.2: Functional block diagram - NDDI2–2 (LS/GS) board

1.3.1 QLSLAC

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Chapter 1 #$!%$!  &!'()'*

A/D and D/A voice signal conversion is ensured by 2 QLSLAC circuits. Each Quad Low
voltage Subscriber Line Audio - processing Circuit (QLSLAC) contains 4 coders-decoders
(CODECS) and supports 4 analog interfaces.
One Time Division Multiplex (TDM) or TS allocation connects both QLSLAC to circuit C1.
The QLSLAC acts as:
- an interface between :
• the Pulse Code Modulation (PCM) bus (Time-Slot Assigner (TSA)) and the processor,
• the SLIC OET/CET management and 4 Signal Processing Channels (SPC),
- the programmable software for transmission features (input impedance, reception and
transmission gains, echo cancellation, µ or A laws coding, etc.).

1.3.2 Analog interfaces


Analog interfaces:
- control the signalling,
- transmit voice,
- receive messages to identify the caller (CLIP), if any.
Interfaces are made up of the following parts:
- protection circuits which consist of:
• overvoltage protection circuits to avoid damage in case of any short circuit,
• EMI filtering circuits to reduce the RFI effects on the telephone line-card.
- impedance for ringing signal:
A firmware command allows a low or high impedance to be connected. This command
allows, with a specific equipment (country dedicated daughter board), either a ringing
impedance or a spark quench circuit to be connected (loop protection circuit during
dialing).
- loop circuits which can be:
• on line loop, a high dynamic impedance circuit with DC current limitation (compatible
with TBR21),
• dialing loop (very low resistance).
- loop current detector.
- polarity detector:
Still used for paging, its use depends on the country for NDDI operation. The polarity can
be detected only if a DC current loop is present.
- interface for AC signalling at hang-up:
The interface allows the AC signalling received during the hang-up phase to be transmitted
from the line to the QLSLAC (to be detected by the DSP). This signaling can be ringing,
dual tone (DT-AS), DTMF, V23 or Bell202 type for line call identification messages (CLIP
function).

1.3.3 DSP module


The Digital Signal Processing (DSP) module has the following functions:

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#$!%$!  &!'()'*

- Tone detection:
Eight channels are available for tone detection. The different paces are validated by the
firmware coupler, levels and frequencies are validated by the DSP software.
- External tone detection on the NDDI2-2 interfaces:
There are two types of tone:
• Dial tone,
• Busy tone.
- Ringing detection:
Eight ringing detection channels are necessary on the NDDI2-2 board. The different paces
are validated by the firmware coupler, levels and frequencies are validated by the DSP
software. The detector must handle frequencies ranging from 14.5 to 68 Hz.
- TAMIS Terminal equipment Alert Signaling (TAS) detection:
Eight TAS detection channels are necessary on the NDDI2-2 board. The TAS can be :
• Dual Tone Alert Signalling (DT-AS),
• Ringing Pulse Alert Signalling (RP-AS).
- Frequency Shift Keying (FSK) demodulation:
Eight FSK demodulation channels are necessary on the NDDI2-2 board (eight FSK carrier
detections are provided). FSK has the following features:
• bit duration: 833 µs,
• 0 logical frequency: 2200 ± 22 Hz (Bellecore) or 2100 ± 16 Hz (ETSI),
• 1 logical frequency: 1200 ± 12 Hz (Bellecore) or 1300 ± 16 Hz (ETSI),
• Signal level reception: -12 to 32.5 dBm (Bellecore) or -11 to -35 dBm (ETSI).
- Dual Tone Multi-Frequency (DTMF) detection:
In some countries, the messages can be transmitted using the 16 DTMF codes.

1.3.4 Common part


The common part is the interface between the NDDI2-2 board and the other ACT boards.
The Revision Code Number (RCN) register of the QLSLAC recognizes the NDDI2-2 board.
The MIC 0 link rated at 2.048 MHz transmits voice for 8 NDDI2-2 lines.
For more information on the common part, see Common Part - Common part.

1.3.5 Power supply


From -48V power supply, the CM8 converter supplies the NDDI2-2 board with +5V, -5V and
+12V.
3.3V regulators supply the QLSLAC and the DSP module.

      ! "  #$!%$!  &!'()'* 1-5


Chapter 1 #$!%$!  &!'()'*

1-6       ! "  #$!%$!  &!'()'*


 

    

2.1 Reference
The NDDI2-2 reference is 3BA 23171 AB.
QATI-2 is the daughter board of the NDDI2-2 board. The QATI-2 reference is 3BA 23184 AB.

2.2 Overview
The following figure gives an overview of the NDDI2-2 (LS/GS) board, its daughter boards and
its jumpers.
___change-begin___
$    ()  !   #$!%$! *+',-!$)'* 2-1
Chapter 2 #$!%$! *+',-!$)'*

___change-end___
Figure 2.1: NDDI2–2 (LS-GS) board with jumpers

2.3 Assembling NDDI2–2 board


Before assembling the NDDI2-2 board, you need to remove the QATI-2 daughter board.
The following figures show how the NDDI2-2 board is assembled and what the different jumper
positions are on the board.
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___change-end___
___change-begin___
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___change-begin___
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Note 1:
When the DC current loop jumper is removed, the current is limited to 28 mA.
___change-begin___
2-2 $    ()  !   #$!%$! *+',-!$)'*
#$!%$! *+',-!$)'*

___change-end___
Caution:
Before positioning the input/output impedance jumpers, you are advised to contact
Alcatel-Lucent technical support because the positioning of these jumpers depends on the
country, specially countries with complex impedances.
___change-begin___
___change-end___
___change-begin___
___change-end___
Note 2:
The assemblies represented with grey background are the ex-factory assemblies.
For more information on the position of the jumpers on the boards and equipment number, see
Jumpers on NDDI2–2 and QATI-2 boards .

$    ()  !   #$!%$! *+',-!$)'* 2-3


Chapter 2 #$!%$! *+',-!$)'*

The X904 assembly is not equipped with jumpers.

2.4 Assembling QATI–2 daughter board


After assembling the NDDI2-2 board, you can assemble the QATI-2 daughter board.
The following figure gives an overview of the QATI-2 daughter board and its jumpers.
___change-begin___
___change-end___
Figure 2.8: QATI-2 board with jumpers
The following figures show how the QATI-2 daughter board is assembled and what the
different jumper positions are on the board.
___change-begin___
2-4 $    ()  !   #$!%$! *+',-!$)'*
#$!%$! *+',-!$)'*

___change-end___
Note 1:
When the DC current loop jumper is removed, the current is limited to 28 mA.
___change-begin___
___change-end___
Caution:
Before positioning the input/output impedance jumpers, you are advised to contact
Alcatel-Lucent technical support because the positioning of these jumpers depends on the
country, specially countries with complex impedances.

Note 2:
When the DC current loop jumper is removed, the current is limited to 28 mA.
For more information on the position of the jumpers on the boards and equipment number, see
Jumpers on NDDI2–2 and QATI-2 boards .

2.5 Jumpers on NDDI2–2 and QATI-2 boards


The following table gives the positioning of the jumpers on the NDDI2-2 (mother board) and
QATI-2 (daugther board) boards.
table 2.1: Jumpers on NDDI2–2 and QATI-2 boards

$    ()  !   #$!%$! *+',-!$)'* 2-5


Chapter 2 #$!%$! *+',-!$)'*

Board name Equipment number DC current loop Input/Output


(Interface) jumpers impedance
jumpers
NDDI2-2 (mother Equipment 1 X1011 X1111
board) Equipment 2 X1021 X1121
Equipment 3 X1031 X1131
Equipment 4 X1041 X1141
QATI-2 (daughter Equipment 5 X1011 X1111
board) Equipment 6 X1021 X1121
Equipment 7 X1031 X1131
Equipment 8 X1041 X1141

Caution:
Before positioning the input/output impedance jumpers, you are advised to contact
Alcatel-Lucent technical support because the positioning of these jumpers depends on the
country, specially countries with complex impedances.

2.6 NDDI2–2 LED


The following figure shows the front panel of the NDDI2-2 board with its LED (Light Emitting
Diode).
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___change-end___
Figure 2.11: NDDI2–2 (LS/GS) board front panel LED
The following table gives the meaning of the NDDI2-2 LED.
table 2.2: Meaning of LED
LED Meaning
CPU (green LED) Processor activity indicator LED

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#$!%$! *+',-!$)'*

LED Meaning
BSY (orange LED) Activity indicator LED of at least one trunk

The following table gives the meaning of the different status of the CPU LED.
table 2.3: Meaning of CPU LED status
Status Meaning
Always ON Initializing
100 ms (ON) / 1 s (OFF) Loading in progress
10 ms (ON) / 10 ms (OFF) Boot flashing
300 ms (ON) / 300 ms (OFF) CPU waiting
8 x (900 ms (ON) / 600 ms (OFF)) / 1 s RAM test error
(OFF)
8 x (300 ms (ON) / 600 ms (OFF)) / 1 s Cheksum error
(OFF)

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Chapter 2 #$!%$! *+',-!$)'*

2-8 $    ()  !   #$!%$! *+',-!$)'*


 

     

3.1 Connection
The NDDI2-2 (LS/GS) board is plugged in an interface position of the ACT shelf.
The following figure shows how the different daughter boards are connected to the NDDI2-2
board and what their positions are on the mother board.
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___change-end___
Figure 3.1: Connection diagram
The following figures give details on how the daughter boards are assembled on the NDDI2-2
board (mother board).
___change-begin___
+    ()  !   ) !*$ ** )'*& 3-1
Chapter 3 ) !*$ ** )'*&

___change-end___
Figure 3.2: Details on the different daughter boards assembly
If the connection is:
- by cable, the distribution frame is carried out with a Type 1 cable with a distribution module
(see TY1 64PTSDIN cable - Cable with Module ) or without a distribution module (see TY1
64PTSDIN cable - Cable without Module ).
- by patch panel (VH cabinet only), the connection is carried out directly using the patch
panel: 2-wire 32-port module (see Patch Panel - 32 ports module - 32 ports module ).
The CLIPIA daughter board possesses different assemblies. For more information on these
assemblies, see NDDI2-2(LS/GS) - CLIPIA Daughterboard - Configuration .

3.2 Output pins on NDDI2–2 board


The following table gives the positioning of the output pins on the back panel rear side of the
NDDI2-2 board.
table 3.1: Output pins on NDDI2–2 board

3-2 +    ()  !   ) !*$ ** )'*&


) !*$ ** )'*&

Back panel rear side view


Wire C Wire B Wire A Equipment number (Interface)
L1b L1a
1 Equipment 1
(Ring) (Tip)
L2b L2a Equipment 2
2
(Ring) (Tip)
L3b L3a Equipment 3
3
(Ring) (Tip)
L4b L4a Equipment 4
4
(Ring) (Tip)
L5b L5a
5 Equipment 5
(Ring) (Tip)
L6b L6a Equipment 6
6
(Ring) (Tip)
L7b L7a Equipment 7
7
(Ring) (Tip)
L8b L8a Equipment 8
8
(Ring) (Tip)
9
10
11
12
13
14
15 GND
16 GND
17
18
19 A48VL_P
20 A48VL_P
21
22
23 GND
24 GND
25 GND
26
27
28 TXD
29 RXD
30 GND
31 STRAP GND STRAP

+    ()  !   ) !*$ ** )'*& 3-3


Chapter 3 ) !*$ ** )'*&

Back panel rear side view


Wire C Wire B Wire A Equipment number (Interface)
32 GND

3-4 +    ()  !   ) !*$ ** )'*&


 
   
  

4.1 Overview
The Call Line Identification Protocol Interface Adaptator (CLIPIA) daughter board allows the
line impedance to be modified for:
- the CLIP function,
- the metering function.
A daughter board handles 4 lines. You need 2 CLIPIA daughter boards for an NDDI2-2
(LS/GS) board.
For more information on the CLIPIA board configuration, see NDDI2-2(LS/GS) - CLIPIA
Daughterboard - Configuration .
For more information on the CLIPIA board connection, see NDDI2-2(LS/GS) - External
connections .

4.2 CLIP function


You need a line impedance of 600 Ohms (conversation excluded) to use the CLIP protocol.
The CLIPIA board has, for each line, a relay controlled by the mother board allowing the
600-Ohm line to be connected when it is not in conversation mode.

4.3 Metering function


To manage accounting pulse reception on the line in some countries, you need a low
impedance of 12 or 16 KHz (selected by a build). The CLIPIA board comprises a resonant
circuit per line, a jumper allows a resonance at 12 or 16 KHz to be selected.

     ()  !   . /0 $-,)1 !$!  2( !$)'* 4-1


Chapter 4 . /0 $-,)1 !$!  2( !$)'*

4-2      ()  !   . /0 $-,)1 !$!  2( !$)'*


 
   
  

5.1 Reference
The CLIPIA board reference is 3BA 23173 AA.

5.2 Board assembly


The following figures show how the CLIPIA board is assembled on the NDDI2-2 board.
___change-begin___
___change-end___
Figure 5.1: CLIPIA board on NDDI2–2 board
___change-begin___
___change-end___
Figure 5.2: Jumpers on CLIPIA board
The following table gives the position of the jumpers on the CLIPIA daughter boards.
table 5.1: Jumpers on CLIPIA board
Daugther board Equipment number Jumper
(Interface)
CLIPIA 1 Equipement 1 X1
Equipement 2 X2
Equipement 3 X3
Equipement 4 X4

     ()  !   . /0 $-,1) !$!  .*+',-!$)'* 5-1


Chapter 5 . /0 $-,1) !$!  .*+',-!$)'*

Daugther board Equipment number Jumper


(Interface)
CLIPIA 2 Equipement 5 X1
Equipement 6 X2
Equipement 7 X3
Equipement 8 X4

5-2      ()  !   . /0 $-,1) !$!  .*+',-!$)'*


 
! " #!"$   
 

6.1 Overview
The Ground Start daughter board reference is 3BA 23196 AA.
The Ground Start daughter board installed on the NDDI2-2 (LS/GS) board is a “Line
Adaptation” which allows to seize the line via the ground and to detect incoming calls via
grounding a line wire. This board is equipped for Ground Start signaling (only available in the
US market).
A Ground Start daughter board is dedicated to 4 network lines. You need 2 Ground Start
daughter boards on the NDDI2-2 (LS/GS) board.
The Ground Start daughter board has no strappings.
For more information on the Ground Start daughter board connection, see NDDI2-2(LS/GS) -
External connections .

6.2 Operation
The ground is sent on the Ring wire and detected on the Tip wire.

The Ground Start board has:


- two control points:
• CET (Terminal State Command) Earth commands connection to the ground on the
Ring wire (1 for connection),
• CET Earth Det On commands connection to the ground on the Tip wire (1 for
connection).
The ground detector may be disconnected during all off-hook phase and dialing phase.
The disconnection may be generated by ground detector during the conversation phase.
- one scan point, OET (Terminal State Scan) B-DET, which indicates the presence of the

 "    ()  !   !-* )$!)  $-,1) !$!  2( !$)'* 6-1
Chapter 6 !-* )$!)  $-,1) !$!  2( !$)'*

ground on the Tip wire.

6-2  "    ()  !   !-* )$!)  $-,1) !$!  2( !$)'*
 
%         
&

7.1 Overview
The metering detector daughter board reference is 3AH 37003 AA.
The metering detector daughter board detects charging impulses. These impulses, coming
from the public network, can be used by the metering process. This daughter board is optional.
A metering detector daughter board is plugged on the NDDI2-2 (LS/GS) mother board and can
process four analog lines. Two daughter boards are needed for the eight lines of NDDI2-2
(LS/GS).
Note:
Two different types of metering detector daughter board must not be installed on a same NDDI2-2
(LS/GS) mother board.
For more information on connection, see: NDDI2-2(LS/GS) - External connections .
The metering detector daughter board can detect 12 or 16 kHz impulses. The type of impulses
to be detected can be configured with straps located on the mother board.
The sensitivity of detection (in mV) can be adjusted to the impulse level with straps located on
the mother board.
For more information on configuration, see: NDDI2-2(LS/GS) - Hardware configuration .

$$      ! "  3 ) !'*,  ) )'* $-,1) ! 4$! 7-1


Chapter 7 3 ) !'*,  ) )'* $-,1) ! 4$!

7-2 $$      ! "  3 ) !'*,  ) )'* $-,1) ! 4$!

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