Aishwarya Hiremath

Austin ,Texas | Phone no. +1 737-262-8893| email: ashhiremath63@gmail.com|

https://www.linkedin.com/in/aishwarya-hiremath-650406101

Summary:
• Specialized in Design verification with 4.5 years of experience in SV-UVM based verification.
• Hands on experience in various aspects of functional verification including detailed verification planning,
environment building, developing testcase and debugging.
• Worked on verification of Network IP, Memory IO & Power Management IP and Protocols like APB, PCIE, ARM-
Q channel expander.

PROFESSIONAL EXPERIENCE :
SENIOR ENGINEER- DESIGN VERIFICATION @MARVELL SEMICONDUCTORS, Pune -INDIA MAY 2019-OCT 2021
• Involved in verification of in-house network IP using PCIE protocol.
• Worked extensively on verification of MAC layer features and a few of TL layer features.
• Developing verification strategy plan to rigorously verify the design for normal operation and corner
cases.
• Involved in migration of legacy environment to UVM environment which involved developing testcases.
• Implementing UVM based directed testcases and debugging the testcases.
• Developed assertion checks for the handshaking mechanism involved in the IP.

DESIGN ENGINEER @ CYIENT LTD, Pune - INDIA APR 2018 -MAY 2019
• I was involved in verification of Memory IO Processor and Power Management Integrated circuit (PMIC).
• Understand the architecture and develop test plan, developing env files and interacting with designer
making sure code coverage goals are achieved as per test plan.
• Verified the memory IO block for packet transformation.Developing Verification plan since the block was
updated with a few new added features for credit mechanism. Implemented UVM testcase to verify the
existing features and newly added credit feature.
• Making sure Memory IO block runs with VIP specified AXI random clocks. Developing the env files and
interacting with designer to meet the feature.
• Developed assertion checks for interface signals and other corner cases for Memory IO
• I was Involved in verifying the registers of PMIC block.

DIGITAL VERIFICATION ENGINNER @KARMIC DESIGN PVT LTD, Manipal-INDIA APR 2017- APR 2018
• I was involved in verification of Power Management IP.
• Worked on Implementation and verification of AMBA APB protocol.
• Verifying the module with ARM based Q-channel expander for low power interface.
• Worked on code coverage and functional coverage - writing the testcase/enhancing the testcase to hit
the bins of CC and writing the testcase to cover the functionality of the testcase.

EDUCATION :
• Master’s in Digital Electronics at S.D.M College of Engineering & Tech. affiliated to Visveswaraiah
Technological University, Karnataka, INDIA (Sep 2014 – Sep 2016)
• Bachelor of Engineering from Visveswaraiah Technological University, Karnataka, INDIA (Sep 2010 - Jun
2014), Electronics and Communication Engineering.