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  • Aparna Upreti Resume

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    Jalaj Gupta
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    This document contains the profile of Aparna Upreti, including her contact information, experience, education, and skills. She has over 9 years of experience in verification domains such as IP verification, USB2.0, SMBus, USB3.0, and SATA. Currently she works as an ASIC Digital Design Engineer Sr II at Synopsys, where her responsibilities include test plan creation and debugging of customer IP. She previously held positions at Mentor Graphics and Truechip Solutions also focused on protocol implementation and verification. Aparna holds an MTech in VLSI and a BTech in Electronics and Communication. Her skills include Verilog, SystemVerilog, UVM, and protocols such as USB,

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    This document contains the profile of Aparna Upreti, including her contact information, experience, education, and skills. She has over 9 years of experience in verification domains such as IP verification, USB2.0, SMBus, USB3.0, and SATA. Currently she works as an ASIC Digital Design Engineer Sr II at Synopsys, where her responsibilities include test plan creation and debugging of customer IP. She previously held positions at Mentor Graphics and Truechip Solutions also focused on protocol implementation and verification. Aparna holds an MTech in VLSI and a BTech in Electronics and Communication. Her skills include Verilog, SystemVerilog, UVM, and protocols such as USB,

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    2 views2 pages

    Aparna Upreti Resume

    Uploaded by

    Jalaj Gupta
    This document contains the profile of Aparna Upreti, including her contact information, experience, education, and skills. She has over 9 years of experience in verification domains such as IP verification, USB2.0, SMBus, USB3.0, and SATA. Currently she works as an ASIC Digital Design Engineer Sr II at Synopsys, where her responsibilities include test plan creation and debugging of customer IP. She previously held positions at Mentor Graphics and Truechip Solutions also focused on protocol implementation and verification. Aparna holds an MTech in VLSI and a BTech in Electronics and Communication. Her skills include Verilog, SystemVerilog, UVM, and protocols such as USB,

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    of 2

    Aparna Upreti

    +919582970409
    er.upreti.aparna@gmail.com

    Pro le
    I have total 9 years of experience.From last 7 years I am working in
    veri cation domain before that I worked on product validation.
    Organised and detail-oriented with proactive and hard-working
    attitude.

    Experience
    ASIC DIGITAL DESIGN ENGINEER SR II
    Synopsys -: May 2021 – Present
    • Working on IP veri cation
    • Roles & Responsibilities:
    ‣ Created Test Plan targeting Pipe6.0 for PCIE6
    ‣ Debugged various scenario and veri ed the Customer IP
    ‣ Updated Monitor checkers and assertions
    ‣ Created coverage plan and implemented coverage model

    Lead Member of Technical Staff


    Mentor graphics -: Sept 2018 – May 2021
    • Worked on USB2.0 and SMBus.
    • Roles & Responsibilities:
    ‣ Developed SMBus VTL Transactor
    ‣ Added different functionality of USB2.0 in VTL
    ‣ Resolve different issues based upon QA team inputs
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    Design Engineer
    Truechip Solutions -: Jan 2015 – Sept 2018
    • Worked on USB3.2,USB3.0,USB2.0 and SATA
    • Roles & Responsibilities:
    ‣ Implementation of driver of protocol layer in USB3.0
    ‣ Created Test plans and Test cases for covering different scenarios of
    USB3.0 protocol layer with the help of XHCI.
    ‣ Tested the customer DUT.
    ‣ In USB2.0 implement the protocol layer and Hub controller
    ‣ . Created sequences for testing of HUB. Regression cleaning and
    debugging.
    ‣ Implemented transport layer monitor in system Verilog i
    ‣ Created coverage monitor for transport layer.
    ‣ Debugging the test cases of SATA 3.3.

    Consultant
    Cadence Design Systems -: Oct 2012 to April 2014
    • Worked on Assertion based Veri cation
    • Roles & Responsibilities: Feature level andIntegration Level testing of
    different features. Created test Plan and Specs which covers all test
    scenarios.

    Education
    • BANASTHALI VIDYAPITH UNIVERSITY
    ‣ Master of Technology VLSI(Jul 2010-2012- 77%)
    • UTTRAKHAND TECHINCAL UNIVERSITY
    Dehradun, Uttarakhand
    ‣ Bachelors of Technology (BTech) Electronics and Communication (Jul
    2006 - 2010 – 76%)

    Skills
    HDLs:Verilog , System Verilog ,UVM
    Tools: NC-sim, Questa-Sim.
    Protocol: USB2.0, USB3.0, SMBus,PCIe,SATA
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