Verdi Basic Training and Technical Overview

Verdi
Basic Training & Technical Overview

Novas Software, Inc
Based on Verdi 5.4v6

Training Course
z Verdi Background and Overview

z Loading Your Design
z nTrace
z nSchema & nState
z Break
z nWave
z Debugging with Verdi
Verdi 5.4 Basic Training -02/22/05

Verdi Background and Overview
Concepts and Technology
Debug in the Design Flow
ESL RTL Gate

Debug Debug
Debug
Verify Verify
Architectural Design Interactive Design SCAN Timing Interactive
Behavioral # Locations Compiler Bist Closure Formal
Testbench GOAL
Regression
Formal Emulation
Debug Debug Debug
IP
Assertions Emulation
Legacy
Properties /Acceleration
Debug Debug
Debug
% of Design/Verification Spent in Debug
Do you know how much time your

teams spend debugging?
50
# of respondants
40
30
20
What else could you be doing with 10
that time?
0
0-10% 11-20% 21-30% 31-40% 41-50% 51-60% 61-70% 71-80% 81-90% 91-100%
Source: Novas Customer Survey, 161 Respondents

The Barriers To Efficient Debug
z Complex Designs
z Increasing device size and complexity
z Barrier to required design understanding
z Complex Behavior
z Complex design cause and effect scenarios
z Increases conditions to be verified
z Complex multi-tool, multi-lingual,
multi-team environments
z Compounds methodology complexity

Novas Solves the Tough Debug Issues
Issues
Complex Environments
Complex Behavior
Complex Designs
Comprehension
Automation
Unification
Knowledge sharing Reusner g g
Increasing automation Verdi
Powerful comprehension and debug Debussy

Novas Technology
Design,
Testbench, Open Analysis
Visualization
Assertions, Databases Engines
Specification,
Layout Info
Behavior Flow Graph
KDB Behavior Analysis
Knowledge Source Code Trace
Database (nTrace)
Structure Analysis
Waveform / Event
(nWave)
Behavior Exploration
Schematic / Structure
FSDB (nSchema)
Behavior Query
Event
FSM / Flow Chart
Database
(nState)
Knowledge Reuse
Full Range Block Diagram /
of Tools Documentation
Comprehensive Debug System - More Than Simple Visualization

Structural / Event Debug Process
Current process involves comparing events, code and structure

across multiple windows to track possible issues
- Time consuming, error prone, complicated

Automating Debug
Critical Productivity Enhancement
Utilizing behavior based debug to automate time consuming aspects of

debug process
z Time and structure in single view

z Immediate visual of design
behavior
z Automated cause / affect tracing
z Understand problem areas
quickly
z Link back to regular views
z Bind problem to modelling issue EDN Magazine Innovation
Award 2002 Finalist

Benefits
z Captures design structure and behavior.

z Generates structural diagrams of RTL or gates.
z Verification results put in context of the design.
z Helps you understand unfamiliar or legacy code.
z Automates difficult debug operations.
z Maintains consistent view of the design through design and
verification process.
z Dramatically cuts your debug time over traditional methods.

Training Course

z nTrace – View and Debug Source Code
z nSchema – View and Debug Designs Graphically
z nState – View and Analyze State Machines
z nWave – View Simulation Results in Waveforms

Before you start…
z Environment Setup
z Verdi Setup File – novas.rc
z Library Mapping
z Symbol Libraries

Environment Setup
z Add binary to the search path.

z setenv NOVAS <Novas_install_dir>.
z set path=($NOVAS/bin $path).
z Specify search path of license file.
z setenv NOVAS_LICENSE_FILE <license_file>
or
z setenv LM_LICENSE_FILE <license_file>:$LM_LICENSE_FILE

Verdi Setup File – novas.rc
z The setup file for Verdi is called novas.rc and contains:

z Mapping information for pre-compiled designs.
z User preferences (set via Tools Æ Preferences).
z Reference to another novas.rc file (optional)
z Search sequence for novas.rc files:
1. -rcFile <filename> command line option (read/write pointer)
2. NOVAS_RC environment variable (read/write pointer)
3. ./novas.rc
4. $HOME/novas.rc
5. <verdi install>/etc/novas.rc
z Specify path for Verdi setup file

z setenv NOVASRC <path>/novas.rc
z Use –rcFile on the verdi command line to overwrite the environment variable.
Logical Library Mapping Details – novas.rc
z Map a library logical name to a physical location in the novas.rc

file.
z Mapping format (in novas.rc):
[Library]
logical name = physical location
pack = ../library/pack
Example:
[Library]
pack = ./work
vital = ./work
z Necessary for VHDL or mixed language designs.
Symbol Libraries
z Why are symbol libraries important?

z Without the symbol mappings for gate cells…
z Active fan-in cone, Fan-in cone and Fan-out cone schematics
will NOT function properly.
z Schematics will show ONLY squares instead of logic cells.
z Symbol mappings differentiate logic gates from Sequential.
z Check the Novas web page, http://www.novas.com/ in the downloads
section for a list of available libraries, Library Developer’s Guide and
cell definitions.
Unmapped Mapped
fanin cone fanin cone

Creating Symbol Libraries
z Automatic (recommend) - If the .lib files of Synopsys are available

z Use the syn2SymDB utility to create symbol library
target_lib.lib++
syn2SymDB –o target_lib synopsys_technology.lib
z Manual - If the .lib files of Synopsys are not available
z You have special cells to create (ASIC/FPGA macro cells)
z Create a .map file using the Library Developer’s Guide, then use
the map2SymDB utility to create the symbol mappings library
target_lib.lib++
map2SymDB –o target_lib manual_technology.map

Specify Symbol Library and Paths
z Use common delimiters between libraries and paths.

z For NOVAS_LIBS only specify the root of the <root>.lib++ directory
name.
setenv NOVAS_LIBS “<LIB ROOT#1> <LIB ROOT#2> ...”
setenv NOVAS_LIBPATHS “<Directory#1> <Directory#2> …”
z Ex:
setenv NOVAS_LIBS “abc def etc”
setenv NOVAS_LIBPATHS “/home /home/on/the/range /etc”
z Where abc, def and etc represent libraries abc.lib++, def.lib++ and
etc.lib++ and they can be found in the different paths listed.
z For the performance issue, set the same process libraries to
NOVAS_LIBS.
Loading Your Design
z Pre-Compiling Design
z Pre-Compiling VHDL - vhdlcom Utility
z Pre-Compiling Verilog - vericom Utility
z Verdi Command Line Options
z Load Pre-Compiled Design from Command Line
z Load Design Files from Command Line
z Load Pre-Compiled Design from the GUI
z Load Design Files from the GUI
z Using Virtual Top

Pre-Compiling a Design (KDB)
z Compile once, load many times.

z Saves load time and overall memory
z Necessary for mixed language or VHDL designs.
z Pre-compile VHDL source files using vhdlcom utility.
z Optional for Verilog language designs.
z Pre-compile Verilog source files using vericom utility.
z By default, a library called work.lib++ is created.
z Uses the novas.rc file logical mapping mechanism

Pre-Compiling Verilog – vericom Utility
vericom [Verdi options] [<your verilog options>]

z Use vericom -h to get all command line options.
z Use vericom to replace verilog simulator commands to create the Verdi
mirror database optimized for debug.
z MTI: vlog top.v –work /home/work –f other_files.f
z NC: ncvlog top.v –WORK /home/work –FILE other_files.f
z VCS: vcs top.v –f other_files.f
z Verdi: vericom top.v –work /home/work –f other_files.f.

Pre-Compiling VHDL – vhdlcom Utility
vhdlcom [verdi options] [<your vhdl options>]

z Use vhdlcom -h to get all command line options.
z Verdi provides pre-compiled versions of STD, IEEE, SYNOPSYS, and
NOVAS libraries which are located at: $NOVAS/etc/kbd/vhdl/
z Use vhdlcom to replace vhdl simulator commands to create the mirror
database.
z MTI: vcom –93 top.vhdl –work /home/work –f other_files.f
z NC: ncvhdl –V93 top.vhdl –WORK /home/work –FILE other_files.f
z Verdi: vhdlcom –93 top.vhdl –work /home/work –f other_files.f
z The vhdlcom or vericom library is of the format work.lib++, pack.lib++,
etc. Thus it never conflicts with simulators libraries.

Verdi Command Line Options
verdi [general options]...

z Use verdi -h to get all command line options.
-f <fileName> : specify a file that lists all source files
-vhdl | verilog: specify language type for import design from source
-vtop : loads Virtual top file
-play commandHistoryFile : play command history file.
-ssc licenseFile : specify the license file name.
-ssr sessionFile : load session file (*.ses).
-ssf fastFile : load fast file (*.fsdb).
-sswr restoreFile(s) : load waveform restore file(s) (*.rc).

Load Pre-Compiled Design From Command Line
verdi -lib <pre-compiled source> -top <top level>
z Reference pre-compiled source on the command line.

verdi –lib abc –top system
z Where abc is the pre-compiled library, abc.lib++ that the design was
pre-compiled into with vericom/vhdlcom.
z Where system is the top level module/architecture

Load Design Files From Command Line
verdi [verdi options] [<your verilog options>]

z Reference source files on the command line (Verilog only).
z Verdi takes all the Verilog command line options.
verdi –f run.f
z Where run.f is a file that contains the verilog source files and any
command line switches.
verdi –ssv –v lib.v +libext+.v –ssy –y /src/abc –y /src/def top.v
z Where –ssv and –ssy are needed only once for design modules
specified with the –v and –y and top.v is the design file.

Load Pre-Compiled Designs from the GUI
z Specify library mapping before importing design.

z Use File Æ Import Design...
or Import Design icon
to import your design.
z Select From Library tab.
z Lists all libraries in current directory
or specified in map file.
z Supports mapping file to set
a Virtual Top.

Load Design Files from the GUI
z Use File Æ Import Design...

or Import Design icon
to import your design.
z Select From File tab.
z Specify language and run file
or individual source files.
z Supports mapping file to set
a Virtual Top.
Note: The imported design does

not get saved as a library.

Compile Design in GUI
z File Æ Compile Design

z File Æ View Import Log
Options GUI will

depend on
Language

Using Virtual Top
z Scenario:
z Design top doesn’t match simulation top (i.e. don’t wish to include the test
bench, test bench code not available or only looking at a portion of a
design)
z Solution:
z Create a file called map.dat that maps the top design module to the
simulation hierarchy.
Format: <module name> = <full hierarchical path>
Example: CPU = system.i_cpu
z Add –vtop map.dat to the Verdi command line and a pseudo hierarchy will
be created.
z Why?
z If a virtual top is not used, active annotation will not work and D&D to
nWave will not work because hierarchical paths will not match.
Loading Your Design – Summary
z At this time you should:

z Understand the Verdi environment setup
z Know how to pre-compile a design
z Know how to invoke Verdi

Training Course


nTrace - View and Debug Source Code
z Mouse Actions
z Overview
z Hierarchy Browser
z Source Code Browser
z Message Window
z Searching
z Find Scope
z Find Signal/Instance
z Find String
z Trace Drivers and Loads
z Bookmarks
z Source Code Editing
z Miscellaneous
z Lab
Mouse Actions (all modules)
z Left Mouse Button(LMB)

z Single-click to select design objects like signals, instances,
groups, etc.
z Hold the Shift key and click the LMB to add object to selection
list.
z Double-click(DC) to take action.
z Drag LMB through an area to select the objects enclosed.
z Drag LMB in schematics or waveforms will zoom in area.
z Middle Mouse Button (MMB)
z Drag & Drop (D&D) across windows.
z Right Mouse Button(RMB)
z Context sensitive menu.
nTrace Overview
z Displays source code and hierarchy

z Compiles the design
z Required for nSchema and nState
z Context sensitive tracing of drivers and loads

nTrace - Overview
Hierarchy Browser Source Code Browser
Message Window
nTrace – Hierarchy Browser
z Displays VHDL architectures and packages, Verilog modules, primitive

instances, tasks and functions.
z Expand/Collapse
design tree.
z Double click folder
to change current
scope.
z Open Folder icon
indicates current
scope.
z Use File Æ Print to print out design tree.

nTrace – Source Code Browser
z Color-coded source code display.

z Double click
z Instance name to go to architecture or module definition.
z Module name or architecture type to return to calling instance.
z Architecture name to go to
entity definition.
z Signal name to find the
driver.
z vi compatible binding keys.

nTrace – Message Window
z Log of debug session.

z Double click on line to go to that location in source code.

nTrace – Find Scope
z Source Æ Find Scope... is a fast way to directly open a Verilog

module or VHDL architecture if the design tree is deep.
z Choose by type: File, Module, Task or Function.
z Enter search filter using wildcards.
Open by Module Open by File

nTrace – Find Signals and Instances
z Source Æ Find Signal... is a fast way to find

signals/instances/Instport in full design or selected scope.
z Supports wildcard characters and regular expressions.

nTrace – Find Strings
z Source Æ Find String… quickly locates a string in current / all files.
z Find String on toolbar quickly locates a string in current scope.

z Enable/disable case matching under
Tools Æ Preferences, Source Code tab,
Miscellaneous tab.
z Use Source Æ Go To command to jump to specified line or First

Executable Line.
nTrace – Trace Drivers and Loads
z To quickly find all the drivers of a signal

z Double click a signal.
z Select signal and click on Trace Driver icon.
z Trace Æ Driver or Right Mouse Button menu.
z To quickly find all the loads of a signal
z Select signal and click on Trace Load icon.
z Trace Æ Load or Right Mouse Button menu.
z To quickly find all the drivers and loads of a signal
z Trace Æ Connectivity or Right Mouse Button menu.
z Dropping a signal in the source window will trace the connectivity of the signal.
z By default, tracing will cross hierarchical boundaries.
z Use Trace Æ Trace Cross Hierarchy to keep within a hierarchy.

nTrace – Trace Driver/Load Tool Bar Icons
Forward History Show Next
Trace Load Show Previous Instance
Trace Driver Show Next Instance
Backward History Show Previous

nTrace – Search, View and Debug Source
Code
z Searching
z Find Scope
z Source Æ Find Scope
z Find Signal/Instance
z Source Æ Find Signal
z Find String
z Source Æ Find String
z Bookmarks
z Source Æ Bookmark
z Multiple Source Code Windows
z Editing Source Code

z Tools Æ Preferences... to select your preferred editor.
z Source Æ Edit Source File

nTrace – Active Annotation
z Display simulation results on source.

z Source Æ Active Annotation in nTrace
z Signal values/transitions are synchronized with cursor time.
z Select signal(s) and go to next or previous transitions.
z Any Change, Rising
or Falling

nTrace – Trace Results and Report
z Trace Æ Save Trace Result saves

Driver/Load/Connectivity in a file for future review.
z Record maximum 32 level trace results.

nTrace – Bookmarks
z Click on Bookmark icon on toolbar or use Ctrl-F2 to toggle a

bookmark on/off at the current line.
z Use Source Æ Bookmark command to get list of current
bookmarks.
z Supports unlimited bookmarks.

nTrace – Source Code Editing
z Use Source Æ Edit Source File command or click icon to edit

your current module.
z Use Tools Æ Preferences... to select your preferred editor.
z Use File Æ Reload Design command to update the changes.

nTrace – Miscellaneous
z Use Tools Æ Preferences... to customize the appearance and fonts

of the hierarchy browser and source code browser.
z Use Help Æ Command Reference for additional information.

nTrace – Wrap-up
z Questions?
z Take 20 minutes to complete

the nTrace LAB

Training Course


nSchema – View and Debug Designs Graphically
z Overview z Schematic Window Types

z Invoke nSchema z Full Hierarchical
z Resultant Schematics z Browser
z Display Source Code z Flatten
z Traverse Hierarchy z View Detail RTL
z Searching Commands z Clock/Reset Tree
z Display Options z Miscellaneous
z Lab

nSchema Overview
z Automatically generates schematic of design

z Gate Level, RTL, behavioral Level
z Hierarchical or flat
z Fan-in or fan-out cones
z Highlight logic between registers

Invoke nSchema
z The “New Schematic” icon

z Select an instance in Hierarchy Browser and click on New
Schematic icon.
z Drag & Drop an instance from the hierarchy browser or a Verilog
module or VHDL architecture from the Source Code Browser to
New Schematic icon.
z Execute Tools Æ New Schematic Æ Current Scope in nTrace.

nSchema – Resultant Schematics
z Storage elements need to be recognized for complete tracing ability.

z Gate level schematic displays cell level netlist.(Symbol libraries required)
z RTL logic diagram displays synthesized view.
z Signal type -- clock, reset, set, flip-flop / latch output or tri-state output
z Block type -- latch, flip-flop or combinational logic
z Enable/Disable Detail RTL option under
Tools Æ Preferences, Schematics tab,
RTL tab.
z State machine recognition as symbolic or

logical views.
z Enable/Disable FSM Recognition option under
Tools Æ Preferences, Schematics tab,
RTL tab.

nSchema – Display Source Code
z To quickly understand what RTL construct created a logic cell

z Double-click on the lowest level RTL to opens View Source Code box of the
corresponding RTL code.
z Drag & Drop a schematic object to nTrace displays the corresponding
source code.

nSchema – Traverse Hierarchy
z Push Into a Module

z Double click on instance or instance port.
z Select an instance and click the Push View In icon .
z Invoke right mouse button menu and select Push View In command.
z Pull down View Æ Push View In.
z Pop View Up
z Use the Pop View Up icon .
z Double-click on a schematic port.
z Invoke right mouse button menu and select Pop View Up command.
z Pull down View Æ Pop View Up or View Æ Pop View Up from Port.
z Click the Last View icon to go to previous view.

nSchema – Searching Commands
z Schematic Æ Find Signal/Instance...

finds signals or instances in full design.
z Schematic Æ Find In Current Scope...
finds signals or instances in current scope.

nSchema – Schematic Window Types
z Full Hierarchical Window – default type

z Partial Hierarchical Window
z Browser Window
z Partial Flatten Window Full Hierarchical
Duplicates Current Schematic
z Flatten Window
z Fan-In / Out Cones Partial Hierarchical
Partial Flatten

nSchema – Full Hierarchical Window
z View, traverse and understand design hierarchy graphically.

z Double click a symbol port to push into the lower level and highlight the
associated net.
z Double click on a net to highlight
all instances which connect to this net.
z Trace menu will highlight a variety
of different objects in current window.
z Search commands
z Schematic Æ Signal/Instance/Instport…
z Schematic Æ In Current Scope…

nSchema – Active Annotation
z Display simulation results on source.

z Schematic Æ Active Annotation in nSchema
z Signal values/transitions are synchronized with cursor time.
z Select signal(s) and go
to next or previous
transitions.
z Any Change, Rising
or Falling

nSchema – Create Partial Hierarchical
Schematics
z Focus on a specified instance or net for debugging.

z Select net(s) or instance(s) while holding Shift key.
z Use Tools Æ New Schematic Æ Browser Window to generate partial
schematic.
z Hierarchical schematic with only those instances connected to selected nets.
z Hierarchical schematic with only those nets connected to selected instances.
z Double click on symbol port to push into the lower level and highlight
the associated net.
z Double click on I/O port to pop up one level.
z Add / delete objects.
z Undo / redo edits.

nSchema – Browser Window Example

nSchema – Create Flattened Schematics
z Focus on a user specified area of the design.

z Select primitive.
z Use Tools Æ New Schematic Æ Flatten Window to generate flat
schematic.
z Add logic by double clicking an instance pin or drag and drop from
other windows.
z Select object and use <Delete> key or icon to remove object
from schematic.

nSchema – Flatten Window Example

nSchema – Create Flattened Schematics –
Fan-in / Fan-out Cones
z Focus on all drivers or loads of selected object.

z Select object (net or primitive instance).
z Use Tools Æ New Schematic Æ Fan-In Cone / Fan-Out Cone to
generate flat schematic.
z Add logic by double clicking an instance pin or drag and drop from
other windows.
z Select object and use <Delete> key or icon to remove object
from schematic.

nSchema – Fan-in Cone Example

nSchema – View Detail RTL on a Window Basis
z New option: View Æ Detail RTL

z Effective in that window only
Non-detail RTL Detail RTL

nSchema – View Detail RTL on Instance Basis
z On RTL Block, RMB Æ Display Detail RTL Block

z New window with details will pop up

nSchema ─ Show Detailed Connections for IO
Pins
z Select one or more pins then invoke RMB Æ Show Detail

Connection
z All detailed connection information will be shown and can be
saved as text file.
Select multiple pins
Save as a text file

nSchema – Miscellaneous
z Use Tools Æ Preferences... to customize the appearance globally.
Manually control the font used

for names on schematics
Apply settings without leaving

the Preferences window
z Use File Æ Print to print multi-page schematics.


nSchema – Miscellaneous (Count.)
z Use Tools Æ Options Æ Trace Cone Stop On Module Boundary or

Tools Æ Preferences... Æ Trace tab to force Trace Æ Fan-In Cone /
Fan-Out Cone to stop on module boundary.
z Set the constrain for tracing the inter-connection net.

nSchema – Summary
z At this time you should

z Understand the nSchema functionality.
z Be able to open a schematic and relate the symbols back to the source
code.
z Know how to locate signal(s) or instance(s) and generate different partial
schematics.
z Be able to access and change the preferences.

Training Course


nState – View and Analyze State Machines
z Overview
z Invoke nState
z Display Options
z Partial FSM
z State Animation
z Analysis Report
z Interacting FSM Display
z Miscellaneous
z Lab

nState Overview
z Display and analyze finite state machines.

z Show or hide conditions / actions on a state or a transition.
z Search by State Sequence.
z State Animation using current simulation results.
z Generate analysis reports using current simulation results.

Invoke nState
z Double click on the state machine symbol in nSchema.

nState – Display Options
z Use View Æ State Action to

display signal assignments for
each state.
z Use View Æ Transition

Condition to display transition
condition on the state diagram.
z Use View Æ Transition Action

to display signal assignments for
each transition.

nState – Partial FSM
z Create partial FSM views to aid understanding

nState – Interacting FSM Display
z Use Tools Æ Extract Interactive FSM… in nTrace or nSchema.

z Shows the interaction between multiple state machines.

nState – State Animation 1
z Load simulation results.

z Enable FSM Æ State Animation.
z Use Previous State / Next State tool bar icons to step through the
states.
z Use FSM Æ Edit Search Sequence to create a sequence of states to
search on.

nState – State Animation 2
State Sequence Animation

nState – Analysis Report
z Use FSM Æ Analysis Report to display analysis report.

z Details of FSM interpretation.
z State coverage report.
z Transition coverage report.
z Save to File command provided.

nState – Miscellaneous
z Use Tools Æ Preferences... to customize the appearance globally.
z Use File Æ Print to print multi-page state diagrams.

nState – Summary

z Understand the nState functionality.
z Be able to open a FSM and enable different display options
z Know how to enable state animation and view analysis reports.

nSchema – Wrap-up
z Questions?

the nSchema and nState LAB

Training Course


nWave - View Design Behavior Using Waveforms
z Overview z Focus Debug Effort

z FSDB File z Search Value and Search
Constraint
z Linking Overview z Markers
z System Tasks z Zero Time Glitch and Event
Sequence
z FSDB Utilities
z Logical Operations
z Invoke nWave z Complex Event
z Open Simulation Results z Waveform Comparisons
z Display and Organize Signals z Analog v.s. Digital
z Adding Signals / Get Signals z Aliasing
Form z Comments
z Group/Bus Operations z Save / Restore Signals
z Display Options and Preference z Lab
nWave Overview
z A complete waveform analysis environment.

z Supports FSDB format (through PLI) or VCD file format.
z Flexible signal group management.
z Fully integrated and synchronized with other verdi views.
z Interactive visual comparison of waveforms.
z Built-in logic analyzer and event searching.
z Capable of displaying analog waveforms.

nWave – Fast Signal Database (FSDB) File
z Compact binary file format which contains the simulation signal data.
z Captured during simulation using PLI system tasks for both VHDL and
VERILOG.
z Advantages:
z Smaller in size than VCD.
z Loads faster than VCD.
z Open file format so other vendor tools can dump data, Verisity,
Vera, Ikos, etc.

nWave – Brief Overview of Object File Linking
z In general, use LD_LIBRARY_PATH to point to pre-compiled PLI

shared object files, but simulator and platform dependent.
z All pre-compiled PLI shared object files are found in the software release
tree
z $verdi_HOME/share/PLI/<simulator>/<platform>
z Nearly all simulators supported, MTI, NC, VCS, etc.
z Standard PLI source files also available for further customization.

nWave – System Tasks to Dump VHDL to FSDB File
z fsdbDumpfile - Specify FSDB file name.

z fsdbDumpvars - Dump the specified instances and nets.
z fsdbDumpvarsToFile - Dump scope/depth from a designated file.
z fsdbDumpon - Turn on FSDB dumping.
z fsdbDumpoff - Turn off FSDB dumping.
z fsdbSwitchDumpFile - Switch dumping to another FSDB file.
z fsdbAutoSwitchDumpfile - Limit FSDB file size and switch dumping to new
FSDB file automatically.
z fsdbDumpMem - Dump the contents of specified memories.
Note: You must link your VHDL simulator before you can use the
above system tasks. See Command Reference.

nWave – System Tasks to Dump Verilog to FSDB File
z $fsdbDumpvars - Dump the specified instances and nets.

z $fsdbDumpfile - Specify FSDB file name.
z $fsdbDumpon - Turn on FSDB dumping.
z $fsdbDumpoff - Turn off FSDB dumping.
z $fsdbSwitchDumpFile - Switch dumping to another FSDB file.
z $fsdbAutoSwitchDumpfile - Limit FSDB file size and switch dumping to new
FSDB file automatically.
z $fsdbDumpflush - Force to dump result to FSDB file.
z $fsdbDumpMem - Dump the contents of specified memories.
z $fsdbDumpStrength - Dump the strength of signals.
z $fsdbDumpvarsToFile - Dump scope/depth from a designated file.
Note: You must link your Verilog simulator before you can use the
above system tasks. See Command Reference.

nWave – FSDB Utilities
z vfast
z Command line conversion of VCD files.
z fsdbextract
z Extract signals, scopes, time periods from existing fsdb files
without re-simulating.
z fsdbmerge
z Merge several fsdb files into one.
z fsdbreport
z Generates a report of value changes for specified signals.
Note: Use <utility> -h for a list of all options or see the Command
Reference for more information.

nWave – Invoke nWave and Load FSDB File
z To open nWave from nTrace, click on the New Waveform icon

or Tools Æ New Waveform.
z Use File Æ Open or toolbar icon to open simulation results file.
z On the verdi command line use the option
-ssf <filename>.fsdb
z Load VCD files generated by $dumpvars.
z VCD files are automatically converted to FSDB at load time.
z Open several files in the same window.
z Use File Æ Set Active... to specify which file is active.
z Open several files in different nWave windows.
z Use Window Æ Change to Primary to specify which window is active.

nWave – Adding Signals
z Recommended method:
z Drag & Drop signals/instances from other windows to nWave.
z All instance I/O.
z Selected signal(s).
z Signals in text region.
z Schematic hierarchical blocks or logic gates
z Other methods:
z Use Signal Æ Get Signals... or toolbar icon
z Select signals and use RMB Add Signal(s) to Wave in nTrace.
z Select objects and use RMB Add Select Set To Wave in nSchema.
z After executing a trace command in nSchema, use Trace Æ Add
Result to Wave.

nWave – Get Signals Form
z Directly Form Bus based on user-defined rules. Sub-block information of selected

block in hierarchy browser
z Option to Find Signals in full scope.
z Option to display signals
in order of selection not
alphabetical.
z Signal type filter.
Use wildcard *,? to get

all matched signals

nWave – Group Operations
z Use RMB menu in signal window to:

z Add Group
z Rename Group name
z View Æ Go To Group… or RMB Go to Group <Select Group name> jumps to
specified group.
z Expand / collapse group member by double clicking.

nWave – Hierarchical Groups
z Invoke RMB Æ Insert Subgroup to create sub-groups of selected groups

z Each group/sub-group can be renamed with RMB Æ Rename
z Invoke View Æ Group Manager… to open the Group Manager form
z Select a group in Group Manager form and click New Subgroup to add a new
group under the selected group.
z Click the Move To button to
move the selected group/signals
in nWave into the selected group
in the Group Manager
z Delete the selected group and
subgroups

nWave – Aliasing
z Use –autoalias command line option for automatic mnemonic recognition for
‘defines and parameters.
z Use Waveform Æ Signal
Value Radix Æ Browse Alias
to create an alias file and
apply to a signal.
z Apply color to alias
z Create a copy of a signal and
use RMB in value column
to Remove Local Alias.

nWave – Add Comment
z Use Signal Æ Comment or RMB menu in signal window to insert a comment

field at cursor position.
z Four comment box types provided: box, attached box, period and arrow period.

nWave – Bus Operations
z Invoke Signal Æ Edit Bus or RMB menu in signal

window to edit selected bus.
z Create bus from selected signals.
z Invoke Signal Æ Create Bus or RMB menu
in signal window.
z Add Logic 0 or Logic 1 as place holders.
z Set radix and signal value notation.
z Waveform Æ Signal Value Radix Æ
Binary, Octal, Hexadecimal, Decimal,
ASCII, Alias
z Waveform Æ Signal Value Notation Æ
Unsigned, Signed 2's Complement,
Signed 1's Complement
z Expand / Collapse bus by double clicking.

nWave – Display Options
z View Æ Hierarchical Name to display hierarchy

before signals
z View Æ Values at Cursor/Marker to display
cursor and marker values simultaneously.
z View Æ Leading Zeros to display leading zeros
z View Æ Grid … to display grid lines on
rising/falling edges and a grid count.

nWave – Preferences
zUse Tools Æ Preferences… to customize waveform display.

(Settings saved in novas.rc)
z General: Display input/output signals
in different colors,
synchronize file browser, etc.
z View Options: Enable highlight
signal, radix display, value
and signal alignment.
z Value System: Change appearance
based on values and
strengths.
z Color / Font / Pattern: Change
appearance of windows and signal
types.
z Default Value: Change signal height
and spacing. Change default time unit.
z Extended VCD: Change appearance
based on values and strengths.
nWave – Search Value
z Use Waveform Æ Set Search Value… to search signal values.

z Search value accepts mnemonics, wild cards and transitions
z Use Waveform Æ Set Search Constraint… to constrain search to a duration

of time or nth occurrence of a condition.

nWave – Markers
z Use Waveform Æ Marker to name and place markers.

z Multiple markers supported.
z Use distinct labels to differentiate markers Jump to markers
from tool bar
Double-click marker label

to change/delete
Labels always visible at

the top of waveform window
nWave – Logical Operation
z Use Signal Æ Logical Operation... to create a new signal from other signals.

nWave – Complex Event
z Use Signal Æ Event to define and name events.

z Events are signal value combinations or complex sequences of single events.
z Double clicking on Event Name or Expression will invoke edit mode.

nWave – Complex Event Waveform
z Display captured event on waveform.

nWave – Split Window
z Use Window Æ Horizontal Split to split window.

z Use Window Æ Stop Split to go back.

nWave – Print
z File Æ Print... command to print out what you see in the window with a
PostScript printer.
z Select to print to file or to printer.
z Support print selected signals or displayed signals.
Stretch signals to
fill whole page.

nWave – Save and Restore Signals
z Use File Æ Save Signals to save all waveform objects including:

z Signals
z Comments
z Color settings
z Markers and labels
z Logical operations
z Events
z Created Buses
z Restore the signals saved

in a previous session
z In nWave, use File Æ Restore Signals
z On the command line, use –sswr <file>.rc
Note: If there is a file open in nWave, the Restore Signals command will not
overwrite the loaded simulation results.

nWave – Additional Commands
z Logical Operations
z Signal Æ Logical Operation...
z Logic analyzer functions (Complex Events)
z Signal Æ Event
z Shift the time of selected signals.
z Waveform Æ Waveform Time Æ Shift Individual Signal
Time…
z Create independently scrollable signal frames.
z Window Æ Horizontal Split
z Aliasing
z Waveform Æ Signal Value Radix Æ Browse Alias

nWave – Summary

z Understand the nWave functionality.
z Be able to open an FSDB file and add signals to the waveform display.
z Know how to create buses and search for a particular value.
z Be able to add markers, comments, aliases and logical operations.
z Know how to compare simulation results.
z Know how to view the analog waveform

nWave – Wrap-up
z Questions?

the nWave LAB

Training Course


Debugging With Verdi
z Alternate Ways to View Simulation Data

z Active Annotation
z State Annotation
z Complex Signal Browser
z Watch, Memory or MDA Windows
z Isolate Logic Relevant to a Specific Simulation Time
z Active Trace
z Trace X
z Post Process Simulation Data
z List X
z Save Debug Environment
z Lab

Active Annotation
z Display simulation results on source or schematic.

z Source Æ Active Annotation in nTrace
z Schematic Æ Active Annotation in nSchema.
z Signal values / transitions are
synchronized with cursor time.

Active Annotation – Stepping through Time
z Select signal(s) in the source or schematic window and go to next or

previous transitions .
z The transition is selectable between: Any Change , Rising or
Falling .
z In nTrace, search for the previous/next transition for all signals in the
selected statement.
z The above commands will move the cursor time in all windows.

Complex Signal Browser
z Dedicated browser for visualizing complex signals

z What are complex signals?
z SystemVerilog struct
z MDAs
z VHDL record type signals
z Invoke the browser from nTrace, nSchema, or nWave
z Tools Æ Browse Structure Signal…
z RMB Æ Browse Structure Signal… (nTrace only)

Hierarchy Signal Tree Window
Value Annotation
Hierarchy Scope Tree

Window
Source Code Window

Signal List Window
Options Form
z General
z Multiple Complex Signal Browser windows can be invoked.
z D&D is supported between Complex Signal Browser and other
windows.
z Hierarchical Scope Window
z Same as nTrace but without package nodes
z Signal List Window
z Supports regular expression in search window
z Complex signals will be shown with Red color
z Signals are sorted alphabetically
z Two options Match Case and Show Structure Signal Only in Option
form will be applied to this window.

z Hierarchical Signal Tree Window

z The signal tree will be built when selecting a signal in Signal List
Window
z Settings for Source Æ Signal Value Radix and Source Æ Signal
Value Notation in nTrace will be applied to this window.
z If an FSDB is loaded, the annotation value will be shown for all leaf
nodes.
z The Value Annotation Window will be closed if Show Annotation Value
option is turned off in the Option form.
z The annotated value will change according to current time point.
z Source Code Window
z Enabled/disabled with the Show Source Definition and Declaration
option in the Option form.

Watch Signal
z From nTrace, use Tools Æ Watch Signal to view the value of selected
signals in a table.

Active Trace from Waveform
z Double clicking on a signal transition in the waveform window will identify

ONLY the active driving statements(s) in nTrace causing that transition.
The active driving statement
Double click to
invoke Active Trace

Active Trace in Source
z Used to identify the active driver for the selected signal.

z Requires design and simulation results.
z Select signal in nTrace.
z Invoke RMB menu and select Active Trace.
z Ctrl-t also performs an Active Trace.
z Use Tools Æ Preferences, Source Code tab, Miscellaneous tab, to enable Double
Click do Active Trace.
The active driving statement

Trace X
z Display logic cone relevant to the unknown.

z In nWave, select a signal.
z Place a cursor at the transition to X.
z Invoke Tools Æ Trace X.
z Generates a flattened
schematic that shows
the X propagation path
back to first storage
element or primary
input.
z In resulting nSchema,
Trace Æ Trace X.
z Repeat as needed.

List X
z Two common causes of X’s:

z Timing violations
z Un-initialized storage elements
verdi can help to isolate storage elements and tri-state devices with unknowns.
z In nWave or nTrace, use Tools Æ List X.
z Build: parses fsdb file to find storage elements and tri-state devices which have
value X.
z A batch build executable called xloc is supported.
z Play: to list storage elements and tri-state devices which have value X at selected
time.
z Double click on a signal in the list or press Trace X icon to generate a
flattened schematic (Trace X functionality).

List X / Trace X Example
Specify time range

to locate X’s Specify path from file
Double click on signal

to invoke Trace X

Start Interactive Mode
z Confirm the PLI/FLI shared object files provided by verdi are linked with your
simulator.
z Choose the simulator under Tools Æ Preferences Æ Simulation tab.
z Be sure to select stop at time 0.
z To enable interactive mode select
Tools Æ Interactive Mode.
z This adds a new toolbar and
Simulation and Debug menu
options to nTrace.
Interactive
Toolbar

Interactive Simulator Control
z Click the Run/Continue icon to start simulator.

z Click the Stop icon to stop simulator.
z Run the simulator to specified time by entering a value in the
Time text field.
z Use Simulation Æ Reset to reset simulator.
z Use Simulation Æ Finish to finish simulation.
z Use Simulation Æ Kill Simulator Process to kill the simulator
process.

Other Interactive Control Options
z Execute Verilog or VHDL step by step.

z Enable Active Annotation for real time updates.
z Use Debug Æ Breakpoints to set and control breakpoints.
z Double click on the line number in source window to set/clear a breakpoint.
z Use Debug Æ Set Focus to focus on a scope(s).
z If a focus is set, the source window will only step through the source code that is
in the focus modules.
z Use Debug Æ User-Defined Commands
to bring up the user-defined commands
window for frequently used commands.

Save/Restore Debug Environment
z Save the debugging status to a session file

z In nTrace, File Æ Save Session...
z Information saved:
z Displayed waveforms and settings.
z All the windows, locations and content.
z Recover the previous debugging status from a session file.

z In nTrace, File Æ Restore Session...
z On the command line, use –ssr <file>.ses

Summary

z Be able to enable active annotation and debug a simulation
problem with active trace.
z Apply the simulation result to nState
z Know how to load an SDF file, annotate values and calculate
longest/shortest paths.
z Be able to use different techniques to isolate logic for active fan-
ins, bus contention and X detection.
z Know how to save a debug session for future use.

Wrap-up
z Questions?
z Take 20 minutes to complete the Debug with

Verdi LAB

If you have problems…
z Contact support with the following information

z Complete description of the problem and what you were doing
z verdi or nLint version
z Platform and OS version
z Simulator and version (if simulation problem)
z Core stack (if applicable)
z verdiLog directory (at a minimum the verdi.cmd)
z Support contact:
z <name>
z <email>
z <phone>

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Verdi

Basic Training & Technical Overview

Based on Verdi 5.4v6

z Verdi Background and Overview

Verdi 5.4 Basic Training -02/22/05

ESL RTL Gate

Do you know how much time your

What else could you be doing with 10

Source: Novas Customer Survey, 161 Respondents

Verdi 5.4 Basic Training -02/22/05

Verdi 5.4 Basic Training -02/22/05

Knowledge sharing Reusner g g

Increasing automation Verdi

Powerful comprehension and debug Debussy

Verdi 5.4 Basic Training -02/22/05

Comprehensive Debug System - More Than Simple Visualization

Current process involves comparing events, code and structure

Verdi 5.4 Basic Training -02/22/05

Utilizing behavior based debug to automate time consuming aspects of

z Time and structure in single view

Verdi 5.4 Basic Training -02/22/05

z Captures design structure and behavior.

Verdi 5.4 Basic Training -02/22/05

z Verdi Background and Overview

Verdi 5.4 Basic Training -02/22/05

Verdi 5.4 Basic Training -02/22/05

z Add binary to the search path.

Verdi 5.4 Basic Training -02/22/05

z The setup file for Verdi is called novas.rc and contains:

z Specify path for Verdi setup file

z Map a library logical name to a physical location in the novas.rc

z Why are symbol libraries important?

Verdi 5.4 Basic Training -02/22/05

z Automatic (recommend) - If the .lib files of Synopsys are available

Verdi 5.4 Basic Training -02/22/05

z Use common delimiters between libraries and paths.

Verdi 5.4 Basic Training -02/22/05

z Compile once, load many times.

Verdi 5.4 Basic Training -02/22/05

vericom [Verdi options] [<your verilog options>]

Verdi 5.4 Basic Training -02/22/05

vhdlcom [verdi options] [<your vhdl options>]

Verdi 5.4 Basic Training -02/22/05

verdi [general options]...

Verdi 5.4 Basic Training -02/22/05

verdi -lib <pre-compiled source> -top <top level>

z Reference pre-compiled source on the command line.

Verdi 5.4 Basic Training -02/22/05

verdi [verdi options] [<your verilog options>]

Verdi 5.4 Basic Training -02/22/05

z Specify library mapping before importing design.

Verdi 5.4 Basic Training -02/22/05

z Use File Æ Import Design...

Note: The imported design does

Verdi 5.4 Basic Training -02/22/05

z File Æ Compile Design

Options GUI will

Verdi 5.4 Basic Training -02/22/05

z At this time you should:

Verdi 5.4 Basic Training -02/22/05

z Verdi Background and Overview

Verdi 5.4 Basic Training -02/22/05

z Left Mouse Button(LMB)

z Displays source code and hierarchy