Aspect Computer Architecture Computer Organization

It defines the attributes, functionality, and organization of It focuses on the actual implementation and
Definition a computer system at a high level. operational features of the computer system.
Level of
Abstraction High-level design and conceptual representation. Low-level design and implementation details.
Concerned with the design and organization of various Concerned with how these components are
components, like the CPU, memory hierarchy, and I/O interconnected and function together
Concerns subsystem. efficiently.
Deals with the instruction set architecture (ISA) and the Deals with the physical components, data paths,
Scope overall system design. control signals, and their interactions.
Defines the interface between software and hardware, Focuses on optimizing hardware components
Goal ensuring compatibility and programmer-friendly features. for efficient data flow and execution.
Pipelining, cache design, memory hierarchy, and
Examples RISC vs. CISC, SIMD vs. MIMD architectures. bus organization.
Impact on Influences the potential for software optimization and Directly impacts the execution speed, power
Performance compatibility. consumption, and resource utilization.
Concerned with Logical design, instruction set design, addressing modes. Physical design, data paths, control unit design.
Decides how to implement the architecture
Determines the instruction set, addressing modes, and effectively, including data paths and control
Design Decisions overall system organization. units.

Aspect Von Neumann Architecture Harvard Architecture

Instruction and Data Single memory for both data and
Memory instructions. Separate memory for data and instructions.
Instructions and data are fetched from Instructions and data are fetched from
the same memory, which can lead to different memories, reducing the possibility
Memory Access data hazards. of data hazards.
Instructions and data share the same bus Separate buses for instructions and data
Program Execution for transfer between memory and CPU. transfer, allowing parallelism.
Can fetch multiple instructions
simultaneously due to separate memory and
Instruction Fetch Fetches one instruction at a time. buses.
More complex due to the need for separate
Complexity Simpler to design and implement. memory spaces and buses.
Commonly used in most general-purpose Often used in embedded systems and DSPs
Typical Use Cases computers. (Digital Signal Processors).
Slower execution due to potential data Faster execution due to reduced data hazards
Speed hazards and single memory access. and parallelism.
Improved performance and reduced data
Advantages Simplicity and flexibility in programming. access conflicts.
Limited parallelism and potentially
Disadvantages slower execution. Increased hardware complexity and cost.

Architecture Description Advantages Disadvantages

Stack In this architecture, operations typically 1. Simple and compact 1. Limited parallelism due to
Architecture involve operands at the top of a stack. The instruction format. stack-based operations.
top of the stack is implied as a default source
Architecture Description Advantages Disadvantages
or destination for operations.
2. Efficient for nested
subroutine calls and 2. Slower random access to
function returns. data not on the stack.
An accumulator-based architecture has one
primary register (the accumulator) that is
often implicit for many operations. Other 1. Limited parallelism due to
Accumulator operands are loaded from and stored to 1. Compact instruction reliance on a single
Architecture memory or other registers. encoding. accumulator.
2. Easier to implement in 2. Multiple memory accesses
hardware and memory- are required for many
efficient. instructions.
In this architecture, most operations involve
Register- two registers, where both source and 1. High potential for
Register destination registers are explicitly specified in parallelism as multiple 1. More complex instruction
Architecture the instruction. registers are available. encoding and decoding.
2. Efficient for data- 2. May require more
intensive applications and registers, which increases
optimizing compilers. hardware complexity.
In this architecture, operations involve one
register and one memory location. One
Register- operand is usually loaded from memory, and 1. Efficient use of memory 1. Increased complexity for
Memory the result is stored either in a register or back hierarchy, balancing speed handling memory access,
Architecture to memory. and capacity. leading to potential latency.
2. Well-suited for general- 2. Additional overhead for
purpose computing with a memory access instructions,
mix of register and potentially slowing down the
memory operations. program.