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    This document contains a logic design assignment from the College of Computer Science at a university in Saudi Arabia. The assignment includes 10 multiple choice questions testing concepts like K-map minimization, register storage capacity, latch operation, Boolean function description, finite state machine diagrams, synchronous sequential circuit design using always blocks, delay definition in Verilog, and full adder register usage. The student is asked to select the correct answer for each question and fill in a table with their responses.

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    Assignment-202021-BB (1)

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    This document contains a logic design assignment from the College of Computer Science at a university in Saudi Arabia. The assignment includes 10 multiple choice questions testing concepts like K-map minimization, register storage capacity, latch operation, Boolean function description, finite state machine diagrams, synchronous sequential circuit design using always blocks, delay definition in Verilog, and full adder register usage. The student is asked to select the correct answer for each question and fill in a table with their responses.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    4 views5 pages

    Assignment 202021 BB

    Uploaded by

    difivig351
    This document contains a logic design assignment from the College of Computer Science at a university in Saudi Arabia. The assignment includes 10 multiple choice questions testing concepts like K-map minimization, register storage capacity, latch operation, Boolean function description, finite state machine diagrams, synchronous sequential circuit design using always blocks, delay definition in Verilog, and full adder register usage. The student is asked to select the correct answer for each question and fill in a table with their responses.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 5

    ‫المملكة العربية السعودية‬

    Kingdom of Saudi Arabia


    ‫وزارة التعليم العالي‬
    Ministry of Higher Education
    ‫كلية الحاسب‬
    College of Computer
    ‫قسم تقـنـــيـــــة المعلومات‬
    IT Department
    Course: Logic Design (COE121) Lecturer: Dr Shabana Habib

    1st Semester 1442/1443 Assignment-2

    Choose the correct answer and insert your answer in the given table. E.g Q.1--A

    Questions Correct option


    1.
    2.
    3.
    4
    5
    6
    7
    8
    9
    10
    Q1. Use K-map to minimize equations in sum-of products form

    A. Y = AC + ABD + ABC + BD
    ̅D
    B. Y = A + C + B ̅
    ̅C + A
    C. Y = A ̅ BD + AB̅C̅ + C̅B
    ̅
    ̅ BC + A
    D. Y = CD + A ̅ BD + AB ̅C̅ + B
    ̅D̅

    Q2. The storage capacity of a register makes it an important type of memory. .


    ‫المملكة العربية السعودية‬
    Kingdom of Saudi Arabia
    ‫وزارة التعليم العالي‬
    Ministry of Higher Education
    ‫كلية الحاسب‬
    College of Computer
    ‫قسم تقـنـــيـــــة المعلومات‬
    IT Department
    Course: Logic Design (COE121) Lecturer: Dr Shabana Habib

    1st Semester 1442/1443 Assignment-2

    A. True

    B. False

    Q3. Using k-map find expression of the following circuit

    A. x’ + z’
    B. x’ + y’z’+ yz’
    C. x + x’y
    D. 1

    Q.4 Latches are tristate devices whose state normally depends on asynchronous inputs.
    A. True

    B. False
    ‫المملكة العربية السعودية‬
    Kingdom of Saudi Arabia
    ‫وزارة التعليم العالي‬
    Ministry of Higher Education
    ‫كلية الحاسب‬
    College of Computer
    ‫قسم تقـنـــيـــــة المعلومات‬
    IT Department
    Course: Logic Design (COE121) Lecturer: Dr Shabana Habib

    1st Semester 1442/1443 Assignment-2

    Q5) What is the correct behavioral description of a module that computes the Boolean
    function?

    Y(ab) = ~a & ~b | ~a & b | a & b

    A.

    B.

    C.

    Q6) The output of ‘(a^b)|c’ and ‘a^b|c’ statements will be same in Verilog.
    ‫المملكة العربية السعودية‬
    Kingdom of Saudi Arabia
    ‫وزارة التعليم العالي‬
    Ministry of Higher Education
    ‫كلية الحاسب‬
    College of Computer
    ‫قسم تقـنـــيـــــة المعلومات‬
    IT Department
    Course: Logic Design (COE121) Lecturer: Dr Shabana Habib

    1st Semester 1442/1443 Assignment-2

    A. True
    B. False
    C. Neither Yes nor NO

    Q7. The state table of a D-Flip Flops is shown, Find the complete FSM diagram

    A.
    ‫المملكة العربية السعودية‬
    Kingdom of Saudi Arabia
    ‫وزارة التعليم العالي‬
    Ministry of Higher Education
    ‫كلية الحاسب‬
    College of Computer
    ‫قسم تقـنـــيـــــة المعلومات‬
    IT Department
    Course: Logic Design (COE121) Lecturer: Dr Shabana Habib

    1st Semester 1442/1443 Assignment-2

    B.

    C.

    Q8 To design syncronus sequential circuit what type of ‘always@()’ block can be used:
    A. always@(posedge clk)
    B. always@(clk)
    C. both of them
    Q 9. What is the correct way to define delay in Verilog:
    A. assign (#2) n1 = a & b & c;
    B. assign #2 n1 = a & b & c;
    C. assign (2) n1 = a & b & c;
    D. none of them

    Q10.Full adder results are typically stored in registers

    A. True

    B. False

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