Electrical Enginerring Lab II

Addis Ababa University
Addis Ababa Institute of Technology

Electrical Engineering Lab II [ Eceg – 2205] Electrical & Computer Engineering Department
Experiment
Basic Measurement
1
Course Number: Eceg 2205
Course Title: Electrical Engineering Lab II
1. Objective: To study and repeat different basic measurements
2. Equipment:
1 Variable DC power supply
1 Oscilloscope with X and Y-input
1 function generator
1 multimeter
3. Components:
1 capacitor 100nF
1 capacitor 1nF
1 resistor 100kohms
1 resistor 10kohms
1 resistor 1kohms
1 resistor 10 ohms
1 decade resistor 0...100kohms
4. Theory
4.1 Voltage measurements
4.1.1 Using oscilloscope(CRO)
To measure the AC component of a signal, display the waveform over the

largest portion of the screen. Multiply the number of divisions between the
desired points by the setting of the amplitude control. Make sure that the
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variable control is in the calibrated position.To measure the DC level of a

signal, set the input switch of the signal input connector to the ground
position; position the trace to a line appropriate for the polarity and amplitude
of the signal to be measured. Once this reference line has been established, do
not change this position control. Set the input switch to the DC positon.
Measure the desired level from the ground reference.
4.1.2 Using multimeter, electronic voltmeter

Starting with the range of smallest sensitivity select the range of highest
sensitivity without exceeding the final point of the scale by the pointer.
Whenever you use multimeter, take into consideration that the internal
resistance of the meter (it is indicated on the meter) will cause some error.
Hence use electronic voltmeter(which has a relatively higher internal
resistance) if necessary.
4.2 Time measurements

4.2.1 Using oscilloscope(CRO)
To measure the time interval between two points on a signal waveform,
multiply the distance between the points in divisions by the setting of the
sweep time/div in the calibrated position.
4.2.2 Using counter

A frequency counter can be used also for time measurements but only for
measuring the time period of a signal (which is the inverse of the frequency). It
is not possible to measure the time between two arbitrarily chosen points of a
curve like on a CRO display. The counter gives always the highest accuracy
with regards to frequency and period.
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4.3 Frequency measurement

The simplest way to determine frequency is, if possible, to read the setting of
the frequency generator. The accuracy of such a reading is however
comparably low for conventional generators.
4.3.1 Using CRO

a) Uisng Time Interval Method: Measuring the time interval between
corresponding points on the consecutive cycles of a signal waveform and taking
its reciprocal gives the frequency of the signal.
b) Lissajous Figures: This method is used to determine the ratio between the
frequencies of a known and unknown frequency signals. Supply the known
frequency to the horizontal input and the unknown frequency to the vertical
input to get an oscillogram of loops called a Lissajous pattern. The ratio of
number of loops tangent to the horizontal to those tangent to the vertical
determines the ratio of the frequencies between the vertical and horizontal
input signals.
Example: Figure 1 shows a sample pattern for a frequency ratio between
vertical and horizontal signals of 2 to 1.
Number of Horizontal Tangent Points (HT): 2
Number of Vertical Tangent Points (VT) :
f v VT = f H VT
Where :
fv = frequency to the Vertical input

fH= frequency to the Horizontal input
VT= Number of Vertical Tangent Points
HT= Number of Horizontal Tangent Points
Fig.1 Lissajous figure for a frequency ratio fv:fh=2:1
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4.3.2 Using frequency counters
The frequency can be red directly. Make sure that the input switch is in the
position for the right input voltage.
4.4 Phase measurement

Apart from special phase measuring devices, the CRO is used for such a
measurement.
a) Time interval measurement: Measure the distance between two
corresponding points on the input and output waveforms of the phase shifting
circuit (assuming a dual trace CRO is used) in divisions. Dividing this amount
by the distance of one period in divisions and multiply the result by 360o. It
gives you the phase shift.
b) Lissajous figures: When two signals of the same frequency are supplied
separately from the vertical and horizontal inputs of a CRO, the resulting
Lissajous pattern is a tilted ellipse. Normally the reference signal is applied to
the horizontal, and the phase shift is determined from certain ratios of
measurements on the elliptic display (refer to a previous experiment on the
CRO On Lab I ).
4.5 Current measurements

4.5.1 Using multimeters
Multimeters and similar devices can be used for current (and also for voltage)
measurements under the following conditions only:
• the current is a DC or the frequency is within the rated range of the
measuring device.
• in the case of AC values the waveform has to be harmonic (sinusoidal)
Using such devices select the range as described in 4.1.2.
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4.5.2 Using CRO

CROs are able to measure voltages only. In order to measure current, include
a resistance as small as possible (to avoid affecting the circuit) into the current
path and measure the voltage drop on the added resistance. Take into
consideration that the ground terminal of the CRO must be connected always
to the ground point of the circuit. This is also true for most of the VTVMs.
Current measurement using the CRO will usually be less accurate because, the
measurement depends on how accurately we know the resistance of the added
resistance.
Input Output
Ri Ro
Ei Eo
Figure 3: Thevenin’s Equivalent of a two-port network
In most practical cases the emf (electromotive force) Ei can be assumed to be

zero. To determine Ri, Ro, and Eo additional resistors R1 and R2 have to be
included.
Circuit
External
voltage V3 V4
V1 V2
source
Figure 4: Measurement set up to determine Ri, Ro and Eo
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V2
Ri = R1
V1−V 2
Eo = V 3
V 3−V 4
Ro = R 2
V4
R1(R2) should be in the same range as Ri(Ro) to obtain best results.

Example:
If V2=0.5V1 then Ri=R1
If V4=0.5V3 then Ro=R2
make sure that R2 does not overload the circuit
4.7 Measurement of gain and frequency response

The gain is defined as the ratio A=.Vo/Vi. Make sure that there is not any
distortion on the output while you determine the gain at a certain frequency.
The frequency response, which is a function of frequency [A(f)], is defined as

the complex gain (gain and phase ) versus the frequency. Make sure that the
input voltage remains constant for the whole measuring and that there is no
distortion of the output waveform at any frequency. Fig.5 gives a survey of the
possible connections of measuring equipment for investigating the frequency
response.
For plotting the gain and the phase versus frequency, the use of semi-log or
log-log paper is very common
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Y1
Circuit Y2 CRO
Vo GND
Vi V
V
Figure 5: Connection of equipment for determination of

frequency response of a circuit.
5. Preparation
5.1 Calculate the DC value across R1, R2 and R3 in fig .6.

5.2 Calculate the minimum internal resistance of the meter if an error of
atmost 1% is allowed for the measurements in 5.1.
5.3 Calculate and compare the actual voltage across R3 and the measured one
if you use a meter with sensitivity of 10 kohms /V in the range:
a) 10V ( full deflection ) and,
b) 100V ( full deflection )
5.4 Derive the formula for the frequency response of the circuit, i.e, Vo/Vi in
phasor form, in fig.6 by neglecting R3 and R4 (open circuit for R3 and short
circuit for R4).
5.5 Clarify for yourself how to use semi-log or log-log papers. State the
advantages and the application of such graph papers.
5.6 Plot the curves for the gain A = f(f) and the phase ϕ = f(f) for the circuit in
fig.6 on a semilog format for the frequency range f=100 Hz ... 100 k Hz using
the formulas obtained in 5.4.
5.7 Calculate Ri at the frequency f1=100Hz and f2=1kHz for
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a) output short circuit by neglecting R4

b) output open circuit by neglecting R3 and R4
6. Procedure
6.1 Connect the circuit shown in fig.6.
V1
R3 V1=10V(DC)
R2 R1=1kΩ
R2=10 kΩ
C1 R R3=100kΩ
Vi C2 Vo R4=1Ω
R4 C1=100nF
C2=1nF
Figure 6: Circuit for basic measurements
6.2 Do not supply any AC input. Determine the DC voltages across R1, R2,
and R3 with a/an:
a) Multimeter
b) CRO
Now supply additionally a sinusoidal input of 1Vpp and 5 kHz and repeat the
measurings.
6.3 Supply a sinusoidal input of 1kHz,10Vpp and measure the current through
R1 with the CRO. Take R4 as the small resistance to get the corresponding
voltage.
Now supply a square wave of 1kHz, 10Vpp and repeat the measurements. Plot
the waveform obtained by measuring with the CRO.
6.4 Measure the rise and fall times at the output, supplying a square wave
input of 10 Vpp, 1kHz.
Note: Rise time and fall time are defined as the time intervals between the
points of 10 % and 90% of the peak value.
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6.5 Plot the frequency response of the circuit ( gain and phase ) for f = 100 Hz
... 100kHz. on the paper you have prepared.
6.6 Determine the frequency for the maximum gain with
a) reading the scale of the generator

b) CRO
use a sinusoidal input and chose a convenient voltage.
6.7 Determine the input resistance Rii and the output resistance Rio of fig 6
6. Evaluation
7.1 Describe the effect of supplying an additional AC input in 6.2.

7.2 compare the results for sinusoidal and square wave input . Is it possible to
use conventional multimeter with AC ranges for measuring the current at 1kHz
/sinusoidal 1kHz/ square wave? Explain your answer.
7.3 compare the calculated and measured curves in 5.6 and 6.5 and give
reasons for differences.
7.4 compare the results in 5.6 and explain differences.
Explain any observations you made.
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Experiment
Semiconductor Diode
2 Characteristics
1. Objectives
(1) To determine the V-I characteristics of a junction diode;
(2) To verify the Boltzmann diode equation experimentally;
(3) To observe an oscillogram of the characteristics of a zener diode.
2. Materials Required
Power sources: low-voltage dc power supply, AC power supply.

Equipment: DC current meter, dual- channel oscilloscope.
Component: Two 1N4001 rectifier diodes, zener diode.
Resistors: ¼-watt, 4.7-ohm, 39-ohm, 180-ohm, +5%; decade resistance box.
3. Theory
Semiconductor materials have conductivity lying between those of insulators
(10-9 Siemens / m) and conductors (108 Siemens / m). Germanium and
silicon, the two most important semiconductors used in electronic devices,
have conductivities of 2.2 x 10-4 and 4.4 x 10-8 Siemens / m, respectively in the
pure state at 300 k. These conductivities are too low for the materials to be of
practical importance in their chemically pure form. They are, however, heavily
dependent on the kind and amount of impurities, chemically pure or intrinsic
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germanium doped with 0.001% arsenic for instance showing a 17,600-fold

increase in conductivity.
The mechanism of electrical conduction in semiconductors is as follows. Like

all Group IV elements, germanium (Ge) and silicon (Si) have four valence
electrons and a diamond-like crystal structure in which each atom shares its
valence electrons with four neighboring atoms. The electron pair shared by
any two such atoms forms a covalent bond which provinces the force binding
them in the crystal structure. This also results in the valence electrons being
tightly bound to the nuclei of these atoms. Covalent bonds can be broken only
if an electron receives sufficient energy such as heat from an extemal source.
An electron which has broken a covalent bond is said to be free and is available
for electrical conduction. An electron which has escaped from its parent atom
leaves a positively charged ion behind, the broken bond being known as a hole
Although the positive ion is not free to move within the semiconductor, the
position of the hole can change if an electron from a nearby atom broke a bond
to come and fill it. The positive charge which can now be ascribed to the hole is
seen to move in the direction of the newly broken bond. Thus, free holes just
as much as free electrons are responsible for current flow in a semiconductor,
the two types of current being additive.
At 3000 k thermal ionisation affects only 1 atom in 1.8x109 for Ge and 1 in 3.3
x 1012 for Si and the electron-hole concentration obtained is not important for
electrical conduction. The required conductivities are obtained by adding
predetermined amounts of impurities from either Group III or Group V. Atoms
of Group III element such as boron (B), gallium (Ga) and indium (In) have only
three valence electrons so that when one such atom substitutes a Ge of Si
atom in the crystal structure, one of the four covalent bonds will be incomplete.
Thus each impurity atom introduces a hole into the semiconductor. Since the
impurity concentration normally far exceeds the charge density arising from
thermal ionisation, electrical conduction in such a semiconductor is largely due

to positive charge carriers. The semiconductor is now p-type and holes are
known as the majority carriers, while free electrons, which are due to thermal
ionisation are known as minority carriers since they are in the minority.
Impurity atoms from group III are known as acceptor impurities since they will
accept free electrons to fill the incomplete covalent bonds introduced by them.
Atoms of Group v elements such as phosphorous (P), arsenic (As) and

antimony (Sb) have five valence electrons, one of which is not needed for the
covalent bonds when these atoms substitute the atoms in the semiconduc or
crystal. Consequently, one electron per impurity atom will be loosely bound to
the nucleus and all such atoms are fully ionised at ordinary temperatures. The
resulting electrons are available for electrical conduction and constitute the
majority carriers, while holes due to thermal ionisation are in the minority.
The semiconductor is now n-type and the group v atoms are known as donor
impurities since they donate electrons for electrical conduction. See Fig. 1 (a)
and (b)
Fig 1 a) P-type Semiconductor a) N-type Semiconductor
Semiconductors are doped or alloyed with p-type or n-type impurities as the

crystal is grown during the manufacturing process. When a p-type and n-type
semiconductor are grown in the same crystal, a p-n junction is formed and a
semiconductor diode is obtained. The characteristics of such a diode can be
explained as follows. Being appositely charged the holes on the p-side and the

electrons on the n-side of the junction are attracted toward the junction where
they neutrals each ether and are lost as current carriers.
As electrons and holes diffuse across the junction in this way, immobile
positive ions are being created on the n-side and negative ions on the p-side of
the junction. Thus a potential barrier, (or contact potential), builds up which
opposes the further diffusion of charge carriers across the junction. The
immediate vicinity of the junction which is deficient of free charge carriers is
known as the depletion or transition region. In a step-graded junction, where
the doping changes abruptly from p-type to n-type, the thickness of this region
is of the order of 0.5µm, and the contact potential of the order of a few tenths of
a volt. (See Fig. 2.)
Fig.2 P-N Junction
When reverse bias is applied to the p-n junction, holes on the p-side and
electrons on the n-side are forced to move away from the junction. The
depletion region widens and the barrier potential increases. Only a very small
revere saturation current flows because of minority carriers which cross the
junction from either side. This saturation current is so called because it is
independent of the magnitude of the reverse bias. However, its magnitude is

highly temperature dependent since the minority carrier concentration is

governed by the operating temperature.
When forward bias is applied to the junction, the electric field set up in the
transition region supplies the energy which enables the majority carriers on
either side to overcome the potential barrier. The potential barrier is therefore
effectively reduced and the extent of the depletion region decreases. The
forward current increases exponentially as the forward bias voltage is
increased. Note that the majority carriers become minority carriers once they
cross the junction and enter the region in which they are in the minority.
The theoretical equation which describes the V-I characteristics of the junction
diode is the Botzmann’s Ideal Diode Equation given in (1) below:
[
i = Is exp( v ηVT ) − 1]
. × 10− 23 J / K :Boltzmann's Constant
where, VT = KT q and K = 138
(1)
q = 1.602 × 10-19 C: Charge of an electron
T = Temp. in K
where Is, the reverse saturation current is of the order of 1uA for Ge diodes and
1nA for Si diodes, and VT = KT/q is 252 mV at 20oc (= 293ok). At this
temperature the above equation may be written in the from:
[
i = Is exp( 40v η) − 1 ] η >1 (2)
where theoretically η=1 for both Ge and Si, but is introduced here to account
for the deviation of the characteristics of practical junction diodes from that of
the idealized junction diode. The forward current is lower than that given by
Eqn. (1) due to the voltage drops in the bulk resistance of the p and n regions.
This particularly noticeable in silicon devices. The deviation in the reverse
region is due to leakage currents and the breakdown phenomena which
become important at large reverse bias voltages. The circuit symbol and typical
V-I characteristics for the junction diode are shown in fig. 3 (a) and (b). Vγ in

the characteistics curve is the bias voltage for which the forward current is 1%
of the maximum rated value, and is known as the cut- in voltage. This varies
from 0.2 to 0.5V for Ge and from 0.4 to 0.8V for Si diodes.
Rectifier Diode
Zener Diode
Fig 3 Junction Diode characteristics
It should be remembered that there is a limit both to the forward bias and
reverse bias voltages which may be placed across the diode. If either one is
increased beyond the value recommended by the manufacturer, a sharp
increase in current may permanently damage the device.
The low forward resistance and high reverse resistance of the semiconductor
diode make it ideally suited for applications such as in rectification, detection,
switching, holding, etc., while special purpose diodes perform a variety of
operations voltage regulation, voltage reference, tuning, transient suppression,
etc. Only rectifier diodes and voltage regulator diodes will be examined in this
experiment.
Voltage regulator diodes (also called zener diode) utilize the process of zener
breakdown to bring about a sharp increase in reverse current at some reverse
bias voltage determined at the time of production of the device. When this
reverse voltage is placed across the diode the field set up in the depletion

region is strong enough to pull electrons out of their covalent bonds, causing a
sudden increase in the reverse current. A similar effect is obtained in
avalanche breakdown, when the field is strong enough to accelerate the
primary electrons to cause secondary ionization by collision with neutral atoms
in the transition region. The Zener diode characteristic and circuit model for a
semiconductor diode are shown in fig. 4 .
Fig 4 Zener Diode Charactrersics.
The dynamic or a-c resistance, rf is obtained by differentiating i with respect to

v in Eqn. (2) and taking the reciprocal.
The equation
25η
rf = (3)
i
gives rf in ohms when i is in mA. η can be determined experimentally from a
plot of log I vs. V, while Is is given by the intercept of the same plot on the
vertical axis. Note also that η is numerically equal to the a-c resistance at i =

25 mA. rr is the revere resistance of the diode and rz the a-c resistance of the
zener diode in the breakdown region.
4. Procedure
A. Determination of Static Characteristics

100Ω
A
A
Id
Vs V
A K
(a) (b)
Fig 5
1. The polarity of the IN4001 rectifier diode and the circuit to be used in the
determination of its static characteristics are shown in Fig. 5 (a) and (b).
Use the ohmmeter of your multimeter to verify the terminals A and K,
recording the forward and reverse resistance as you do so. It should be kept
in mind, however, that the resistance thus measured depend on the current
flowing in either direction as the ohms battery of the meter is placed across
the diode. Different meters and even different ranges of the same meter
cause different currents to flow through the device.
2. Connect the circuit of Fig. 5 (a) and have it checked by the instructor before
applying power.
3. Increase E very slowly and record the VTVM readings for forward currents of
1.0, 2, 3, 4, 6, 10, 16, 25, 40, 60, 80, mA, 0.10, 0.16, 0.25, 0.40, 0.60 and
0.80A. Do not exceed 1A under any circumstances.

4. Reduce E to zero, and reverse the diode terminals only in the circuit. The
diode is now reverse biased. Record the current for reverse bias voltages of
2, 4, 6, 8, and 10V using a suitable µA range.
B Observation of Oscillogram of Zener Diode Characteristics
D1 B R1
A D2 C R2 E
+ D3
es R3 F
- R4
G
Fig 7
1. Set up the circuit of Fig. 7 using the two diodes for D1 and D2 and the zener
diode for D3 R1 = 4.7 ohms, R2 = 39 ohms, R3 = 180 ohms, and R4 =1 ohm..
es is the a-c source.
2. Have the circuit checked and energized the circuit with es in its minimum
range. Observe and record the waveform of es (vAg ) and vAE with the
oscilloscope in the d-c mode.
3. Set the CRO in the x-y mode, connecting point F to the Y-input and point E
to the x-input, while point G is grounded. Both X-and Y-inputs should be
in the d-c input position. Have the circuit checked and increase es to 4 vrms.

4. Set the X-scale on 1v/div, the Y-scale on 20mv/div and sketch the complete
display.
5. Now set the X-scale on 0.1v/div, the Y-scale on 10mv/div, center the
positive part of the display and plot on millimeter paper using enough
points.
6. Now put the X-scale back to 1v/div, the Y-scale to 20 mV/div.and set es at 6
vrms and sketch the complete display. Since R4 =1 ohm, the vertical scale in
mV gives the diode current in mA directly. Thus the display is essentially
the V-I characteristics of the zener diode.
7. Finally, expand the y- scale to 10 mV/div and sketch the negative part of
the zener diode characteristic.
5. Discussion
The IN4001 is rated at IF (AV) =1.00A, and the zener diode has the ratings Vz
=6.2v +5% at 1 mA, and IFRM =IZRM =250mA.
1. Plot the static V-I characteristics for the rectifier diode, using suitable scales
for the forward and reverse directions. Develop the d-c equivalent circuit of
Fig. 4(a), clearly labeling with the values of rf, vγ and rr.
2. For the circuit of Fig. 6 draw the d-c load line corresponding to Esmax.
Determine the operating point graphically and compare it with the result
obtained from part B of the procedure.

3. Use the ohmmeter measurements of rdc and rr in part A to estimate the

corresponding currents through the diode. Is it possible to obtain unique
values of rdc and rr with such measurements?
4. Make a semilog plot of your data in part A to estimate the values of Is and η
and substitute in Eqn.(2). Compare your estimate of Is with the reverse
current measured in part A. How does your estimate of η compare with the
value of rf at i= 25mA? What does the value of η tell you about the bulk
resistance of the diode? Does this resistance depend on the current
through the diode? How does your conclusion compare with the implication
of Eqn. (3) ?
5. The oscillogram of part C of the procedure is not exactly the static v-I
characteristic of the zener diode. It is only the dynamic characteristic for a
load resistance of 1 ohm. Obtain the former graphically from the later. How
closely do the two resemble one another? Use the static characteristics and
the ratings given earlier to develop the piece-wise linear model of Fig. 4(b).
You are to use the experimental value of Vz for this model. How does this
value compare with the diode rating?
6. Discuss any other significant observations.

6. Data Sheet





Experiment
3 Regulated DC Power Supply

1. Objectives:
To test a dc power supply circuit with an RC-filter
2. Equipment:
1 tapped transformer ( Leybold power supply )
1 oscilloscope
1 multimeter
1 µA multimeter or electronic voltmeter
1 decade resistance
3. Theory:
Electronic devices and most of the circuits and systems incorporating them
require direct voltage sources for their proper biasing and operation. In most
instances, however, it is impractical to use batteries as the source of this
power. Since most power distribution systems are ac in nature, the most
common frequencies being 50, 60, and 400 Hz, a process of converting this ac
power to the desired dc form must be employed. This is carried out in two
steps: Rectification and Filtering. Rectification converts the zero dc
component current or voltage to a current or voltage with a non-zero dc
component. Filtering removes all or most of the remaining ac components of

the rectified current or voltage. For many applications, this dc output should
also be regulated. Regulation helps the output to remains constant even
when the supply line voltage or the load resistance varies.
While the conversion of large amounts of power from ac to dc usually

necessitates the use of three phase or other poly-phase sources, moderate or
small power requirements such as in most electronic equipment can be met
from a single phase source. In this laboratory exercise discussion will be
limited to a single phase source although much of the material can be applied
to other types.
A. Half-wave and Full-wave Rectification
Rectifier circuits utilise diodes which act as the switches connecting the source
to the load whenever the anodes are positive with respect to the cathodes, and
disconnecting the source from the load whenever the anodes are negative with
respect to the cathodes. The two circuits in fig.1&2 depict a half-wave and a
full-wave rectifier. In both circuits the transformer is used to step the power
line voltage up or down to the required value.
ei
eL
Eim
ELm
eS ei eL RL
t
T t
T
(a) (b) (c)
Fig 1: (a) input waveform

(b) half-wave rectifier circuit
(c) output waveform

In the half-wave rectifier circuit current flows only when ei is positive, so that
the voltage across the load consists of half-sinusoid pulses repeating every
period of the input voltage. See fig.1(c). If the diode is assumed to be ideal or
to have a linear characteristic with a forward dc resistance rf , eL can be
described by the Fourier series:
E L , max  π 2 2 
eL = 1 + sin ω t − cos 2ω t − cos 4ω t + .... (1)
π  2 3 15 
The first term on the right is the dc component, the remaining terms
representing unwanted ripple, since the ac components merely produce heat
losses in the transformer windings and the load without contributing to the dc.
The efficiency with which the ac is converted to dc is measu
red by the efficiency of rectification, which is defined as the ratio of the dc
power delivered to the load to the total power furnished by the source. Since
the effective value of the load current is IL = Im / 2 and since its dc component
or average value is Idc = Im / π.
Idc 2 RL 4 RL
ηR = 2 x100% = 2 x100% ≤ 40.5% (2)
IL ( R L + R f ) π RL + Rf
The theoretical maximum value is 40.5% when an ideal diode is used.
A measure of the smoothness of the rectified output, known as the ripple

factor , γ, is defined as the ratio of the effective value, Iac, of the ac ripple to the
dc component, Idc.
Iac ( IL − Idc )
1/ 2
 IL  2 
1/ 2 1/ 2
2 2
π 2 
γ = = =   − 1 = − 1 = 121
. (3)
Idc Idc  Idc    4 
It is seen that Iac=1.21Idc. This excessive content of ripple limits the use of the
half-wave rectifier circuit. Another disadvantage of this circuit is the tendency
of the unidirectional current in the transformer secondary to cause dc
magnetisation and saturation of the core, making the use of large, expensive
transformers necessary. A related measure of performance in this regard is the
transformer utilisation.( read on this)

The full-wave rectifier eliminates the core magnetisation characteristic of the

half-wave rectifier circuit since it uses a centre-tapped transformer secondary
and two diodes which conduct in opposite directions during alternate half-
cycles of the input voltage. Current flow in the load is in the same direction
during both half-cycles and the half-sinusoid voltage pulses across it repeat
every half period of the power-line voltage, as shown in fig.2(b). The Fourier
series expansion of eL is:
2 E L , max  2 2 
eL = 1 − cos 2ω t − cos 4ω t − .... (4)
π  3 15 
Since Idc = 2Im/π and IL = 0.707Im, it can be shown that:

8 RL
ηR = × 100% ≤ 811%
.
π 2
RL + rf
1/ 2 (5)
π 2 
γ = − 1 = 0.48
 8 
which show that full-wave rectification is more effective than half-wave
rectification.
It is to be noted, however, that only one half of the secondary winding carries
current during any half cycle since only one diode is forward at any instant. A
smaller, less expensive transformer would be needed if the same section of the
secondary could be used to carry current alternately in both directions.
ei
eL
Eim +
eL ELm
ei +
eS RL
+
t ei
T t
T
(a)
(b) (c)
Fig2: (a) input waveform

(b) full-wave rectifier circuit
(c) output waveform

A rectifier circuit which uses the transformer windings more efficiently in this
way is the bridge rectifier shown in fig.3. Since bridge rectifiers can also be
obtained as single four-terminal devices, the saving in cost and economy of
space obtained makes their use more attractive. For analysis, consider the half
cycle in which point ‘x’ is positive with respect to point ‘y’. Diode D1 and D3 are
forward-biased and conduct through RL causing a positive voltage pulse eL.
During the next half cycle, D2 and D4 are forward-biased causing an identical
voltage pulse eL, so that the waveform of fig.2(b) is obtained.
+
D2 eL + D1
eS ei
D3 D4
Fig. 3 Bridge rectifier circuit
Although the full-wave rectifier output is an improvement over that of the half-
wave rectifier circuit, the smoothness of the dc voltage or current thus obtained
is far from satisfactory for most applications without the use of filter circuits.
B. Filtering and Filtering Circuits
Filter circuits are combinations of R, L and C elements which improve the

rectification efficiency and reduce the ripple factor of the rectifier circuit. The
series elements present a high impedance while the shunt elements present a
low impedance to the ac components, the converse being true for the dc
component. In this way the ripple content of the load current can be made as
small as required for any desired application.

Filter circuits may be as simple as an inductor in series or a capacitor in shunt

with RL. The inductor stores magnetic energy when the load current tends to
rise above the average value and releases that energy to the load when the
current tends to fall below the average, thus reducing the average ripple. The
capacitor is charged when the input voltage exceeds the capacitor voltage
causing the diode to conduct. when the input falls below the capacitor voltage,
the diode is reverse-biased and the capacitor discharges through RL, again
reducing the ac ripple. While the above simple filters are satisfactory for some
applications, multiple L-section or π-section networks have to be employed for
more effective filtering. See fig.4.
L L
C RL RL C
(a) (b) (c)
L L1 L2 R
C1 C2 C1 C2 C1 C2
(d) (e) θ2
(f)
Fig. 4 (a) capacitor filter (d) π-section filter
(b) inductor input filter (e) two-section inductor input filter
(c) L-section (LC) filter (f) RC-π-section filter
Inductors with large inductance values at power line frequencies are relatively
expensive, large and heavy components. Where only moderate currents and
voltages are required, some or all of the inductors in the filter networks can be
replaced by resistors. This results in an increase of the ripple factor and the
internal resistance of the power supply, but there is the possibility of reducing

the ripple by increasing the capacitance or by adding more RC-sections while

making sure that the correct output voltage is obtained.
In this laboratory exercise the performance of a bridge rectifier and π-type RC-
filter circuit will be examined. (See fig.5).
R1 eL
+ i2 + ELm
from
i1
bridge e2
e1 RL
rectifier
C1 C2
ωt
θ1 θ2 π π+θ1 2π 3π
(f
fig. 5 π-section RC filter fig. 6 load voltage waveform under capacitor filter
The filtering action of C1 can be studied by removing C2 from the circuit. The
effective value of load resistance is RL’ =R1 + RL. Since two diodes conduct in
series during any one half-cycle, the peak value of e1 with C1 disconnected can
be determined from:
E1m =E im RL’/(RL’+2rf) (6)

When C1 is connected across RL’, the former charges through 2rf as long as ei
>e1 (between θ1 and θ2) and discharges through RL’ as soon as ei < e1 (between
θ2 and θ1+π). See fig.6. If rfC1<< T and RL‘C1 >>T, it can be shown that e1
alternates almost linearly between
e1(θ2)=E1m
e1(θ2)=E1m (1 - T/2RL’C1) e1(teta1)

The peak-to-peak ripple voltage is therefore
E1r = e1(θ2)-e1(θ1) = E1m T /2RL’C1,
and its effective value, since it is a saw tooth waveform, is:
Elac= Elr /(2√3) = ElmT/4√3RL’C1 (7)
The average value, or DC component, of e1 is:
Eldc= [e1(θ2) + e1(θ1)] / 2 = Elm (1- T/4RL’C1) (8)
From equation (7) and (8) , the ripple factor becomes:
γ1 = Elac/Eldc = Elac/ Elm = T / 4√3RL’C1 (9)
Since id = iCl + il = iCl + iRL’, it can be shown that:
id = ωC1Elmcosωt + (Elm / RL’) sinωt

or
id = Elm [ ( 1 + ω2R’L2C12)1/2/RL’] sin(ωt + Φ) for θ1 < ωt < θ2,
where φ = tan-1(ωRL’C1). The peak diode current is evaluated at ωt = θ1, where
 4 R ′LC1 − T 
θ 1 = sin −1  
 4 R ′LC1 + T 
So that:
Idm = ωClElmsin (θ1 +φ) (10)

when (ωClRL’)2 >> 1, which is generally true for good design.

The effect of connecting C2 across RL is to divert most of the ripple current
flowing through R1.
If R1 >> 1 / 2ωC2 and RL >> 1 / 2ωC2, where 2ω is the ripple frequency, it can
be shown that the ripple content of e2 is given by:
γ 2 = γ 1 2ωC 2( R1|| RL)
or (11)
γ 2 = π 4 3 ω 2 R1 RLC1C 2
Foir a power lne frequency of 50 Hz, γ1 and γ2 are given by,

γ1 = 2.90/R’LC1 (12)
and γ2 = 4.60 / R1RLC1C2
where resistances are in kΩ and capacitances are in µF.
(10) and (12) show that while increasing C1 and C2 reduces the ripple factor,
increasing C1 may lead to a dangerously high peak diode current. In designing
a capacitor-input filter, therefore, care should be exercised to ensure that Idm
does not exceed the rated peak forward current. Otherwise, a surge resistor
may have to be connected in series with the diode. For modern silicon diodes,
the rated peak repetitive current varies from about 5 to 15 times the rated
average or dc current.
At the instant when ei = Eim sin wt = -Eim and D1 and D3 are reverse biased, ei
= Elm and the total voltage across D1 and D3 is ei-e1 = Eim - Elm = 2 Eim.
Hence, the peak inverse voltage (PIV) across either diode is Eim, and care
should be taken that the rated PIV of the diode is chosen greater than Eim.
C. Voltage Regulation
The output of a DC power supply can fluctuate with the line voltage or change
with the load current due to the voltage drop in its internal resistance. In

many application such fluctuations are undesirable and it becomes necessary

to provide a circuit for regulating the output voltage. A shunt regulator circuit
employing a zener diode is shown in fig.7(a).
ROZ
R0 R0
+ I2 + I2 +
I1 I1 IZ rZ
E1m IZ RL E2 E1m RL E2
C1
- VZ
- -
(a) (b)
Fig. 7 (a) Zener diode shunt regulator circuit
(b) DC equivalent circuit
The breakdown characteristics of the diode is such that its voltage is almost
independent of the reverse current. Thus, if E1m should increase, the diode
current, Iz, and hence Ildc, increase causing the voltage drop IldcRo to rise. The
increase in E1m appears almost entirely across RO and E2dc is stabilised.
Similarly, if I2dc should decrease due to increase in RL, IZ increases sufficiently
for Ildc, and hence E2dc = (E1m - IldcRO) to remain essentially constant. If E1m
should decrease or RL should be reduced causing increased I2, Iz decreases and
E2dc is again held essentially constant.
Fig .1(b) is an equivalent circuit for that in fig 1(a), assuming the regulator
diode is properly biased in the zener region. Since E2dc = Vz + Izrz and E1m = (Iz
+ I2dc) Ro + E2dc, one can write:
rz Rorz Ro
E 2 dc = E 1m − I 2 dc + Vz (13)
Ro + rz Ro + rz Ro + rz
The output resistance, Roz, is given by:
∂E 2 dc Rorz
Roz = = (14)
∂I 2 dc Ro + rz
The regulation factor, F, is defined as:

∂E 2 dc rz
F= = (15)
∂E 1m Ro + rz
and is the fraction by which changes in E2dc are reduced as compared to

changes in E1m or ∆E2dc=F∆E1m . Thus, regulation should reduce the effect of
line voltage variations as well as ripple at the output. Since Roz < Ro and E2dc =
E1m - (Iz + I2dc )Ro, variations in E2dc due to changes in RL, and hence I2dc, should
be lower. Besides, load regulation is more effective if Iz > I2dc. This, however,
leads to large power dissipation in Ro as well as in the diode itself. This results
in poor efficiency. Another shortcoming of the zener voltage regulator is that,
the output voltage cannot be chosen at will, but must be made to correspond to
available diode breakdown voltages. These being the major disadvantages of
this simple type of voltage regulator, more complex circuits are used for higher
efficiency and better regulation. Such regulators are commercially available in
the form of ICs and are characterised by their regulated output voltage
specification ( viz, 5V, 12V, ...)
4. Preparation
4.1. Explain briefly how to measure the three different values in M1.1 and
M1.1
4.2. What are the differences in the measuring set ups in fig. 7a and 7b?
Under what conditions will each set up be preferable?
A A
v V
R R
Fig. 8 (a) Fig. 8 (b)

4.3. Calculate γ1 , γ2 , E1dc, and E2dc for the RC filter in fig. 5, with C1 = C2 =
1000µF, R1 =18 Ohms and RL = 56 Ohms and the rectifier driven from a
6Vrms source.
4.4. Explain how to measure the dc value, the peak value and the ripple voltage
value in fig 1(c) and fig .6.
5. Procedure
Component values:
R1 = 18 ohm R4 = 0.2 ohm
R2 = 1 kohm C1 = 1000 µF
R3 = 56 ohm C2 = 1000µ F
5.1. Rectification
5.1.1 Connect the circuit in fig. 1. Take the Leybold source and apply an ac
voltage of 6 Vrms. Measure the actual output of the source with the
CRO.
5.1.2 Measure the:

output dc component with the multimeter or the electronic voltmeter,
output waveform with the CRO, recording the peak value in the dc
mode, and the ripple voltage Vrpp in the ac mode on the conditions:
a) RL = R3
b) RL = R3; C1 parallel to RL
5.1.3 Display waveform of the current through C1 and the output voltage
together on the CRO. Record the waveforms carefully labelling the peak
value of IC1. Use R4 as the small resistance to be added for current
measurement.

5.1.4 Repeat 5.1.3 with C1 doubled ( C2 added in parallel to it )
5.1.5 Connect the circuit in fig.2. Use the Leybold source with its centre tap
and repeat 5.1.2 to 5.1.4.
5.2. Filtering
5.2.1 Connect the bridge rectifier circuit using the Leybold source and R1 & R3
in series as a load.
5.2.2 Record the waveform on the screen carefully; notice the frequency.
Measure also the dc component with the meter.
5.2.3 Connect C1 across the series combination of R1 and RL as in fig.5 but do

not connect C2. Record the waveform of e1 and the meter reading of E1dc
and E2dc. Put the CRO in the ac-mode, centre the waveform, magnify it
and sketch carefully.
5.2.4 Connect C2 across RL and note any effect on e1 by measuring the ripple
waveform of e1 and E1dc.
5.2.5 Observe and record the ripple waveform across RL and measure E2dc.
Repeat with C2 disconnected, but with C1 doubled (C1 and C2 in parallel).
5.3 Regulation
5.3.1 Plot the reverse voltage-current characteristics of the zener diode in the
range IZ = 0 .. 200mA
Use the measuring set up of fig. 9
R1 =18 Ω
A
Fig. 9 V

5.3.2 Connect the circuit of fig. 10 using the decade resistance for Rx and the
rest of the values as shown below:
R1 = 18 Ohms R3 = 56 Ohms C1 = C2 = 1000 µF
R2 = 1 k Ohms R4 = 1 Ohms
Set the ammeter in the 100 mA range and the voltmeter in the 10V range.
R2 is needed to limit the maximum value of iz, while R3 is needed to limit
the maximum value of iL. Thus, RL=R2//(R3 + Rx) Set Rx at 54 Ohms.
This should give RL close to 100 Ohms, allowing for the resistance of the
ammeter. Have the circuit checked.
5.3.3. With the zener diode disconnected, record the mA and V readings as well
as the ripple waveforms of e1 and e2.
R1 RX
+ A
~
ei e1 e2 V R2 R3
~
_ C1 R4
Fig. 10 Measurement set up.
5.3.4. Connect the zener diode and record the meter readings and the ripple
waveforms as in 5.3.3. Also measure the waveform of the zener diode
current (voltage across R4)
5.3.5. Observe and record the effect on the ripple waveforms of e1 and e2 of
connecting the other 1000µF capacitor C2 first in parallel with C1 and
then across the zener diode.

5.3.6. Set Rx first to zero and then 1kOhms and record the two mA readings.
5.3.7. Vary Rx while recording the mA readings and the corresponding DC

voltages, E1dc and E2dc for five more current values, preferably equally
spaced, in the above interval.
5.3.8. Record the waveform of e2 without C1 and C2 but with the zener diode
in circuit.
6. Evaluation
6.1 Compare γ1, γ2, E1dc and E2dc measured or calculated from the results of 5.2
with the values calculated in 4.3.
6.2 Explain the significance of the waveforms obtained in 5.1.3 and 5.1.4
relating them with theoretical expectations.
6.2 Discuss the advantages and the disadvantages of doubling C1 and leaving
C2 out as compared to using C1 in conjunction with C2. Justify your
argument both with theory and experimental data.
6.3 Calculate rz from the V-I characteristics of the zener diode.
6.4 For the circuit of fig 10 plot E2dc vs I2dc and use the slope to determine Roz.
Compare with theoretical value.
6.3 Discuss any other important observations.
7. Data Sheet
‡ Check from page 21 to page 25

Experiment
4 Junction Transistor
Characteristics
1. Objective
To Plot the input and characterstics (graphic between the base

current iB and base to emitter voltage VBE, Keeping collector emitter
voltage VCE constant)
To Calculate the input dynamic resistance for the input
characteristics at given operating point
To plot the output characteristics (graph between ic and VCE For
fixed value of iB )
To calculate the Ac resistance (ro), the dc beta (βde) and ac beta at
agiven operating point.
2. Equipment
2 DC power Supply
1 mA range DC ammeter
1 µA range DC ammeter
3. Component
BC 107 or BC 109 BJT transistor or Equivalent

Decade resistor

4. Theory
A bipolar junction transistor has three terminals: emitter (E), base (B) and
collector (C). In BJT the current flowing from E to C (IC) is controlled by
changing voltage drop between B and E, or equivalently by changing current
flowing into B terminal (IB). In the most common circuits the signal current IB is
usually quite small as compared to IC. Hence, BJT-based circuits can be used
to amplify the signal since small input variations (low input power) can produce
large output variation (high output power). Of course the energy is not
generated from nothing inside BJT. The extra power that becomes available at
the output comes from power supply that has to be present in BJT-based
amplifier circuits (actually, power supply has to be present in any amplifier
circuit).
Hence, one can say that VBE or IB controls the amount of energy taken from DC
power supply to change IC. One can recognize common emitter (CE), common
base (CB) and common collector (CC) BJT configurations in circuits depending
on which BJT terminal is grounded (i.e. used as a reference point for the input
and output signals). A BJT gain stage can amplify voltage (CB), current (CC) or
both (CE). In this lab we will use only the CE configuration when the input
voltage is applied between the base and emitter terminals, and the output
voltage is taken at the collector with respect to the ground (emitter).
Internally BJT is three layers of semiconductors of different conductivity types.

For instance, in n-p-n Sibased BJT the emitter is n-type Si, base is p-type Si
and collector is again n-type Si. Hence, inside the BJT there are two pn-
junctions. By applying voltages between terminals, one can bias Base-Emitter
or Base-Collector junctions either in forward or reverse direction. In n-p-n BJT
the positive VBE = VB-VE means forward bias to B-E junction. Forward bias of
the B-E junction lowers the energy barrier for electron injection from Emitter to

Base (Figure 1). Electrons from the Emitter are injected to Base and can diffuse
across the B provided that they are rapidly removed at the B-C junction. For
this purpose the B-C junction is reverse biased, i.e. VBC = VB-VC is negative. In
other words, the positive Collector accepts electrons coming from Emitter
through the Base.
Fig 1 NPN junction
The hole current in n-p-n BJT is unwanted current component and it is

minimized by design of BJT transistor. One manifestation of the hole current is
recombination current in Base, i.e. electrons that came from Emitter recombine
inside the Base with holes that came from Base terminal.
The flux of hole from Base terminal isessentially the base current IB. To make
the base current small as compared to the emitter current, the Base width is
made very small and the acceptor concentration (doping) in the Base is made
much smaller than the donor concentration in the Emitter. Thus, with increase
of the B-E forward bias we get small flux of holes coming from Base (small IB)
and large flux of electrons from Emitter into Collector (large IC). Since IB << IC,
in many cases one can use approximation IC=IE. The ratio of collector and base
currents is the BJT current gain β Usually the current gain is being introduced
for variations of current iB and iC around some preset value IB0 and IC0 – bias
currents.

The symbol of an NPN-BJT transistor is shown in Fig. 1. Since the dependence

of iC on vBE is exponential, the collector current varies drastically as the base-
emitter voltage changes. A small current iB flows into the base terminal
because of vBE variations; usually it is a small fraction of the collector current
iC. We call the ratio of iC to iB the current gain of the transistor that is denoted
by b. The value varies significantly with temperature, and can be different
between two transistors of the same type; see textbooks and/or lecture notes.
The bipolar junction transistor (BJT) has three regions of operation:

1. Cutoff Region: If both base-emitter and base-collector junctions are reverse
biased, the BJT transistor enters the cutoff region. All
terminal currents are extremely small and we say the
transistor is off.
2. Active Region: The base-emitter junction must be forward biased and the
base-collector junction reverse biased to make a BJT
transistor work in the active region. The active region is
desired to design a linear amplifier.
3. Saturation Region: When both the base-emitter and collector-base
junctions are forward biased, the saturation region is entered.

 VBE 
Ic=Is  e nVth −1  (1)
 
 
where IS is the saturation current for the emitter terminal, Vth is the thermal
voltage and n is a fitting parameter whose value is within 1 and 2. At room
temperature (300° K), the thermal voltage is roughly 26 mV. Another
fundamental equation of the bipolar device is
iE = iC +iB (2)

Techno
It will be evident in the course that a very useful parameter is the collector-
colle
base DC forward current gain defined as follows
Ic α
ΒDC= = >>1 (3)
IB 1−α
Ic
Where α is
IE
Input characteristics
In the case of common-emitter configuration, the Emitter Base junction can also be considered
as a forward biased diode, the current
current-voltage characteristicss is similar to that of a diode. The
input characterstics of the common emitter configuration is looks like as fig…
fig…….
….
VBE
I B = I o (e VT
− 1)
The collector-emitter voltage VCE has little effect on IB.

Output characteristics
To measure the output characteristics of Common emitter by keeping the abse

current constatnt and varying the VCC
Active Region:
Recall that the active region requires that the EBJ be forward-biased, and that
the CBJ be reverse-biased.A forward-biased EBJ means that vBE 0.7 V. Thus,
the CBJ will ≈ be reverse-biased as long as vCE > 0.7 V. Note that iC and iB are
related by the ratio β , as long as the BJT isin the active region .We can also
identify the cutoff and saturation regions
Cutoff:
The Emitter base Junction is not forward-biased (sufficiently) if iB=0. Thus the
cutoff region is the particular curve for iB= 0 (i.e., the horizontal axis).
Saturation:
When the EBJ is forward-biased, vBE 0.7 V. Then, the Collector Base Junction
is ≈ reverse-biased for any vCE > 0.7 V. Thus, the saturation region lies to the
left of vCE = 0.7 V.Note that the Collector Base Junction must become forward-
biased by 0.4 V to 0.5 V before the iC=βiB relationship disappears, just as a
diode must be forward-biased by 0.4 V to 0.5 V before appreciable forward
current flows

5. Procedure
A. Measurement of Output characteristics
1) Set up the circuit of Fig..... using Voltmeter for V1 an V2. Use the
decade resistance box for RB and set it 100K. Connect mill
ammeter range ammeter on collector leg. Have the circuit checked
by the instructor.
2) Record the ic Vs VCE for the values of IB = 0, 30, 60, 90, µA. IB is to
be varied primarily by the adjustment of VBB and RB. Care should
be exercised not to exceed the maximum power rating of the given
transistor
B. Measurement of Input characteristics

1) The base or input characteristics are to be obtained for VCE =0,
1.0, 3.5V.
2) For each value of VCE , record IB varying VBE. About 8 points
should be taken for each value VCE. Plot IB vs VBE using suitable
scale. Do not exceed IB = 250µA for VCE =0V. For the other values
of VCE, the maximum value of IB should be taken to be the one
corresponding to IE

6. Data sheet



Experiment
Transistor biasing and
5 operating point stabilisation

1. Objective : To study the techniques of transistor biasing and operating point

stabilisation.
2. Equipment:
1 Regulated power supply 9V DC
1 Oscilloscope
1 Function generator
1 Electronic voltmeter or VTVM
1 Decade resistance
3. Theory
For the normal operation of a transistor, the emitter-base junction has to be

forward biased while the collector-base junction reverse biased. However,
since:
a) there is a wide variation in the characteristics of transistors of the
same type number,
b) the characteristics vary widely with temperature,
these undesirable properties of the transistor may easily lead the circuit
malfunction or failure. A transistor biasing circuit is therefore not considered

properly designed unless the Q-point chosen can also be maintained within
some prescribed limits in the safe operating region.
The safe operating region of the transistor is determined by its voltage, current,
and power ratings. In fig. 1 the boundaries of this region are indicated by
dotted lines on the ic-VCE plane. The maximum values PCMAX and VCEO should
be observed strictly to assure that excessive junction temperature do not
destroy the transistor or render it temporarily useless. The specification ICMAX
is not absolute limit in the sense that the transistor will be destroyed, but
should also be observed as a matter of good practice. The remaining
boundaries of the safe operation region arise from the requirement of having
the transistor biased in the linear region, that is out of the saturation region on
the one hand and the cut-off region on the other. Precisely where, within the
safe operating region, the operating point should be located and how accurately
it should be controlled depends on three main factors:
a) Firstly, the Q-point must be selected and controlled sufficiently to
maintain linear operation, that is ,the amplifier should be prevented
from destroying the signal at any temperature as a result of
saturation of the collector diode or reverse-biasing of the emitter diode
at the maximum of the voltage swings.
b) Secondly, the Q-point must be controlled in such a way that the

transistor dissipation always remains below the maximum allowable
value. This is particularly important in high power circuits where the
collector load may be an inductor or a low value resistor, and in which
an improper bias design may lead to a Q-point shift with temperature
which may end up in thermal run-away. This is a condition of
regenerative heating in which increase in ICQ causes greater heating
of the collector junction and this in turn increases ICQ. The resulting
rapid rise in temperature usually results in destruction of the
transistor.

c) Finally, the Q-point should be controlled in such a way that at least

some of the small-signal transistor parameters are kept reasonably
constant. The transistor parameters depend in a variety of ways on
voltage, current and temperature. By keeping the Q-point fixed in the
IC - VCE plane, as the temperature changes, parameter variations at
least with current and voltage will be avoided, if not with temperature.
This design will also reduce the effects of parameters variations due to
unit replacement from among transistors of the same type.
A DC model useful in the analysis of transistor biasing circuits is shown in fig

3. Because of the shortcomings already mentioned, the transistor
characteristics VBE and ICBO used in this model are not unique. Typical
static input and output characteristics as often appear in data sheets or
transistor manuals are inadequate for bias circuit designs. The usual
approach to transistor circuit design is a combination of both the graphical and
analytical methods. Useful rules of thumb for temperature dependence of VBE
and ICBO for both Ge and Si transistors are:
1) VBE decreases at a rate of about 2.5 mV / 0C, or,

VBE(T2) = VBE (T1) -2.5 x 10-3 ∆T (1)
2) I CBO doubles with each 100C rise in temperature, or,

ICBO(T2) = ICBO(T1)x2 ∆T /10 = ICBO(T1)x(1.072) ∆T
(2)
where ∆T=T2-T1
Eqn.(2) may therefore alternatively be stated by saying that ICBO increases by

about 7.2% for each 0C rise in temperature. Although the rate of increase is
the same for both types of materials, the lower absolute value of ICBO in Si,

typically about 1nA as compared to about 1mA for Ge, enables silicon
transistors to be used upto 150 and 2000C as compared to their Ge
counterparts which are limited to 850 to 1050C.
The dc equivalent circuit of fig .2 may now be used to design the simple biasing
circuit of fig. 3 (a). Under quiescent conditions,
VCC = ICQRC + VCEQ (3a)
for the collector circuit, and,
VCC = IBQRB + VBEQ (3b)
for the base circuit. From Eqn.(3b),
IBQ = (VCC -VBEQ ) / RB (3C)
Since VCC is normally much grater than VBE and VCC and RB are fixed, the
circuit of fig .3(a) is known as a fixed-biasing circuit.
From fig. 2, it is clear that:

ICQ = βIBQ + (β+1)ICBO (4)
Thus, it can be seen that ICQ is greatly affected by changes in β and ICBO,
which, as pointed out earlier, may vary from unit to unit and are also
temperature dependent. The relative stability of biasing circuits is studied
using what are customarily known as stability factors. It can be shown that
ICQ depends on β, VBEQ, and ICBO for any biasing circuit. If VCC is assumed
to be constant, one can write:
ICQ = f (β,VBEQ , ICBO ). (5)
For small changes in β, VBE , and ICBO ,
∂Ic ∂Ic ∂Ic
∆Ic = ∆β + ∆VBE + ∆ICBO
∂β ∂VBE ∂ICBO (6a)
or,
∆IC = Sβ . ∆β + SV . ∆VBE + SI . ∆ICBO (6b)
where,

Sβ = ∂IC / ∂β, SV =∂IC / ∂VBE and SI = ∂IC / ∂ICBO

These stability factors, or S-factors, actually express sensitivity rather than
stability since the stability decreases rather than increasing with the S factors.
From Eqns (3c) and (4), it can be shown for the circuit of fig .3 that:
ICQ = β( VCC - VBEQ ) / RB + (β +1)ICBO (7)

Then,
Sβ = IBQ + ICBO
SV = -β /RB
SI = β + 1
These equations show that while only SV may be minimised by increasing RB,
the circuit of fig. 3(a) offers no means of controlling Sβ and SI. Even the value
of RB cannot be chosen at will since it is determined by VCC and β. The circuit
of fig. 3(a) is in fact the most unstable biasing circuit that can be designed.
(Β+1)IBo
Maximum Dissipitation
Ic(max curve pc(max)
IB βIB
+ + VCB _-
Ic
VCE VBE
-
Fig. 1. Safe operating region Fig. 2. Simplified dc model for an NPN

transistor
IC 1
− AC load line
Rac
IBQ
ICQ
1
− DC load line
Rdc
VCE Q VCC VCE
b) load line on collector characteristics

Fig 3. (a) Fixed biasing circuit
Fig. 4. Self-biasing circuit
Fig 5. Modified self-biasing circuit Fig 6. Equivalent circuit for fig. 5

Fig 8. Circuit of fig. 7 modified to prevent

Fig 7. Another form of a self-biasing circuit ac negative feedback.
The techniques usually employed to achieve operating point stability, or to

keep the point (VCEQ, ICQ ) fixed in the IC -VCE plane, may be classified into two
categories, namely, the stabilisation and compensation techniques. Stabilisation
techniques employ resistive biasing circuits and are mostly used in the low -
signal-level stages of transistor circuits. Compensation techniques, on the
other hand, make use of temperature-sensitive devices such as thermistors,
sensistors, diodes, transistors, etc., to maintain ICQ constant against changes
in temperature and are used in high power stages of transistor circuits where
resistances have be low for good power efficiency. A combination of both
techniques is also used as appropriate.
In this laboratory exercise the stabilisation technique will be used to keep ICQ
sufficiently stable in spite of temperature variations or unit replacement. The

common emitter amplifier is used for illustration as this is also the most
popular and versatile configuration. The reasons for this are high current and
power gains and good stability of output and input impedances with changes in
source and load impedance, respectively. Stabilisation in the circuit of fig. 4 is
achieved through the emitter resistance RE. If ICQ increases for any reason, the
increased voltage drop across RE tends to reduce the forward-biasing voltage
VBEQ and hence IBQ, so that the increase in ICQ is much less than if RE were
zero. The process by which a change in the output is used to control the input
in such a way as to reduce the change in the output is known as negative ,or
degenerative feedback. The circuit of fig. 4 is known as a self biasing circuit.
CE is included in the circuit to prevent degenerative ac feedback through RE.
With CE sufficiently large, RE is effectively bypassed at all frequencies of
interest.
For the base-emitter circuit of fig .4

VCC = IBQRB + VBEQ + IEQ RE (8a)
or,
VCC = IBQ (RB + RE ) + VBEQ + ICQ RE , (8b)
Since IEQ = ICQ + IBQ
Solving Eqn.(4) for IBQ and substituting in Eqn.(8b),

it can be shown that:
β (VCC − VBEQ ) + ( β + 1) ICBO( RB + RE )
ICQ = (9)
RB + ( β + 1) RE
Taking the partial derivatives of ICQ with respect to β ,VBEQ , and ICBO
,respectively one has:

( RB + RE ) ( IBQ + ICBO)
Sβ =
RB + ( β + 1) RE
β
SV = − (10)
RB + ( β + 1) RE
( β + 1) ( RB + RE )
SI =
RB + ( β + 1) RE
Eqns. (10) reduce to Eqns.(7) when RE = 0. By making RE as large as is

practicable the S factors can be reduced greatly below their values for RE=0.
Except in the case of SV, Sβ and SI can also be reduced by making RB as small
as possible. However, a small value of RB conflicts with the requirements of a
high input impedance for the amplifier. A low resistance RB shunts the input
and reduces the gain of the amplifier. In the absence of overriding stability
requirements, it is good practice to have RB >10 hie.
No strict rules can be given for the choice of RE ,but whenever practicable, RE
should be kept as small as possible to avoid unnecessary power losses in this
resistor. Satisfactory design can in many cases be achieved with 0.2RC ≤ RE ≤
0.3RC.
Since IBQ is typically two orders of magnitude less than ICQ, the use of a
common source VCC for the base and collector circuits as in fig. 4 leads to large
values of RB usually hundreds of kilo-ohms. From the standpoint of stability
this is a disadvantage and very often the current limiting resistor is replaced
by the voltage-divider network R1, R2 of fig.5. This arrangement yields an
equivalent value of RB which is at least one order of magnitude less, while at
the same time meeting the high input impedance requirements. The Thevenin
equivalent of the base circuit is shown in fig. 6, where:
VBB = (RB / R1)VCC (11)

and RB = R1 R2 / (R1 + R2 )

The analysis of the circuit of fig. 5 is the same as that of fig. 4 except hat VCC is
replaced by VBB in Eqn. 9. The circuit of fig. 5 is quite flexible since a wide
range of RB values can be obtained using suitable combination of R1 and R2.
Another type of self-biasing circuit is shown in fig. 7 ,where RB is connected
between collector and base rather than between VCC and the base. The
stability improves in two ways:
(a) As VCEQ < VCC and a smaller value of RB is used than in fig. 4.
(b) If ICQ increases for any reason, the Q- point moves up the dc load line
and VCEQ decreases. See fig . 3(b).
IBQ , which is given by:
IBQ = (VCEQ - VBEQ ) / RB (12)
also decreases ,causing ICQ to be stabilised. If ICQ decreases, VCEQ increases,
causing IBQ to increase and ICQ to be stabilise. Like RE in the emitter circuit RB
introduces degeneration by providing a feedback path from the collector to the
base. AC degeneration leading to reduced gain can be prevented by splitting RB
into two parts R1, R2 and connecting a capacitor CB between the junction and
ground. For stability purposes the effective value of RB may be reduced by
connecting a third resistor R3 between base and ground. Alternatively an
emitter resistor RE and a bypass capacitor CE may be included as in fig. 8. The
circuit can have even better stability than that of fig. 5. The chief disadvantage
of this circuit is that an extra capacitor CB has to be used. For this reason ,the
simpler circuit of fig. 5 is generally preferred. The last biasing scheme that will
be discussed is the emitter-biasing circuit of fig. 9. This circuit sets a constant
emitter current rather than base current, in contrast to the circuit of fig. 3 (a)
and offers the best Q-point stability so far, especially if RB is low. For this
circuit,
VEE = IBQ RB + VBEQ + IEQ RE (13)
So that
β (VEE − VBEQ) + ( β + 1) ICBO( RB + RE )
ICQ = (14)
RB + ( β + 1) RE

VEE − VBEQ − ICBO( RB + RE )

or, ICQ = for β>>1
RE + RB β
If =VEE >> [VBEQ-ICBO (RB + RC)] and RE >> RB / β, ICQ=VEE /RE and hence
independent of temperature variation changes in device parameters.
Since Eqn.(14) is identical to Eqn.(9) except that VEE replaces VCC, the S factors
for the circuit of fig. 9 are identical to those in Eqns.(10). If in this case RE
>>RB /β, the S factors become
( RB + RE )
Sβ = ( IBQ + ICBO)
βRB
1
SV = − (15)
RE
( RB + RE )
SI =
RE
The ultimate in operating point stability is achieved if RB << RE, as the S factors
then become:
Sβ = (IBQ + ICBO ) /β
SV = - 1 / RE (16)
and,
SI = 1
A circuit in which Eqns. (16) apply is shown in fig. 10, where RB =0 if the dc
resistance of the transformer secondary is negligible. The chief disadvantage of
this circuit is the requirement of two power supplies, which is generally avoided
in low cost design.
The laboratory exercise that follows will be limited to the application of a design
procedure for a linear small signal amplifier of the type shown in fig. 5.

Although the main factors in the selection of a Q-point have already been given,
practical design requires such detailed information as input and output signal
levels, input and output impedance levels, load and source characteristics,
available power supply, allowable dc current drain of stage, allowable noise and
distortion levels, operating point stability, and cost, weight and size
requirements. After such pertinent information has been obtained, the biasing
circuit should be designed in such a way that the Q-point will not drift outside
of a predetermined locus in the ic-VCE plane. A design technique based on due
consideration of the worst values of the device parameters and the extremes of
temperature to be possibly encountered when using the circuit is known as
extremal analysis.
Fig. 9 Emitter-biasing circuit Fig. 10. Improved emitter-biasing circuit

Suppose it is required to establish a quiescent collector current ICQ and

maintain this between the limits IC1 and IC2, where IC2= IC1 +∆IC. Assume that
β, VBE, and ICBO vary in the ranges β1 < β < β2,VBE1 > VBE > VBE2 and ICO1 < ICBO <
ICO2, respectively, due to production tolerances or temperature variations, or
both.
Replacing VCC by VBB in Eqn.(8a) and noting that IEQ = ICQ and that β>>1, one
has:
VBB = IBQRB +VBEQ + ICQRE (17)
and similarly from Eqn.(4)
IBQ = ICQ /β - ICBO (18)
Using Eqn. (18) in Eqn.(17) and taking the extreme values of β, ICQ, VBEQ and
ICBO ,one can write:
VBB = (IC1 / β1-ICO1 )RB + VBE1 +IC1 RE (19a)
and
VBB =(IC2 /β2-ICO2 )RB + VBE2 + IC2 RE (19b)
where VBB is assumed to remain constant. Subtracting these two equations

and solving for RB, one has:
β 1 β 2 (VBE 2 − VBE 1) + ( IC 2 − IC1) RE
RB = (20a)
( β 2 IC1 − β 1 IC 2) − β 1 β 2( ICO 2 − ICO1)
Defining ICQ = ( IC1 + IC2 ) / 2, β0 = (β1 + β2 )/2, and ∆β = β2 - β1, Eqn. (20a)
becomes:

β 1 β 2 ∆ICRE + ∆VBE
RB = (20b)
ICQ∆β − β 0 ∆IC − β 1 β 2 ∆ICO
where ∆VBE = VBE2 -VBE1 , and ∆ICO = ICO2-ICO1. .For silicon transistors, the term
in ∆ICO is negligible and Eqn. (20b) becomes
β 1 β 2 ∆ICRE + ∆VBE
RB = (20c)
ICQ∆β − β 0 ∆IC
If RB is specified, this equation may be used to determine RE.
Design
The specifications for the amplifier to be designed in this section are as follows:
1.Transistor to be used: BC107B, or BC147B, or equivalent
2.Power source available: VCC = 9.0V
3.Current drain of stage: ICQ = 2.0mA
4.Load impedance: RL =27 kΩ
5.Output capability: VO MAX = 2.0 VP
6.Amplifier should be useable anywhere in Ethiopia.
The transistor ratings and characteristics are given at the end of this section.
For the least possible distortion under large-signal condition, the amplifier will
be designed for symmetrical clipping, that is the Q-point will be located half-
way the ac load line. Then:
VCEQ = ICQRac = VCC - ICQ RDC (21a)

or
ICQ = VCC / ( Rac + R dc ) (21b)

In order to avoid entering the saturation and cut-off regions, a safety margin of
about 0.5V will be allowed at each end of the ac load line. See fig. 11. If VCEQ =
(VCE1+VCE2)/2 and ∆VCE = VCE1-VCE2 ,
VCE2 = V0 MAX + 0.5V
VCEQ = VCE2 + ∆VCE / 2
and, IC1Rac=V0 MAX+0.5V=VCE2
From these it follows that:

VCEQ = V0 MAX + 0.5 + ∆VCE / 2
For the design under consideration,
VCEQ = 2.5 + ∆VCE / 2 (22)
Note that the degree of Q-point stabilisation is determined by the value of ∆VCE.
The smaller the value of ∆VCE is the more stringent is the stability requirement.
On the other hand, ∆VCE cannot be made vary large because of the finite value
of VCC, and hence VCEQ. In fact, for non-zero RE and for a finite value of RL, it is
not difficult to show that VCEQ < VCC / 2 = 4.5V for symmetrical clipping. This
means that ∆VCE < 4.0V. For this design a value of ∆VCE = 2.0V can be allowed.
Then VCEQ =2.5 + 1.0=3.5V.( from Eqn.(22))
From Eqn.(21a) ,
VCEQ = ICQ Rac =3.5V
and
Rac = VCEQ / ICQ = 3.5 / 2.0 = 1.75kΩ
Since
Rac = RC RL /(RC + RL), and RL =27 kΩ
RC = Rac RL / ( RL - Rac )
RC = 1.75 x 27 / (27 - 1.75) =1.87 kΩ
RC=1.8 KΩ (standard value) will be used. Then

Rac = 1.8 x 27 / (1.8 + 27) =1.69 kΩ

From Eqn.(21b)
Rac + Rdc = VCC / ICQ = 4.50 kΩ
Rdc = 4.50 - 1.69 = 2.81 kΩ
Since
Rdc =RC + RE
RE = 2.81 - 1.80 = 1.01 kΩ
RE=1.0 kΩ will be used. Then Rdc = 1.80 +1.0 =2.8 KΩ.

Using Eqn.(21b) again, Rac + Rdc=1.69 + 2.80 = 4.49 KΩ, and
ICQ = 9.0 / 4.49 = 2.00mA
VCEQ = VCC - ICQ Rdc = 9.0 - 2.0 x 2.8 = 3.40V
Since the Q-point moves along the dc load line,
∆VCE = ∆IC. Rdc
So that
∆IC =∆VCE /Rdc =2.0 / 2.80 = 0.71mA.
Hence, the Q-point should be stabilised within the interval
ICQ = 2.00 ± 0.35mA.
Before Eqn.(20c) can be used to complete the design, the extreme value of β
and VBE should be determined. At 25 0c, according to the data sheet,
0.55 ≤ VBE ≤ 0.7V
and
200 ≤ β ≤ 450.
As far as can be determined from information that could be located, the
maximum and minimum temperatures for Ethiopia are 440c (average
maximum for July and August in Afar region) and 10c (average minimum for
December in Harrari region) respectively. Hence the amplifier will be designed
to operate satisfactorily in this range.
The maximum temperature at the collector junction is

TJ MAX =TA MAX + θTPC

where, TA MAX is the maximum ambient temp.
PC is collector power dissipation
Where TA MAX = 44 0C and PC =VCEQ ICQ =3.40 x 2.00 =6.8mW. Using the more
conservative value for the BC107 transistor, that is θT= 0.42 0c /mW, one has
TJ MAX = 44 + 0.42 x 6.80 = 46.90C ≅ 47 0C.
Similarly, the minimum temperature at the collector junction is

TJ MIN = 1.0 + 0.42 x 6.80 =3.90C ≅ 40C.
At TJ MIN = 40c,
∆T = 4 - 25 = -210c, so that from Eqn.(1)
∆VBE1= -2.5 x 10-3∆T = -2.5 x 10-3x 21 = 0.053 V.
Then
VBE1 =0.70 + 0.053 = 0.75V.
At TJ MAX = 470c,
∆T = 47 - 25 = 220c, and
VBE2 = -2.5 x 10-3 x 22= -0.055V,
Hence
VBE2 = 0.55 -0.055 = 0.5 V.
Then,
∆VBE = VBE2 - VBE1 =0.5 -0.75 = -0.25 V.
From the data sheet information for the temperature dependence of β, for each
group, β can be plotted versus temperature. By interpolating for βmin = 200 and
βmax =450, one finds that βmin will be 170 at 40c while βmax will be about 500 at
470c. Hence,

β1= 170 and β2 = 500,

so that
β0=(β1 + β2) / 2 = 335
and
∆β = β2 - β1 =330
Substituting the above value in Eqn.(20c) and remembering RE = 1kΩ,
170 × 500( ∆IC − 0.25)
RB =
( 2 × 330 − 335∆IC )
or
254( ∆IC − 0.25)
RB = (23)
( 197
. − ∆IC )
Where RB is in kΩ when ∆IC is in mA. Eqn.(23) shows that for the transistor
and the value of RE chosen, the shift ∆IC is given by 0.25 < ∆IC <1.97. The
lower limit can be reduced by increasing RE while the upper limit and can be
reduced only if β is high and ∆β is low. Here ∆β > β, and this is usually the case
unless the transistors are to be specially selected.
Before hastening to substitute ∆IC=0.71mA in Eqn.(23), it must be noted that

nothing had been said about Q-point shift due to component tolerances.
Component values come with tolerances and since they may be higher or lower
than their nominal values, the Q-point may likewise shift far out of the
specified locus in the IC-VCE plane. Using 5% resistors for R1, R2, and RE. an
uncertainty of 20 to 30% in ICQ may be expected if ICQRE >3VBEQ. If ICQRE =
2VBEQ, The uncertainty becomes about 40%. Denoting by ∆IC the contribution
to ∆IC of β,VBE, and ICBO, and allowing a margin of 25% for component
tolerances one has:
∆IC = [∆I2C - (25% ICQ) 2 ] 1/2 = (0.712 -0.50 2 ) 1/2 =0.50mA

Using a trial value of ∆IC = 0.48mA in Eqn. (23)
RB = 254 (0.48 - 0.25). = 39.2KΩ.

1.97 - 0.48 )
Neglecting the effect of ICO1 and using IC1 = ICQ - ∆IC / 2 in Eqn.(19a), one has
VBB=IC1 (RE + RB / β1 ) +VBE1 (24)

and
VBB = 1.76 (1 + 39.2 /170) + 0.75 =2.92V
Then
R1 = RB .VCC / VBE
= 39.2 x 9.0 / 2.92
= 121 kΩ
R2 = R1RB /(R1 - RB )
=121 x 39.2 / ( 121 - 39.2)
= 58 .0 kΩ
R1=120 kΩ and R2=56 kΩ will be used.
Then
RB = 120 // 56 = 38.2 kΩ
and
VBB = VCC RB / R1
= 9.0 x 38.2 / 120
= 2.87V.
The expected values of IC1 and IC2 are given by
IC1 = VBB - VBE1 . = 2.87 - 0.75 = 1.73mA
RE + RB/β1 1.0 + 38.2 /170

and
IC1 = VBB - VBE2 . = 2.88 - 0.50 = 2.20mA
RE + RB/β2 1.0 + 38.2 /500
Hence,
ICQ = (IC1 + IC2 ) / 2 = 1.97mA,
and
∆IC =IC2 - IC1 = 0.47mA
so that
ICQ = 1.97 ± 0.47 /2 mA
To determine the contribution of component tolerances to ∆IC. the mean values

β0=335 and VBE=(VBE1 + VBE2 ) / 2 =0.63V will be used. Assuming 5% resistors,
it can be shown that the errors in RB and VBE are 8.0%and 9.4% respectively.
Then letting
ICQ= VBB - VBE

RE + RB /β0 (25)
It can be shown that ICQ = 2.01mA ±13%. Taking the contribution of

component tolerances as ±13%, the earlier value of ICQ modifies to
ICQ =( 1.37 ± 0.47 / 2 )mA ±13%.

That is
ICQ =( 1.97 ± 0.24 ) ± 0.26mA
Ratings And Characteristics for the

Low Frequency NPN Si Transistors
BC107B, BC108B, BC147B and BC148B

Ratings
VCBO = 50 V (BC107,BC147)
VCBO = 30 V (BC108,BC148)
VCEO = 45 V
IC = 100mA
Ptot = 300 mW up to 250c
TJ MAX = 1500c (BC147,BC148), θT = 0.420C/ mW
TJ MAX = 1750c (BC107,BC108), θT = 0.500 C/ mW
Characteristics
VBE = 0.55 - 0.70 V

VCE SAT = 0.12 V (< 0.38 V)
ICBO = 0.2nA (250c)
ICBO = 200nA (1500c)
Temperature dependence of β for A, B, and C group Si transistors :
Group β (representative)
-500c 250c 1000c
A (β : 110 -220) 82 160 210
B (β : 200 - 450) 150 260 360
C (β : 110 -220)* 252 500 270
* C groups are not available for types BC107 and BC147.
Hybrid parameters ( at IC = 2.0mA, VCE =5.0 V, T = 250c )
hie : ( 3.2 - 5.0 )kΩ hre : ( 1.7 - 2.4 ) x 10-4

hfe : ( 250 - 500 ) hoe : ( 22 - 44 ) x 10-6 mho
Note:
For VCE = 3.50V, take:
0.95 hie , 1.1 hre , 0.95 hfe , 1.20hoe
4. Preparation
4.1 Describe the advantage when RE in circuits 4 and 5 is zero and describe
also the disadvantage.
4.2 Design amplifier biasing circuits of the types fig. 4 and 5 for the following
conditions:
VCC = 12V
ICQ = 10mA
RL = 5 kΩ
Design the circuit for symmetrical clipping. Take the BC107 transisor and use
its parameters given on page 15. Do not consider the effect of temperature.
5. Procedure:
The component values to be used are:

R1 = 120 kOhms RL = 27 kOhms
R2 = 56 kOhms C1 = 10µF
Rb = 1 MOhms C2 = 10µF
Rc = 1.8 kOhms CE = 200µF
5.1 Connect the circuit of fig.5 and have it checked by the instructor before
applying power. Set the decade resistance to RE = 1kohms. Now set VCC
= 9.0V. Measure the DC potentials at the collector, base, and emitter
using suitable ranges of the meter.

5.2 Apply a 1.0 kHz signal of 10mV at the input and record the corresponding
value of the output voltage. Now increase Vi slowly until noticeable
distortion at the output results. Record waveforms of both Vi and Vo
properly labelled. Increase Vi further until clipping is observed at either or
both peaks of the output waveforms. Record and label the waveforms of
both Vi and VO with the scope in the DC mode.
5.3 Connect the Volt meter across RE. Read the meter and record the readings
for RE = 0.9, 0.95, 1.00, 1.05, and 1.10 kOhms.
5.4 Disconnect VCC. Remove R1 and R2 and connect the circuit of fig. 4 using
RB. Repeat the procedure of all above paragraphs.
5.5 Now change the transistor and use it in the circuits of both fig 4 and 5.
Repeat 5.1 to 5.3 with the other transistor.
6. Evaluation:
6.1 Calculate ICQ = IEQ for each case in 5.3, 5.4, and 5.5.
6.2 From your DC measurements of the first paragraph of the above procedure
and from the values of the resistors, compute VCEQ, VBEQ , ICQ , IBQ and β,
including the uncertainty estimates in these values.
6.3 The amplifier was designed to handle an output VO MAX = 2.0 VP without
serious distortion. From your results for the second paragraph, would you
say that this objective has been achieved? If not, give the probable cause
and also the maximum output voltage that can be handled without serious

distortion. What happens to the voltage gain as the output increases?

What happens to the input waveform and why? Did the amplifier clip the
output symmetrically? If not, which one occurred first, saturation or cut-
off?
6.4 Discuss any other important points.
7. Data sheet
Check from page 49 to page 51

Experiment
Transistor as an
6 amplifier
1. Objectives:
• To measure hie and hfe for the transistor at a given operating point
• To investigate the gain and impedance characteristics of a transistor
amplifier;
2. Equipment:
1 regulated dc power supply
1 function generator
1 oscilloscope
1 electronic voltmeter
3. Theory
The performance of a transistor amplifier at low frequencies can be analysed
using any of the low-frequency models of the transistor. The T-parameters can
be related more directly to the junction properties of the device. However, it is
more usual to use hybrid parameters because they lend themselves more easily
to direct measurement in a laboratory set up. The defining equations for the
common emitter model are:

ei= hie ib + hre eo

ic = hfe ib + hoeeo (1)
and the circuit is shown in fig.1(c).
The parameters of the circuits of fig.1(b) and (c) are related by the following
approximate equations.
hie = rb + (β +1) re
hfe = βrd / (rd + re)
hre ≈ re / (rd + re) (2)
hoe ≈ 1 / (rd + re)
The amplifier to be tested and its equivalent circuit are given in fig.2(a) and (b),
respectively.
Fig. 1. (a) BJT (b) t-model of the transistor (c) hybrid model of the transistor
Fig.3 Circuit for determination of Ai Fig.4 Circuit for determination of Ro

The equivalent circuit is valid in the frequency range where the coupling and
bypass capacitances
and also the inter-electrode and parasitic wiring capacitances can be assumed
to have negligible effect on amplifier performance.
In fig.2(b),
RB =R1//R2 and Rac =RC // RL
Noting that,
eo= -hfe ib .(Rac // 1/hoe ) (3)
= -ib.hfe Rac /(1+hoeRac)
The expression for ei in Eqn. (1) can be written as

ei= ib [ hie - hre hfe Rac / (1 + hoe Rac)] (4)
Applying KCL to node b in fig.2(b), one can write ib= i1-ei /RB, which can be
used to rewrite Eqn. (4) in the form:
ei= i1. RB //[hie -( hfe hre Rac) / (1 + hoeRac) ]

so that,
Rin = ei / i1 = RB // [hie -(hfe hre Rac) / (1 + hoeRac) ]

(5)
The quantity after the minus sign is negligible in comparison with hie and
Eqn.(5) can be simplified to:
Rin ≈ RB // hie = Rbhie / (RB + hie ) (5a)

Using Eqns.(3) and (4), the expressions for the voltage gain of the amplifier
becomes:
AV = eo / ei = -hfe Rac /[hie + (hie hoe - hfehre)Rac] (6)
This can be approximated by writing,
AV ≈ -hfe Rac / hie (6a)
since the quantity after the plus sign is also negligible compared to hie.
To derive an expression for the current gain, fig.2(b) is redrawn in fig.3 with a
slight modification.
Since i1 = ei /R in and iL = eo / RL, the current gain becomes:
Ai = iL / i1 = (eo / ei )( Rin / RL)

or,
Ai=AV .Rin / RL
On substitution from Eqns (5) and (6) and simplification, one has:
Rac RB
Ai = − hfe
RL ( RB + hie)(1 + hoeRac) − hfehreRac
which can be approximated to a high degree of accuracy by, (7)
hfeRacRB hfeRcRB
Ai = − =−
RL ( RB + hie) ( RL + RC )( RB + hie)
To derive an expression for the output resistance, the source is replaced by its
internal resistance RS and a generator ex is made to replace RL. See fig.4. One
can see that:

i2=hfeib + e2 /(RC // 1/hoe )

or
i2=hfe ib + e2 (1 + hoe RC) / RC (8)
and that
hre e2 = - ib [ hie + RS // RB] (9)

= - ib (hie + RS’ )
Eliminating ib between Eqns.(8) and (9), one has
i2 = e2 .[1/RC + hoe - hfe hre / (hie + RS’ ) ]

So that
e2 (hie + Rs' ) Rc
Ro = = (10)
i 2 hie + (1 + hoeRC ) Rs'+(hiehoe − hfehre ) Rc
This expression shows that RO is slightly dependent RS. If RC is small, that is

RC<<1/hoe,
Eqn. (10) can be simplified to:
RO ≈ RC / (1 + hoeRC ) ≈RC (10a)

without great loss of accuracy.
Examination of Eqns 5(a), 6(a), 7(a) and 10(a) shows that, for most practical
purposes, the transistor can be characterised by the two parameters hie and hfe
at low frequencies. Since parameters vary greatly even for the same group of
transistors, often by as much as a factor of two, there is no practical advantage
in employing the more complex expressions for Rin, AV ,Ai,
and RO.

Sometimes it may be desirable to know the voltage gain of the amplifier in

terms of the open-circuit source voltage eS. Since:
ei = eSRin / (RS + Rin)
eo ei eo Rin
Avs = = = Av (11)
es es ei Rs + Rin
where Rin and AV are as derived earlier.
In this experiment the amplifier of fig.2(a) will be analysed using

Eqns.5(a),6(a),7(a) and 10(a)
after which the predictions are checked by direct measurement of the four
quantities. To make this effort worthwhile hie and hfe for the particular
transistor will be measured at its operating point, since typical values obtained
from transistor manuals cannot be sufficiently precise.
A simple circuit which enables a quick but sufficiently accurate determination

of hie and hfe is shown in fig.5(a). The applicable equivalent circuit is given in
fig.5(b). Since both hie and hfe are short-circuit parameters, that is RC = 0, this
condition will be approximated by making RC<<1/hoe. Since:
ei RB / / hie hie hie

= ≈ ≈
es Rs + RB / / hie Rs + hie Rs
one has:
ei
hie = Rs, if Rs / / RB >> hie (12)
es
Similarly,
io≈-hfeib ≈ -hfei1 ≈ -hfe (eS / RS)
and

io= e0 / RC ,
One has,
hfe= -(e0/eS)(RS/RC), If RB>>hie, (13)
where the minus sign appears because eo and eS are out of phase. Thus hie
and hfe are determined easily from measurements of eS, ei, eo and the values of
RS and RC subject to the indicated simplifying assumptions, that is RC <<1/hoe
and RB // RS>>hie.
It should be mentioned that, although in principle possible, a simple set-up as

in fig.5(a) will not yield measurable results for the determination of hre and hoe.
A much more elaborate set-up is required.
Fig. 5 (a) circuit for determination of hie and hfe (b) approximate equivalent circuit

Fig. 6 Practical circuit for the determination of hie and hfe.
4. Preparation:
4.1 Explain how to determine the input and output resistances of an amplifier.
4.2 Calculate in the circuit in fig.2 Rin, RO, AV, and Ai assuming the following
typical hybrid parameters:
hie=4.3kohms
hre=2.2 x10-4
hfe=300
hoe=3.6 x10-6 1/ohm

5. Procedure:
The values of the components to be used are:

R1=120 kOhms Rc1=250 Ohms Transistor: BC107B
R2=56 kOhms Rc2=1.8 kOhms
Rv=200 kOhms ( decade ) RE=1kOhm
Rb=82 kOhms RS1=390 kOhms
RL=3.9 kOhms RS2=3.9 kOhms
C1= C2=10µF CE =220µF
5.1 A more practical version of fig.5(a) is shown in fig.6. Use Rs=RS1 and
Rc=RC1. The operating point to be used in this experiment is
(VCE=3.5V,IC=2.0mA). Since IB will have to be different for transistors with
different values of β, RB will have to be variable. Have the circuit checked
by the instructor and set VCC=4.0V. Vary RV until a voltage of 3.5V is
obtained between collector and emitter. This happens when Ic=2.0mA.
Leave RB at this point and connect a 1.0kHz signal es of 1 to 2VPP. Adjust
eS to get e0 = 0.2VPP. Record the corresponding values of es and ei. Repeat
for e0 = 0.3 and 0.4VPP as a check for your results.
5.2 Connect the circuit of fig.2 with Rs=RS2 and Rc=RC2. Have it checked by
the instructor and apply VCC=9V. Record the DC potentials at the base,
emitter, and collector using the VTVM, and verify that the transistor is
biased close to ( VCE=3.5V, IC=2.0mA). If the operating point is found to
deviate from this significantly, use a decade resistance for RE to adjust
VCE to 3.5V.
5.3 Apply a 1.0kHz signal eS making sure that eo does not exceed 1VPP. Record
the corresponding values of eS, ei, and eo. Repeat for another value of eS.

5.4.Determine the output resistance of the amplifier loading the circuit with RL
= ∞ and RL=3.9kOhms and measuring e0.
6. Discussion
6.1 Compute βdc from the DC potentials obtained in 5.1.
6.2 Compute hie and hfe using Eqns.(11) and (12). Estimate the uncertainties
in these values and comment on the applicability of the simplifying
assumptions used in the derivations of these equations. How does βdc
compare with hfe?
6.3 Use the DC measurements in 5.2 to determine the operating point of the
amplifier in fig.2 (ICQ, VCEQ, VBEQ). The biasing circuit was designed to keep
ICQ in the range ICQ=2.00±0.35mA. Verify that this holds for the circuit you
are testing.
6.4 Use Eqns.5(a), 7(a) and 10(a) and the experimental values of hie and hfe to
calculate Rin, AV, Ai and RO. Now use your measurements of eS, ei., and eo
and the relevant component values to determine the experimental values of
the above four quantities. Comment on the agreement between the
theoretical and experimental values and explain any serious
disagreements.
6.5 Plot the Thevenin equivalent circuit of the amplifier (without the resistance
RS).
7. Data sheet

Experiment
Frequency Response of
7 a transistor amplifier
1. Objective: To study the frequency response of an RC-coupled common

emitter amplifier.
2. Equipment: 1 dc power supply 9V

1 dual trace oscilloscope
1 electronic voltmeter
1 function generator 10Hz ..1MHz / 10mVPP
3. Theory
The frequency response of a transistor amplifier is conveniently studied using

the hybrid-pi model for the transistor. Unlike the parameters of the other
models of the transistor, the parameters of this model are frequency-
independent provided that f << 3fT, where fT, known as the transition
frequency, is defined as the frequency at which the short circuit common
emitter current gain attains unit magnitude. The hybrid-pi model can
therefore be considered as valid for f ≤ 0.3fT. For the transistor types used,
manuals show that fT=170MHz for IC=2.0mA. Hence the model is useable up to

50MHz. Note, however, that this does not mean the transistor itself is used up
to this frequency. A moderately simplified version of the hybrid-pi model is
given in fig.1(a). Inter-electrode capacitances between the terminal pairs B-E,
B-C, and C-E have been neglected.
At low frequencies the circuit if fig.1(a) reduces to that of 2(a). The hybrid
model of the transistor is shown in fig.2(b) for comparison purposes.
An approximate relationship between the parameters of the hybrid model and

the hybrid-pi model is as follows.
hie= rx + rπ // rµ ≈ rx + rΠ (1)
hfe=gm rπ // rµ ≈ gm rπ (2)
hre= rπ / (rπ +rµ ) ≈ rπ /rµ (3)
hoe=1/r0 + (1+gm rπ) /( rπ + rµ )=1/r0 +gm rπ / rµ (4)
Fig.1 (a) hybrid-pi model for a transistor (b) approximaion hybrid-pi model.

Fig.2 (a) the hybrid-pi model at low frequencies (b) the CE hybrid model
Fig. 3(a) common-emitter amplifier
cµ
rπ cπ
Fig. 3(b) Simplified version of 3(a)

For the same reason that hre and hoe are neglected in the hybrid model, the
hybrid-pi model can be simplified by considering rµ and ro as open circuits.
For most practical purposes, therefore, the model of fig.1 (a) can be replaced by
the circuit of fig.1(b).
The amplifier to be studied in this experiment and its small-signal equivalent

circuit are given in fig.3.
Fig.3(b) includes wiring capacitance on the load side, including the input
capacitance of the oscilloscope. The voltage gain expression for this circuit is
highly complex and a derivation of the complete expressions will be avoππided.
Fortunately the values of the capacitances shown are such that the circuit can
be broken down into three simpler circuits: one applicable in the low-frequency
range, where only the coupling and bypass capacitances (C1, C2 and CE) need
be considered, a second applicable in the mid-frequency range where all the
capacitances have negligible effects, and a third applicable at high frequencies
where only the inter-electrode and wiring capacitances (CΠ,Cµ and Cw) are
considered.
rπ
Fig 4 Hybrid-π model for Mid frequencies

The mid-frequency equivalent circuit shown in fig.4 is studied first. In this

frequency range, C1, C2, and CE act as short-circuits and CΠ, Cµ and Cw act as
open circuits.
From fig.4, it can be seen that:

rπ rπ RB / /(rx + rπ )
V= ei = es
rx + rπ rx + rπ Rs + RB / /(rx + rπ )
or
rπ Ri
V= es
rx + rπ Rs + Ri
where Ri = RB / /(rx + rπ )
Since
e0 = -gmVRac, one can write:
− gmrπRac Ri
eo = es
rx + rπ Rs + Ri
(5)
eo − gmrπRac Ri
so that Amid = =
es rx + rπ Rs + Ri
The low-frequency equivalent circuit is shown in fig.5(a).
The analysis of this circuit is also unwieldy unless the latter can be modified
further. This is in fact made possible by practical amplifier design
considerations. Of the three capacitances in the circuit, CE is always the
largest and, in order to minimise its size and cost, it is allowed to determine the
lower 3-dB frequency of the amplifier, while C1 and C2 are chosen so as to have
negligible reactances at this frequency. This enables the circuit of fig.5(a) to be
simplified to that of fig.5(b).

rπ
Fig 5 (a) Equivalnet circuit for low frequencies
Using fig.5(a), it can be shown that:

 ei V   Rs  Rs
es =  +  Rs + ei = ei1 +  + V
 RB r π   RB  rπ
and that,
V (1 + gmrπ ) RE 
ei =  rx + rπ +
rπ  1 + jωCERE 
so that,
V  (1 + gmrπ ) RE  RB + Rs 
es =  rx + rπ + + Rs 
rπ  1 + jωCERE  RB 
Since eo = − gmVRac, one has,
eo gmrπRacRs′
AV 1 = =− (6)
es  (1 + gmrπ ) RE 
Rs Rs′ + rx + rπ +
 1 + jωCERE 
where Rs′ = RB / / Rs
(6) can be rewritten in the form
gmrπRac Ri 1 + jωCERE
AV 1 = −
(rx + rπ ) Ri + Rs  (1 + gmrπ ) RE 
1 + Rs′ + rx + rπ + jωCERE 
or
Amid (1 + jω / ωE )
AV 1 = (7)
(b + jω / ωE )
using (5) and letting
1 (1 + gmrπ ) RE
ωE = and b = 1 +
RECE Rs′ + rx + rπ
Eqn.(7) shows that the circuit of fig.5(b) has two natural frequencies, that is a
zero at ωE and a pole at a frequency ω1 such that b=ω1/ωE, or ω=bωE . The pole
at ω1=bωE is defined as the lower 3-dB frequency so that:
bωE b
f1= = (8)
2π 2πRECE
f1 = ωE/2π = f1 / b is the frequency below which AV1 approaches the constant

value Amid/b. However, if b>>1, C1 and C2 cannot be considered to act as short

circuits, and the approximation of fig.5(b), and hence Eqn.7, is valid only for
frequencies close to f1.
Fig 5 (b) Simplified version for the case CE is Dominant
If CE were to be made very large and either of C1 or C2 were to determine the

lower 3-dB frequency, the circuit of fig.5(a) would reduce to that of fig.6. This
circuit will now be used to determine the natural frequencies corresponding to
C1 and C2.
rπ
Fig 6. Low frequency equivalent circuit for the case when C1 and c2 are
dominant
Inspection of fig.6 shows that:

rπ RB (rx + rπ )
V = es
rx + rπ 1
RS + + RB / /(rx + rπ )
jωc1
or,
rπ RB (rx + rπ ) 1
V = es ( 9)
rx + rπ RS + R B / /(rx + r ) π 1
1+
jωC1 [ RS + RB / /(rx + rπ )
Similarily, it can be seen that
R ( R + 1 / jω c 2 ) RL
eo = − g mV C L
RC + R L + 1 / jω c2 ( R L + 1 / jω c2 )
or ,
RC R L Rac
eo = − g mV = − g mV (10)
RC + R L + 1 / jω c2 1 + 1 / jω c2 ( RC + R L )
Using Eqn.(9) in Eqn.(10),it can beshown that,
g r R Ri 1
AVe = − m π ac
(rx + rπ ) RS + Ri  1  1 
1 +  1 + 
 jω c1 ( RS + Rin )   jω c2 ( Rc + R L ) 
or ,
Amid
AVe = (11)
ω1 ω2
(1 + )(1 + )
jω jω
1 1
Where ω1 = and ω 2 =
C1 ( RS + Ri ) C2 ( Rc + R L )
If ω1 and ω2 are widely separated, the higher of the two natural frequencies
will determine the lower 3-dB frequency of the amplifier. Since it is generally
advantageous to let CE determine the lower 3-dB frequency, C1 and C2 are
chosen in such a way that ω1 <ωL/10 and ω2 < ωL /10, or
10 RE
C1 > C , − − − − − − − − − − − − (12 a )
b( RS + Ri ) E
and
10 RE
C2 > C , − − − − − − − − − − − − (12 b)
b( R C + R L ) E
where b isgiven by Eqn.(8).

The high-frequency equivalent is shown in fig. 7(a). Fig. 7(b) is obtained from
this by applying Miller’s theorem.
rx cµ
rπ
Fig 7(a) Equivalent circuit for high frequencies
rx
rπ
Fig 7(b) Simplified circuit using Milner’s theorem
The applicable relationships are
Ci=CΠ +(1+gmRac )Cµ (13a)

and

C0=Cω + (1+ 1/gmRac)Cµ. (13b)
using fig.7(b), it can be shown that:

 
rx  rx 1 1 
es = V ( + 1) + V  ( + 1). + RS
1  r // 1 RB 1 
rπ / / rπ / /
j ω ci 

π
j ω ci jω c i 
or ,
( rx + rπ + R ' S ) R S
es = ' [1 + jω ci . rπ / /( rx + R ' S )]V − − − − − − − − − − − − − − − − (14 )
rπ R S
and that
1 g m R ac
e o = − g mVR ac / / =− V − − − − − − − − − − − − − − − − − − − − (15)
jω c o 1 + jω c o R ac
From Eqns.(14) and (15), one has

eo g m rπ Rac RS′ 1 1
AVh = =−
es RS (rx + rπ + R ' S ) [1 + jω ci rπ / /(rx + R ' S )] (1 + jω co Rac )
or ,
g m rπ Rac Ri 1 1
AVh = − . .
(rx + rπ )( RS + Ri ) [1 + jω ci& rπ / /[rx + R ' S ] (1 + jω co Rac )
which can be put in the form

Amid
AVh = − − − − − − − − − − − − − − − − − − − − − −(16)
jω jω
(1 + )(1 + )
ωi ωo
where
1 1
ωi = and ωo =
ci rπ / /(rx + R' S ) co Rac
If ωi<< ω0, the upper 3-dB frequency of the amplifier is determined by Ci and ωh
≈ ωi. Then

ωi 1
fh = = , − − − − − − − − − − − − − − − − − − − (17a)
2π 2π ci rπ / /(rx + R' S )
If ωi and ω0 are not widely spaced, a good approximation for fh is given by

1
fh ≈ ,− − − − − − − − − − − − − − − − − −(17b)
2π [Ci rπ / /(rx + R' S ) + CO Rac ]
Earlier it was pointed out that the hybrid-pi model is valid up to about 0.3fT,
where fT is the transition frequency. fT will now be related to the parameters of
the hybrid-pi model in fig.1(b). The short-circuit CE current gain Aie will be
determined from fig.8.
Fig 8 Circuit for the determination of short circuit CE current gain
Noting that:
IC = V [ g m − jω C µ ]
and
1
Ib = V [ + jω (Cπ + C µ )]
rπ
One obtains
I g m rπ − jω rπ C µ
Aie = C =
I b 1 + jω rπ (Cπ + C µ )
OR
h fe − jω rπ C µ
Aie = − − − − − − − − − − − − − − − − − − − (18)
1 + jω rπ (Cπ + C µ )
ω T = 2π f T is defined as the frequency at which Ai = 1.

Hence
h fe − jω T rπ C µ = 1 + jω T rπ (Cπ + C µ )
OR
h 2 fe + ω T 2 r 2 π C 2 µ = 1 + ω 2
T r 2 π (Cπ + C µ ) 2
For h 2 fe >> 1 , one has
2C µ
[ ]
h 2 fe = ω T 2 r 2 π (Cπ + C µ ) 2 − C 2 µ = ω T 2 r 2 π C 2 π (1 +
Cπ
)
So that
h fe
ωT =
2C µ
rπ C π 1 +
Cπ
and
h fe
fT = − − − − − − − − − − − − − (19 )
2C µ
2 π rπ C π 1 +
Cπ
For C π >> C µ , this becomes
h fe
fT =
2 π rπ C π
Another parameter of interest is the β-cutoff frequency, f β , which is defined as

1
that frequency at which the short-circuit current gain drops to = 0.707 of its
2
low-frequency value hfe.
From Eqn. (18)

h fe
Aie (ω β ) =
2
OR
2
2 Ai e (ω β ) = h 2 fe
which leads to
1 1
ωβ = ≈
2c µ 2 rπ (cπ + c µ )
rπ (cπ + c µ ) 2 +
h fe 2
so that
ωβ 1
fβ = = − − − − − − − − − − − − − − − − − (20)
2π 2π rπ (cπ + c µ )
h fe
Since h f b = − , fα, the α-cutoff frequency, or the frequency at which the
(h fe + 1)
1
short-circuit CB current gain drops to = 0.707 of its low-frequency value, is
2
given by:
[ ]
f α = h fe + 1 f β ≈ h fe f β ,
So that
h fe
fα = − − − − − − − − − − − − − − − − − − − −(21)
2π rπ (cπ + c µ )
Thus, when CΠ >>Cµ , it is seen that f T ≈ f α ≈ h fe f β .
The significance of fB is in that the low-frequency hybrid-parameters are valid

only up to about 0.1fB, while, in contrast, the hybrid-pi parameters are valid
up-to about 0.3fT.
The equations derived in the above theoretical notes will now be applied to the
analysis of the test amplifier to be used in this experiment.
Typical values for the transistor group used are

hfe=300 and hie=4.3kohm
as corrected for an operating point of (VCE=3.5V,IC=2.0mA). Since the value of

gm is not provided, the theoretical value at 250c will be used.
q IC 1.60 X 10 −19
gm = = .I = 38.9 I C ,
K T 1.38 X 10 −23 X 298 C
Since IC=2x10-3A ,
gm =38.9x2x10-3 = 0.078 mho
Using Eqn.(2),
h fe 300
rπ = = = 385
. kΩ
gm 0.078
Using Eqn.(1)
rx =hie - rΠ =4.3 - 3.85 =0.45 kΩ
with RS=3.9 kΩ and RB= R1//R 1 =56//120 =38.2 kΩ.
R’S=RS //RB =3.9//38.2=3.54 kΩ
Since RE=1.0 kΩ
(1 + g m rπ ) R E (1 + h fe ) R E 301
b = 1+ = 1+ = 1+ = 1 + 38.4 = 39.4
R ' S + rx + rπ R ' S + hi e 3.54 + 4.3
using Eqn.(8) with CE=220µF,
June, 2011 Page | 100

b 39.4
f1 = = = 28.5Hz
2π RE C E 2π × 0.22
Ri = RB / /(rx + rπ ) = RB / / hi e = 38.2 / /4.3 = 3.⋅86kΩ
U sin g Eqns. (12a ) and (12b)
10 R E 10 × 1 × 220
C1 > CE = = 7⋅2µ F
b( RS + Ri ) 39 ⋅ 4(3 ⋅ 9 + 3 ⋅ 86)
and
10 RE 10 × 1 × 220
C2 > CE = = 1⋅ 9 µ F
b( RC + R L ) 39 ⋅ 4(1 ⋅ 8 + 27 ⋅ 0)
The values used are C1=10µF and C2=4.7µF, so that the above conditions are
satisfied.
Transistor manuals give CC=Cµ= 4pF at VCB=3.0V and Ce =CΠ=9pF at

VBE=0.65V for both BC107 and BC147 type transistors. Using these values in
Eqn.(13a) and (13b ) yields:
Ci ≈ CΠ +gm Rac Cµ =9 + 78x1.69x4=536PF
and
C0≈Cω+ Cµ =13 + 4 =17PF,
where 13pF is the input capacitance of a typical 10X1 oscilloscope probe, and is
used as the wiring capacitance on the load side of the amplifier.
From Eqn.(16),
June, 2011 Page | 101

1 10 7
ωi = = = 9 ⋅ 52 × 105 rad / s
Ci rπ / /(rx + R' S ) 5 ⋅ 36 × 1 ⋅ 96
an d
1 10 9
ωo = = = 3 ⋅ 48 × 10 7 rad / s
CO Rac 17 × 169
.
Since
ω o = 37ωi >> ωi , Eqn.(17a ) can be used for f h and
ωi 9 ⋅ 52 x105
fh = = = 152 kHz
2π 2π
If it is now required to reduce this frequency to 20kHz for use of the amplifier
in the audio-frequency range, a capacitance C can be connected between the
collector and base of the transistor. If rx in fig.7(a) is neglected (rx<< rΠ ),C can
be considered to be in parallel with Cµ
and Eqn. (17a) simplifies to:
1
fh =
2π Ci rπ / / R' S
Where
Ci ≈ Cπ + g m Rac (C µ + C )
Then
1
Ci = = 4 ⋅ 325 × 10 −9 F = 4325 pF
2π × 20 × 10 × 1 ⋅ 84 × 10
3 3
and
Ci − Cπ 4325 − 9
Cµ + C = = = 327 pF ,
g m Rac 132
So that
C = 32 ⋅ 7 − 4 ⋅ 0 = 29 ⋅ 7 pF ,
A value of 27pF should be satisfactory.
In the above analysis, the input resistance of the amplifier, Ri is found to be

3.86kΩ. The mid-frequency voltage gain for the amplifier in this exercise
becomes:
June, 2011 Page | 102

g m rπ Rac Rin h fe Rac Rin

Amid = − ⋅ =− ⋅
(rx + rπ ) Rin + Rs hie Rin + Rs
Or
300 x1 ⋅ 69 3 ⋅ 86
Amid = − x = −58 ⋅ 6 ≈ −59
4⋅3 3 ⋅ 86 + 3.9
This should drop to 0.707x59 ≈ 42 at the two half-power frequencies f1≈29Hz

and fh≈152KHz
(or fh≈20kHz if C=27pF is connected between the collector and base of the
transistor).
For the useful frequency range of the amplifier, the voltage-gain expression can
be obtained by inspection of Eqns.(7) and (16).
and
Amid
AV =
bω E jω
(1 + )(1 + )
jω ωi
OR
Amid Amid
AV = = − − − − − − − − − − − − − −(22)
ωl jω f1 jf
(1 + )(1 + ) (1 + )(1 + )
jω ωh jf fh
Provided that b>>1 and ωi<<ω0. The bandwidth of the amplifier is given by
1
BW = (ω − ωl ) = f h − fl − − − − − − − − − − − − − − − − − (23)
2π h
4. Preparation
4.1 Predict the values AMID, f1, and fh using the values of hie and hfe obtained
for the transistor BC107 from the previous exercise on transistor amplifiers.
Take CΠ=9PF and Cµ=4pF. If a probe 10:1 is not used C will be the input
capacitance of the oscilloscope which may reach from 30pF for a 35MHz
oscilloscope to 50pF for a 15MHz osilloscope. Assume using a 35MHz CRO.
June, 2011 Page | 103

4.2 Use Eqns.(19),(20), and (21) to calculate fT, fβ and fα and state whether fT
and fα are equal. How does the calculated value of fT compare with the
measured value of 170 MHz specified by the manufacturer? What possible
reasons can you find for the discrepancy between these values?
4.3 Explain briefly how to measure the phase shift using Lissajous figures.
4.4 Prepare one graph paper for plotting gain and phase VS frequency in the
range
10Hz...1MHz.
5. Procedure
Component values to be used:

R1=120 kohms RS=3.9 kohms
Transistor: BC-107B
R2=56 kohms C1=10 µF
R3=1.8 kohms C2=4.7 µF
RL=27 kohms CE=220 µF
RE=1 kohms CE=27 pF
5.1. Connect the circuit of fig.3(a). Set VCC=9V and check that the amplifier is
biased properly near VCE=3.5V and IC=2mA using only the electronic
voltmeter.
5.2. Connect a sinusoidal input with f = 1kHz and eS=10mVPP to the input.
Measure and record e0. Repeat for eS=20mVPP and calculate the mean
value of Amid.
June, 2011 Page | 104

5.3. Plot the gain vs frequency in the range 10Hz...1MHz into the prepared
graph paper making sure that eS is always constant at 10mVPP.
Determine the gain at each frequency for the circuit
a) without the capacitor C
b) with the capacitor C between collector and base.
Determine the cut-off frequencies from the plot.
5.4 Plot the phase shift between eS and e0 in the same range of frequency using
Lissajous figures for the circuit without C. Connect eS to the y-input and
e0 to the x-input. Since the phase shift is independent of the voltage you
can increase eS until the ellipse becomes distorted.
6. Discussion
6.1 Plot the dB voltage gain vs frequency both with and without C. Locate the
3-dB frequencies and determine the bandwidth of the amplifier both with
and without C.
6.2 Compare the experimental results with the prediction you made in the
preparation.
6.3 Explain any deviation or unexpected results.
7. Data sheet
June, 2011 Page | 105

Appendix A
LBORATORY REPORT FORMAT
I. Laboratory Report Evaluation
• Neatness-10%
• Theory-20%
• Procedure-20%
• Result-20%
• Conclusion-30%
Every student is expected to attend each and every laboratory class. Failure to attend one
laboratory will result in NG unless the laboratory is done by arranging a make up class.
Failure to do a lab on time results in 20% deduction from the over all mark.
.
II. Laboratory Report
- Each experiment shall be described by a laboratory report
- Each laboratory report shall be hand written or typed
- No portion of the laboratory report shall be done in pencil
(including graphs, circuit schematics, charts, etc.)
- Each laboratory report shall consist of the following sections
A. Theory
B. Methods and/or Procedures
C. Results, Observations, and/or Data Collection
D. Discussion and/or Conclusion
III. Laboratory Experiments
Keep in mind that lab reports are due one week after the completion of each lab exercise.
All experiments can be found in the laboratory manual.
IV. LABORATORY REPORT WRITING
Every Lab report has to have organization, structure, and must be written in a manner that
educates the reader. The following is a suggested structure and method for writing such a report.
Keep in mind that the intent of a report is to disseminate information to an audience that may or
may not have any idea of the nature or subject that you are describing in the report.
June, 2011 Page | 106

1. THEORY
-Briefly describe what the experiment is about.
-What is the subject matter?
-Who or what are the important components of the experiment?
2. PROCEDURE(S) / METHOD(S)
- List of equipment
- Formulas, equations, etc.
- Block diagrams
- Graphs, charts, tables, etc.
- Computer program
- Verbal description of the procedure or strategy used to perform the
experiment
3. RESULTS / OBSERVATIONS
- Formulas, equations, etc.
- Block diagrams
- Graphs, charts, tables, etc.
- Computer programs
- Verbal explanation of the results and observations
4. DISCUSSION / CONCLUSION
- Verbal summary of the experiment or event
- Provide any explanations of new or unknown phenomena
- Reflect on how the experiment could be changed or improved
- Provide a personal commentary on how the experiment impacted you
VI. Laboratory Report Format
The format must be written as shown in the next page
June, 2011 Page | 107

[Cover page]

Addis Ababa Institute of technology
Department of Electrical & Computer Engineering
Laboratory Report
Course No____________
Experiment No__________
Title: [The title of the experiment]
By: [Your Name]

Group: [Your Group Number]
Date of Experiment: …
Date of Submission: …
June, 2011 Page | 108

Equipment used [new page]
No Description Code/Lab Reference Quantity

1 Volt meter AAU 08-655 1
2 Dc source AAU 08-1150 1
3 Oscilloscope AAU 08-700 1
. . . .
. . . .
. . . .
Component used
No Description Type Quantity

1 Resistor 1K Ω 2
2 Capacitor 100 µ f 1
3 Transistor BC 108 1
. . . .
. . . .
. . . .
1. Theory[new page]
[Not more than 2 page]
2. Procedure[new page]
1.
2.
.
.
[Written in passive voice]
June, 2011 Page | 109
3. Calculation [new page]
• Perform your calculation in the experiment here
4. Results [new page]
• Better in from of tables comparing measured and theoretical value

• Graphs and wave forms plots when appropriate.
5. Discussion and conclusion [new page]
• Evaluate result obtained; giving reasons for departure for measured

values form theoretical ones.
• Comment on important observation
• Concluding remarks to what extent the objective of the experiment
was met.
June, 2011 Page | 110

Electrical Enginerring Lab II

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Addis Ababa University

Addis Ababa Institute of Technology

1. Objective: To study and repeat different basic measurements

4.1 Voltage measurements

4.1.1 Using oscilloscope(CRO)

To measure the AC component of a signal, display the waveform over the

June, 2011 Page | 1

variable control is in the calibrated position.To measure the DC level of a

4.1.2 Using multimeter, electronic voltmeter

4.2 Time measurements

4.2.2 Using counter

June, 2011 Page | 2

4.3 Frequency measurement

4.3.1 Using CRO

Number of Vertical Tangent Points (VT) :

fv = frequency to the Vertical input

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4.3.2 Using frequency counters

4.4 Phase measurement

4.5 Current measurements

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4.5.2 Using CRO

Figure 3: Thevenin’s Equivalent of a two-port network

In most practical cases the emf (electromotive force) Ei can be assumed to be

Figure 4: Measurement set up to determine Ri, Ro and Eo

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R1(R2) should be in the same range as Ri(Ro) to obtain best results.

4.7 Measurement of gain and frequency response

The frequency response, which is a function of frequency [A(f)], is defined as

June, 2011 Page | 6

Figure 5: Connection of equipment for determination of

5.1 Calculate the DC value across R1, R2 and R3 in fig .6.

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a) output short circuit by neglecting R4

6.1 Connect the circuit shown in fig.6.

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a) reading the scale of the generator

7.1 Describe the effect of supplying an additional AC input in 6.2.

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Power sources: low-voltage dc power supply, AC power supply.

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germanium doped with 0.001% arsenic for instance showing a 17,600-fold

The mechanism of electrical conduction in semiconductors is as follows. Like

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Atoms of Group v elements such as phosphorous (P), arsenic (As) and

Fig 1 a) P-type Semiconductor a) N-type Semiconductor

Semiconductors are doped or alloyed with p-type or n-type impurities as the

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Fig.2 P-N Junction

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highly temperature dependent since the minority carrier concentration is

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Fig 3 Junction Diode characteristics

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Fig 4 Zener Diode Charactrersics.

The dynamic or a-c resistance, rf is obtained by differentiating i with respect to

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A. Determination of Static Characteristics

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B Observation of Oscillogram of Zener Diode Characteristics

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3. Use the ohmmeter measurements of rdc and rr in part A to estimate the

6. Discuss any other significant observations.