Design and analysis of two stage CMOS

operational amplifier using 0.13 µm

technology
Cite as: AIP Conference Proceedings 2203, 020040 (2020); https://doi.org/10.1063/1.5142132
Published Online: 08 January 2020

K. T. Tan, N. Ahmad, M. Mohamad Isa, et al.

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© 2020 Author(s).
 Design and Analysis of Two Stage CMOS Operational
Amplifier using 0.13 µm Technology

K.T.Tan1, a), N. Ahmad 1, b), M. Mohamad Isa1, c), F.A.S. Musa1, d)

1
School of Microelectronic, Universiti Malaysia Perlis, Kampus Pauh Putra, 02600 Arau, Perlis, Malaysia
a)
Corresponding author: khaitee0301@gmail.com
b)
norhawati@unimap.edu.my
c)
muammar@unimap.edu.my
d)
amirasyakirahmusa@yahoo.com

Abstract: Nowadays, low power operational amplifiers (op-amp) are highly demand for most of the applications such
as in medical and communication system. In this project, two stage op-amp is designed and operated at 1.8 V supply
voltage. The supply voltage is scaled down to reduce the power dissipation of the op-amp. This is because the power
will be high when there is a large supply voltage. The design is simulated and analysed using Mentor Graphic Pyxis
software. This two stage op-amp is designed using the Silterra 0.13 µm process technology. The operational amplifier
provides a Direct Current (DC) gain of 21.18 dB and a unity gain bandwidth of 6.31 MHz. The gain margin obtained
from the op-amp is 14.07 dB and the phase margin of the op-amp is 94.26 ° for 3 pF compensation capacitor and 10
pF load capacitor. The result shows that circuit able to work at 1.8 V power supply voltage and the total power
dissipation for the op-amp is 5.35 mW.

INTRODUCTION
The operational amplifier (op-amp) is defined as the most versatile and vital building blocks in the analogue
circuit or mixed signal circuit design (Bangadkar, 2014). It has variety function and can be applied to many
applications such as communication and medical system. The forward gain of an op-amp is sufficiently high. The
closed-loop transfer function is where negative feedback is used and makes the gain practically independent of it.
Large open-loop gain is needed for an op-amp in order to implement negative feedback concept. Typically, an
open loop gain for an ideal op-amp is infinity.

There are varieties of applications that op-amp is applied on due to its linear device characteristic. In order to
produce a good product, differential inputs are applied to the amplifier to obtain a higher gain. Nowadays, the
design of the op-amp becomes more challenging and tougher for the designer because the transistor channel length
of the CMOS technology gradually reduced. With the proper selection of feedback components, op-amp is used
to describe amplifiers that performed various mathematical operations such as addition, subtraction, integration
and differentiation (Yadav, Saxena, & Rajput, 2017).The advantage of the differential inputs of the op-amp is that
it is able to amplify a million times larger at the output signal. Ideally, op-amp has an infinite input impedance at
the input terminal, infinite differential voltage gain, and zero output impedance at the output impedance. However,
in reality, it only approaches these values.

Basically, there are three main blocks in two stage op-amp which is a differential amplifier, gain stage and
output buffer as shown in Fig. 1. The input differential amplifier block is designed to provide high input
impedance, large CMRR and PSRR, low noise, high gain and low offset voltage. The second stage of the op-amp
performs level shifting which added gain as well as the conversion of differential to single ended (Verma, Sharma,
Singh, & Yadav, 2013). The output buffer is the last block where it produces low output impedance. The main
target of this project is to design two stages op-amp by using Mentor Graphic Pyxis with 0.13 µm technology.

The 2nd International Conference on Applied Photonics and Electronics 2019 (InCAPE 2019)
AIP Conf. Proc. 2203, 020040-1–020040-5; https://doi.org/10.1063/1.5142132
Published by AIP Publishing. 978-0-7354-1954-4/$30.00

020040-1
 FIGURE 1. Block Diagram of Two Stage Op-Amp

The outline of this paper presents as follows: In section II Designing of Two Stage Op-Amp, the steps and
specifications of two stage op-amp will be presented and the circuit design for this work will be discussed.
Meanwhile, in Section III Results and Discussions will gather and discuss the obtained results. In Section IV
Conclusion will deduce the findings of this work and the further improvement of this design will be discussed in
Section V.

DESIGNING OF TWO STAGE CMOS OP-AMP

The designed op-amp had been simulated and the design was performed in Mentor Graphic. In this
section, the design specification shown in Table 1 in order to compare with the obtained parameters of the device
through the simulation result.

A. Design Procedure
Steps in designing a CMOS op-amp:

 A basic structure of two-tage CMOS op-amp was created

 The compensation required by the design was identified
 The specification of the design was identified
 The DC current and transistor size was selected
 Schematic implementation of the design
 Analysis of the result

TABLE 1. Design Specification

Parameters Value
i. Open-loop gain 100 V/V (40 dB)
ii. Unity gain bandwidth 5 MHz
iii. Phase margin, Φm ≥ 60°
iv. Power supply 2V
v. Load capacitance, (CL) 10 pF
vi. Maximum power dissipation ≤ 5 mW
vii. Channel length 0.13 µm

B. Circuit Design
Two stage op-amp comprised of three subsections which were a differential gain stage, gain stage and
bias strings. The first stage which was the differential stage of the circuit provided a higher gain while the second
stage which was known as the gain stage helped to provide an additional gain in order to obtain a large output
swing. Figure 2 shows the schematic of the two stage CMOS op-amp that will be designed through this project
using 0.13 µm technology.

020040-2
 FIGURE 2. The proposed Two Stage Op-Amp

Transistor M1, M2, M3 and M4 form the differential stage of the op-amp. The two nMOS transistors
which are M1 and M2 form the differential inputs of the amplifier. The gate M1 and M2 are the inverting and
non-inverting inputs respect to the transistors. The resistance of the input transistors and active load transistors
which are M3 and M4 are the main resistances that contribute to the output (Priyanka, Aravind, & Hg, 2017). The
advantages of using the current mirror active load transistors M3 and M4 are that current mirror can help in the
conversion of the input signal from the differential to single-ended while the load helps with common mode
rejection ratio. The current of M1 and M3 are equal because M1 is mirrored by M3 and the current of M2 and M4
are the same because M4 is subtracted from the current from M2.

The transistors M6 and M7 form the second stage which was a current sink load inverter. The output
from the drain of M2 and amplifies it through M6 which called as common source configuration (Verma et al.,
2013). Besides, the biasing of the op-amp was achieved with four transistors. Transistor M5 and M8 controlled
by the bias string where it sink a certain amount of current based from the gate to source voltage. Compensation
capacitor (CC) is connected to the output of the first stage. Its function was to reduce the frequency of the dominant
pole and move the output pole away from the origin (Razavi, 2001). Load capacitor was connected at the output
of the op-amp.

RESULTS AND DISCUSSIONS

The result for the DC analysis of the proposed circuit is simulated in order to observe the operation of the
transistor. Figure 3 shows the graph of Id versus Vgs for the transistor M6.

020040-3
 FIGURE 3. Graph of Id versus Vgs

When the gate voltage increases from zero, the transistors operate in the sub-threshold region. Then, the
transistors start to operate in the saturation region at a gate voltage of 0.8 V and the current is 1.45 mA. The value
of the current is quite high, therefore it can be the total IV characteristic of two stage op-amp. The current starts
to become constant when the transistor operated at a gate voltage of 1.53 V with 7.59 mA.
The simulated result obtained from the frequency response is shown in Fig. 4.

21.18 dB

14.07 dB

94.26 °

.
FIGURE 4. Frequency Response

The gain margin obtained is 14.07 dB and the phase margin is 94.26 ° where it is unconditionally stable.
The more positive the margin, the more stable will be the system. The optimum value of a phase margin is 60 °
where the step response of a feedback system will exhibit little ringing and provide a fast settling. The open-loop
gain obtained is 21.18 dB. Open-loop gain is very important because it is used to determine the precision of the
op-amp with a feedback system. Therefore, the higher the open-loop gain, the more precise the feedback system
employing the op-amp.

020040-4
 CONCLUSIONS

In this paper, a well-defined method for the design of a two stage op-amp has been presented. The design
has been made through the scaling of device parameters. In DC analysis, power dissipation obtained is comparable
to the specification which is 5.35mW. IV characteristic determines the operation region of the op-amp. In this
design, all the transistors are operated in the saturation region. The transistor started to operate in the saturation
region at 0.8 V. AC analysis is used to determine the stability of an op-amp. Compensation capacitor is added
because it will affect the stability of the op-amp. The gain margin and phase margin obtained are 14.07 dB and
94.26° respectively.

REFERENCES

1. Bangadkar, B. (2014). Two Stage Op-Amp Using Cmos, 1(7), 664–666.

https://doi.org/01.0401/ijaict.2014.07.33
2. Priyanka, T., Aravind, H. S., & Hg, Y. (2017). Design and implementation of two stages operational
amplifier. International Research Journal of Engineering and Technology(IRJET), 4(7), 3306–3310.
Retrieved from https://irjet.net/archives/V4/i7/IRJET-V4I7657.pdf
3. Razavi, B. (2001). Design of Analog CMOS Integrated Circuit. McGraw-Hill.
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