1 IEEE CICC 2022

3nm Gate-All-Around (GAA) Design-Technology Co-

Optimization (DTCO) for succeeding PPA by Technology
Taejoong Song, Hakchul Jung, Giyoung Yang, Hoyoung Tang,
Hayoung Kim, Dongwook Seo, Hoonki Kim, Woojin Rim, Sanghoon
Baek, Sangyeop Baeck, Jonghoon Jung

Samsung Electronics, Hwaseong, Korea

Abstract
3nm Gate-All-Around (GAA) technology is introduced to suggest
the future of logic transistor with performance, power, and area
(PPA) benefit. However, as with the recent advanced technologies,
GAA technology also faces the potential challenges to overcome for
the optimum PPA. Therefore, Design-Technology Co-Optimization
(DTCO) has become more important than ever to maximize
technology-to-design benefits of GAA. In this paper, the motivation
of DTCO is presented by showing the successful design examples
in advanced technologies. Then, the design techniques of standard
cell and SRAM compiler are proposed based on DTCO to maximize
the benefit of 3nm GAA technology.
2022 IEEE Custom Integrated Circuits Conference (CICC) | 978-1-6654-0756-4/22/$31.00 ©2022 IEEE | DOI: 10.1109/CICC53496.2022.9772784

Introduction
Technology has been developed to meet the requirement of PPA by
providing solutions to System-on-Chip (SoC) design [1]. Figure 1 (a)
shows the technology pitch scaling and standard cell density over
upcoming years [1]. Contact poly pitch (CPP) and metal (Mx) pitch
scale down by forming standard cell scale down consisting of x-
and y-dimension. The critical design rule is supported for small x-
and y-dimension of standard cell, which is integrated into standard Fig. 1. (a) Technology pitch scaling and standard cell density over
cell architecture. Then, standard cell is developed to implement upcoming years [1]. (b) CPU throughput at fmax and the constant
block design with competitve PPA. Figure 1 (b) shows CPU power density according to IRDS2021 [1].
throughput at fmax and at the contant power density. CPU
throughput expects sequential ascent over years by meeting
market requirement. Generally, SoC design utilizes fast transistor or
high-performance design technique to achieve high throughput.
However, as shown in Figure 1 (b), throughput gets saturated at the
constant power density over years, since high-performance
technology and design knobs require power consumption
accordingly. Therefore, the competitive technology and design
solutions are necessary to provide low-power solution by meeting
high-performance at the same time. In this paper, the various
design techniques are introduced to recover PPA challenge in
advanced technologies. Then, DTCO are proposed to succeed PPA Fig. 2. SoC area breakdown of standard cell, SRAM, IO, and IP.
benefit above 3nm GAA technology. Standard cell occupies the largest portion, and SRAM the second
largest of SoC area.
Standard cell and SRAM design in SoC
Standard cell and SRAM are crucial elements of SoC design Table 1. Technology-to-design scaling level
constituting a dominant portion in terms of transistor count and die
area [2]. Figure 2 shows the area breakdown of SoC design. Scaling levels Scaling features
Standard cell occupies the major portion of SoC by more than 50%,
and SRAM takes the second largest area by about 30%. The area Level-I Gate length, Gate-to-contact space, Mx pitch
portion is different according to the specifications of SoC design, Level-II Gate cross-coupled structure, diffusion break
but there is no doubt that standard cell and SRAM occupy most
area in SoC design by impacting the overal PPA. Therefore, DTCO Level-III Facilitation of place and routing elements
techniques are majorly introduced in standard cell and SRAM Level-I*II*III Block scaling
design in this paper. Standard cell is the smallest macro that
implements various functionality of SoC design. Then, its
characteristics of PPA are clearly determined by the features of Especially, since SRAM power and performance are dependent on
technology parameters along with circuit and layout architecture. SRAM assist techniques, the various SRAM assist design
Therefore, standard cell is defined and evaluated from the very techniques are exploited in this paper.
early stage of technology definition to assess PPA of technology.
Meanwhile, standard cell plays an important role in providing a
design environment in conjunction with automated EDA tool. For DTCO for standard cell and block scaling
this reason, the competitiveness of standard cell is decided by not Technology-to-design scaling is featured by many factors thorugh
only its own PPA, but also its competence with EDA tool. The key several design levels as shown in Table 1. Level-I factor shows the
features of technology-to-design scaling is discussed in the next intrinic standard cell scaling with x- and y-dimension. Level-II factor
Section with standard cell architecture and routing capability. Then, includes cell-level architecture regarding dummy gate inside and
SRAM, the 2nd largest design in SoC, is discussed by providing outside cell. Lastly, level-III factor is related to cell-to-block scaling
DTCO knobs to optimize area by layout and circuit improvement. in terms of pin solution and routing resources.

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 IEEE CICC 2022 2

Fig. 3. Inverter standard cell layout architecture with critical

dimension for level-I scaling. Middle-of-layer (MOL) and metal
pitch dimension decide x- and y-dimension of standard cell.
Figure 3 shows inverter stanard cell layout architecture with the
critical dimension. The area of standard cell is categorized by three
design levels as shown in Table 1. The first scaling level is a
lithographical dimension such as critical poly pitch (CPP), gate
length, gate-to-contact space, and metal pitch. For example, in
order to reduce CPP dimension, gate length or gate-to-contact
space is scaled down, which impacts x-dimension of standard cell.
Then, metal pitch and gate contact-to-source (or drain) space Fig. 4. Standard cell features of level-II scaling factors. (a) Double-
decide y-dimension of standardd cell. Since each critical feature of diffusion-break (DDB) and single-diffusion-break (SDB) construct
x- and y- dimension is provided by technology capability, they are architecture. (b) 3-CPP and 2-CPP cross-couple construct
very related to technology scheme at the very early stage of architectures [5].
technology definition. Therefore, thoruough DTCO is performed to
evaluate and decide the critical dimension with the tool of PPA and
cost equation.
In addition to x- and y-dimension, there is another factor that affect
standard cell area, which defines the required dimension for space
inside and outside cell. As Table 1 indicates, level-II scaling factor
plays an role of reducing the space required for the isolation of
signal-signal, signal-power, and power-power. Figure 4 (a) shows
standard cell layout architecture with double-diffusion-break (DDB)
and single-diffusion-break (SDB) for inverter cell. Inverter cell
requires two CPPs ideally to implement the function comprising
gate and single dummy gate at the right and left of cell boundary,
which is called as SDB structure [3], [4]. However, if technology
does not support single dummy gate to isolate signal or power
between adjacent cells, inverter standard cell is designed by three
CPPs, which is called as DDB structure. Inverter cell with DDB
structure increases area by 50% comparing to SDB inverter cell,
which impacts 15%~20% area penalty of standard cell design.
Figure 4 (b) shows gate cross-coupled structure, which connects
the adjacent gates across. Generally, two active gates of #1 are
connected across with metal layer, while center active gate of #2 is
connected veritically by forming 3-CPP cross-couple structure.
Meanwhile, 2-CPP cross-couple connects two active gates across
through metal and poly layer, which removes dummy gate for area
reduction. Cross-couple structure is widely used in complex
standard cell such as flip-flop (F/F) and multiflexer (MUX).
Therefore, 2-CPP cross-couple helps to reduce area by more than
6% in standard cell design. Since SDB and 2-CPP cross-couple
features influence standard cell area a lot, DTCO is applied Fig. 5. (a) And-or-inverter (AOI) standard cell schematic with pin
connection in place-and-routing. (b) AOI pin solution with pin-
thoroughly to optimize design-rule and layout at the first stage of
technology definition like level-I scaling factor. When special access (PA) and remaining-pin-access (RPA) [6].
construct requires additional cost to implement the required rule,
cost and gain are assessed to adopt the construct in design. Figure 5 shows and-or-inverter (AOI) standard cell schematic with
Meanwhile, level-III scaling factor is defined as cell-to-block pin connection in place-and-routing. Since AOI cell is one of the
deployment, which facilitates place-and-routing capabilities such as most congested cells in place-and-routing, its pin solution and
pin solution and routability of standard cell. If level-I and level-II are routing resources are important to optimize block area. Cell-level
related to cell area itself, level-III scope is extended to block area routability is analyzed at the early stage of cell design by calculation
above cell area. to avoid design turn-around-time from cell design to block design by
place-and-routing.
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pin soluton analysis for AOI
apply.
3 IEEE CICC 2022

cell. A, B, and C pins provide two hitting points to M2 horizontal pin

respectively, which is called as pin-access (PA). Meanwhile,
remaining-pin-access (RPA) is defined as the allowable hitting point
when the adjacent pin is taken by other routing resource. For
example, AOI type 1 cell in Figure 5 (b) does not allow additional
hitting point to pin C when the adacent pins of A and B are hitted by
M2. There is no enough space for C pin to be picked up if M2 tip-to-
tip (T2T) space is not small enough in the same M2 track. As a
result, RPA of C pin is zero by calculation in case of AOI type 1 cell.
Meanwile, AOI type 2 cell provides more pin solution by allowing
additional space inside cell with RPA=2. If two types of cells, type 1
and type2, are routed by EDA tool, type 2 cell with higher RPA
implements smaller block area with the help of more pin solution.
Therefore, stanard cell architecture is designed to allow enough pin
solution at the early design stage by analyzing the interference
phenomenon of adjacent pin solution such as RPA equation [6].
Fig. 6. SRAM bitcell and logic area trend [7]. Area gap between
Technology-to-design scaling is not decided by single scaling factor, bitcell and logic area gets smaller due to improved design rule.
but by multiple scaling factors from basic pitch dimension, special
construct, and routability as explained before. Therefore, DTCO is
applied to optimize the whole scaling factors from cell-level to
block-level. Advanced patterning scheme shrinks the basic design
rule from level-I scaling. Shallow-trench-isolation (STI) is developed
to provide SDB structure for level-II scaling. At the same time,
competitive rules provides additional design flexibility of cell
architecture for better routability in terms of level-III scaling.
Besides technology innovation of friendly rules, pin can be drawn
intentionally large enough with wider metal layer, so that standard
cell is well picked up by place-and-routing tool. However, large pin
increases parasitic capacitance by degrading performance as a
trade-off with block scaling. Therefore, the best design technique is
to implement cell architecture with the minimum overhead through
DTCO. Pin is implemented as small as possible for low-power, and
extended as needed during place-and-routing for high-density.
Since standard cell is a major design element that accounts for Fig. 7. SRAM area portion breakdown of bitcell array, peripheral,
more than 50% of SoC area, cell-to-block DTCO is crucial for the and bitcell-to-peripheral interface.
competiveness of technology and design.

DTCO for SRAM scaling

SRAM is a major macro IP that accounts for more than 30% area of
SoC design. Therefore, there have been many research and
approaches to reduce SRAM area through innovative design-rule
optimization. Figure 6 shows SRAM area trend for bitcell and
peripheral [7]. SRAM bitcell was much smaller than peripheral in
legacy technologies. However, the recent advanced technology has
shrunk peripheral area with competitive design rule, which was
accelerated by extreme-ultraviolat (EUV) technology [7]. Peripheral
repair is proposed to improve logic yield in addition to bitcell repair
at the early stage of technology development.
Figure 7 shows SRAM area breakdown with bitcell, peripheral, and
bitcell-to-peripheral interface. While bitcell is designed to store data
effieciently with the help of technology scaling, peripheral is
designed to implement the functionality of wordline, write-driver,
and sense-amplifier based on logic design rule. There is remaining
part of bitcell-to-peripheral interface region as shown in Figure 7.
Bitcell-to-peripheral interface supports the pattern protection where
bitcell and peripheral meet with different shape of patterning. As
technology advances, bitcell and peripheral scale down
proportionally, but bitcell-to-peripheral interface does not shrink
proportionally. Therefore, SRAM DTCO is important to optimize
bitcell-to-peripheral interface in an advanced technology.
Meanwhile, SRAM area is considered in a different way regarding
bitcell usage of high-density (HD) and high-performance (HP) in
SoC design.
Figure 8 shows the effective SRAM PPA analysis for HD and HP
bitcell. Intrinsically, HP bitcell is larger than HD bitcell by about 20%.
However, HD bitcell requires additional assist to meet the minimum
operating voltage (VMIN) by increasing area. Moreover, since HD
bitcell is slower than HP bitcell, the effective area gain of HD SRAM
bitcell is variant according to PPA target of SoC design. SRAM
DTCO focuses on designing the optimum SRAM assist circuit to
minimize area or speed penalty by meeting VMIN target [8].
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Fig. 8. Effective SRAM PPA analysis for HD and HP bitcell [8]. HD
bitcell shows high-density and low-power at low-speed comparing
to HP bitcell.
DTCO for low-power
SoC level performance and power consumption are highly
correlated to each other. Since most design techniques for high-
performance are in the direction of increasing power, which use low
threshold voltage (VTH) device, high supply voltage, large transistor,
high track of standard cell. Therefore, high-performance should
trade-off power-consumption when legacy desing knobs are used.
As shown in Figure 1 (b), it is not easy to achieve high-performance
with low-power at the same time. One of efficient low-power
techniques is to use lower operating voltage (VOP) by meeting the
target frequency. Since power is reduced according to the equation
of C*VDD2, it is widely used as low-power technique. In order to
achieve low-power in SoC design more effectively, VMIN needs to be
lowered accordingly to enjoy low-power in wide range of supply
voltage. Technology capability such as transistor performance,
process variation, and VTH impact VMIN characteristics basically.
Then, design features of low-voltage layout and circuit techniques
also play an important role of supporting VMIN characteristics along
with technology.
 IEEE CICC 2022
Fig. 9. VOP, VTH, VMIN trend over technologies [8]. Design
headroom is lowered by VTH as VOP - VTH, and SRAM assist
recovers the reduced design headroom to support VMIN.
Fig. 10. SRAM assist scheme to help write and read operation by
changing bitcell power (VDDC), WL voltage, and BL voltage [8].
Since the sequential functionality is implemented in SRAM and F/F
of standard cell, VMIN of SoC depends on characteristics of SRAM
and F/F. Therefore, DTCO is applied to improve VMIN of SRAM and
F/F. Figure 9 shows SRAM VMIN trend regarding VOP, VTH over
technologies [8]. As technology advances, VOP has been decreased
for low-power. However, VTH reduces the design headroom
according to the equation of VOP - VTH. In order to provide additional
design headroom, various SRAM assist schemes are developed by
providing VMIN. Figure 10 shows various SRAM assist schemes to
improve read and write margin. Since SRAM assist schemes have
pros and cons with different PPA characteristics, various circuit and
layout architectures are developed to provide the optimum PPA in
addition to VMIN [7-12]. Since low-power SRAM and F/F are very
crucial to provide high-performance of SoC, and SRAM DTCO
should be applied to achieve the competitive PPA in the advanced
technologies.
DTCO for high-performance
Over a decade, FinFET technology has provided high-performance
solution comparing to Planar technology until GAA technology is
proposed recently. There have been literatures to optimize parasitic
resistance and capacitance through DTCO to make the best use of
transistor [7-9], [11]. Figure 11 (a) shows metal patterning difference
for uni- and bi-direction. EUV allows bi-directional metal with
patterning flexibility, while ArF supports uni-directional metal. In bi-
directional metal, sufficient VIA can be inserted between two layers
metals by placing them in the same direction.
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4
Fig. 11. (a) Uni-directional and bi-directional metal comparison. (b)
Bi-directional metal is designed by sufficient VIA to connect two
different metal layers in power-rail of standard cell [9].
Fig. 12. Dual-write driver (DWD) SRAM assist to reduce the
effective BL resistance [9].
Figure 11 (b) compares ring-oscillator delay according to additional
VIA distance in power-rail of standard cell. Power-rail of M1 and M2
reduces resistance by drawing two layers with more VIAs, which
improves performance of ring-oscillator. There is similar DTCO of
SRAM design to reduce metal resistance effectively. Figure 12
shows dual-write-driver (DWD) SRAM assist, which is developed to
reduce BL resistance by DWD [9]. By utilizing the parallel
resistance effect, DWD BL resistance is reduced by 75% ideally.
Write time and margin are also improved with the help of the
reduced BL resistance. Metal resistance plays more important role
in GAA technology, since transistor is faster, and suffers from metal
resistance effect more.
DTCO for 3nm GAA technology
GAA technology is proposed to provide PPA benefits by featuring (1)
small capacitance, (2) large effective channel width (Weff), and (3)
design flexibility. Therefore, DTCO knobs are applied to maximize
those features in 3nm GAA technology. Figure 13 (a) shows GAA
transistor structure comparing to FinFET. FinFET increases
transistor width by adding quantized Fin, which increases
performance by increasing capacitance digitally. However, GAA
increases transistor width linearly by increasing nanosheet.
Moreover, overlap capacitance of GAA transistor is relatively small
by the gentle slope comparing to FinFET thanks to transistor
structure.
5 IEEE CICC 2022
Fig. 13. Transistor structure comparison of FinFET and GAA
regarding overlap capacitance (Cov). GAA shows the smaller Cov
due to the benefit of 4-dimensional transistor structure [10].
Figure 13 (b) shows the comparison of overlap capacitance (COV)
for FinFET and GAA transistor over Weff. GAA design can be
optimized more easily for high-performance than FinFET because
GAA provides much larger current at the same COV. Otherwise, COV
of FinFET transistor is proportionally increased to fin number of
transistor, while COV of GAA transistor increases more gently as
Weff increases for high-performance and low-power. The second
benefit of GAA transistor is to provide large Weff at the same
footprint comparing to FinFET. Especially, large Weff is very
effective to improve low-voltage characteristics. Figure 14 shows
the effective resistance (Reff) over varying supply voltages. Reff is
defined as the summation of channel resistance (Rch) and external
resistance (Rext). Rch is dependent on VOP, while Rext is constant
over VOP, since Rext is defined by resistance of MOL, VIA, and
metal beside transistor channel. Rch of both FinFET and GAA
transisor increases as VOP is lowered by affecting Reff more in low-
voltage than nominal VOP. Since smaller Rch of GAA transistor
affects Rch more effectively in low-voltage range, GAA shows much
better performance than FinFET in low-voltage range. Reff features
are the motivations to focus on low-voltage characteristics of GAA
technology. According to literature [1], there is projection that VOP
can be reduced in GAA technology due to low-voltage features.
Meanwhile, since GAA transistor has large Weff with small Rch,
parasitic resistance impacts performance more sensitively in GAA
technology. Therefore, reducing resistance has become one of the
most critical DTCO activities in the 3nm GAA technology. GAA
design can adopt the design techniques to reduce the effective
metal resistance for high-performance [7], [10], [11].
GAA technology provides the third design benefit of design-
flexibility. In FinFET transistor, width is controlled by quantized Fin
number as explained before. Therefore, FinFET standard cell
supports limited PMOS/NMOS (P/N) ratio. On the other hand, GAA
transistor is minutely adjusted by changing various nanosheet to
meet necessary P/N ratio. Figure 15 shows P/N ratio comparison of
FinFET and GAA standard cell design. GAA shows more flexible
P/N ratio by supporing from large-skewed cell to unitary cell. Then,
the design flexibility of GAA provides more opportunities for timing
optimization in SoC design, because the flexible cell can be fine-
tuned and adopted in the sweet spot of design.
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Fig. 14. Transistor resistance analysis. (a) Reff is composed of
Rch and Rext, and Rch is decided by the channel characteristics.
(b) The smaller Rch of GAA is effective to reduce Reff in low-
voltage range comparing FinFET [10].
Fig. 15. PMOS/NMOS (P/N) ratio of FinFET and GAA [10]. GAA
allows different nanosheet width to design P/N ratio more flexibly.
SRAM enjoys the design flexibility of GAA technology for better
margin, since GAA allows various sizes for pass-gate (PG), pull-
down (PD), and pull-up (PU) transistors. Therefore, GAA can
optimize cell-stability and write-ability more easily. Moreover, GAA
SRAM bitcell has design flexibility to optimize low-power and high
performance more at the same footprint of FinFET SRAM bitcell.
Figure 16 shows GAA SRAM bitcell with various nanosheept width
for PG, PD, and PU such as 1:α:α or 1:a:b ratio of PU, PG, PD
transistors. In case of 1:α:α, large Weff of PG and PD improves
disturb margin, while 1:α:β improves disturb margin even more with
the help of increased PG:PD ratio. The improved read-margin
allows SRAM designer to focus on writeabilty, which provides more
flexibility to optimize write assist for better PPA. Figure 17 shows
SRAM VMIN comparison for high-density (HD) and high-current (HC)
of FinFET and GAA. GAA SRAM shows lower VMIN than FinFET for
HD and HC bitcell, which provides low-power and high-density
SRAM design options comparing to FinFET.
The design flexibility expands standard cell design as shown in
Figure 18 (a). GAA F/F can be sized more flexibly by sizing up
drivers, while feedback loop can be sized down for low-power and
stability. Therefore, F/F PPA can be improved more than the
intrinsic technology gain. Figure 18 (b) shows PPA projection for HD
and HP standard cell. Generally, HP standard cell provides high-
performance by sacrificing power and area for both FinFET and
GAA. However, DTCO can add additional PPA gain above
technology gain with small design overhead of power and area in
GAA.
 IEEE CICC 2022 6

Fig. 16. (a) GAA SRAM bitcell with various PU, PG, and PD
nanosheet size. (b) Iread and disturb margin comparison for
FinFET and GAA with different nanosheet width [10].

Fig. 18. (a) Flip-flop optimization with various nanosheet of GAA.

(b) PPA projection by using HD and HP design. GAA provides
DTCO to achieve high-performance by reducing power or area.

Fig. 17. SRAM bitcell VMIN of GAA and 7NM for HD and HC types.
GAA shows lower VMIN than 7NM, and HC shows much lower VMIN
than HD by sacrificing area [10].

Figure 19 shows PPA comparison of ring-oscillator for FinFET and

GAA standard cell. GAA standard cell is designed by four types of
nanosheet width comparing to single type Fin number of FinFET
standard cell. GAA optimize PPA more widely to provide higher-
performance or lower-power for the same footprint of design.
Moreover, GAA allows VOP lowering with lower VMIN, and it provides
much lower power for the same design.
DTCO optimizes power, performance, and area respectively.
However, the maximum PPA gain can be achieved by focusing on
the whole PPA at the same time [8]. Since performance trades off Fig. 19. High-speed and low-power solution by GAA technology by
power or area, vice versa, DTCO should find a way to optimize utilizing small capacitance, large Weff, various nanosheet width,
each PPA with the minimum penalty of other PPA. Then, DTCO is and lower VOP.
not limited to technology pitch or transistor, but extends to standard
cell, SRAM, and even SoC design. Therefore, SoC-level impact is Conclusion
analyzed to find the optimum PPA at the early stage of DTCO.
Advanced technologies have been developed to provide PPA
Figure 20 shows PPA circle with performance, power, and area benefits to designers. However, designers are facing more
impact on each other. Comparing to other technologies, 3nm GAA challenges to enjoy all the PPA benefits at the same time. In order
has more opportunity to improve PPA with the help of small to maximize technology-to-design benefits, various DTCO activities
capacitance, large Weff, and design flexibility. Large Weff makes should be developed from technology definition to SoC design.
high-perofrmance, and high-performance allows small standard cell
Recently, GAA technology is introduced to suggest small
to meet the target performance by making low-power. Low-power
capacitance, large Weff, and design-flexibility, which open new era
makes power-mesh simple to make high-density, which makes low- for high-density, low-power, and high-performance. DTCO are
power recursively. As shown in Figure 20, GAA supports PPA circle adopted from the previous advanced technology and developed
to achieve the optimum PPA gain of technology and design through newly to maximize the value of 3nm GAA technology.
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7 IEEE CICC 2022
Fig. 20. PPA circle with high-performance, low-power, and high-
density connection to impact each other in GAA technology.
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