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8051 Instructions
❖ 8051 instructions consist of 1 byte of opcode and 0 to 2 bytes of operands.
❖ The instructions use 8 bit register A, B, R0, R1, R2, R3, R4, R5, R6, R7 and also 16 bit
registers, DPTR (data pointer) and PC (program counter).
❖ The instructions (Total 111) of 8051 can be broadly classified under the following headings:
1. Data transfer instructions
2. Arithmetic instructions
3. Logical instructions
4. Branch instructions
5. Subroutine instructions
6. Bit manipulation (Boolean) instructions
✓ The following notations are used in the description of the instructions.
✓ Rn means, any of the eight registers (R0 to R7) in the selected banks.
✓ Ri means either of the pointing registers (R0 or R1) in the selected banks.
✓ M means internal data memory.
✓ E.D.M. means external data memory.
✓ P.M. means internal or external program memory DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

Data Transfer Instructions: Internal Data Memory (RAM)

❖ Table shows the instructions that are available for moving data around within the internal memory
spaces, and the addressing modes that can be used with each one with a 12 MHz clock, all of these
instructions execute in either 1 or 2 s.

A List of the MCS@-51 Data Transfer Instructions that Access Internal Data Memory Space.
DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA
Assuming 12MHz clock

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Data Transfer Instructions: External Data Memory (RAM)

❖ These data transfer instructions access external Data Memory. Only indirect addressing can be used.
❖ The choice is whether to use a one-byte address, @Ri where Ri can be either R0 or R1 of the selected
register bank, or a two-byte address, @DPTR.
❖ The disadvantage to using 16-bit addresses if only a few K bytes of external RAM are involved is that 16-
bit addresses use all 8 bits of Port 2 as address bus.
❖ On the other hand, 8-bit addresses allow one to address a few K bytes of RAM, without having to
sacrifice all of Port 2. Alf of these instructions execute in 2 s, with a 12 MHz clock.

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

A List of the MCS@-51 Data Transfer Instructions that access External Data Memory Space

Data Transfer Instructions: Look up tables in Program Memory (ROM)

❖ Table shows the two instructions that are available for reading lookup tables in Program
Memory. Since these instructions access only Program Memory, the lookup tables can only be
read, not updated. The mnemonic used is MOVC for “move constant”.
❖ If the table access is to external Program Memory, then the read strobe is PSEN.
❖ The first MOVC instruction in table can accommodate a table of up to 256 entries, numbered 0
through 255. The number of the desired entry is loaded into the Accumulator, and the Data
Pointer is setup to point to beginning of the table. Then MOVC A,@A+DPTR copies the
desired table entry into the Accumulator.

The MCS@-51 Lookup Table Read Instructions DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

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Data Transfer Instructions

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Data Transfer Instructions

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Data Transfer Instructions

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Data Transfer Instructions

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Data Transfer Instructions

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Data Transfer Instructions

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Data Transfer Instructions

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Data Transfer Instructions

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Data Transfer Instructions

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Data Transfer Instructions

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Data Transfer Instructions

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Data Transfer Instructions

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Data Transfer Instructions

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Data Transfer Instructions

Exchange the
digit

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Arithmetic Instructions

A List of the MCS@I-51 Arithmetic Instructions

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Arithmetic Instructions

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Arithmetic Instructions

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Arithmetic Instructions

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Arithmetic Instructions

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Arithmetic Instructions

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Arithmetic Instructions

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Arithmetic Instructions

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Arithmetic Instructions

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Arithmetic Instructions

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Arithmetic Instructions

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Arithmetic Instructions

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Arithmetic Instructions

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Arithmetic Instructions

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Arithmetic Instructions

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Logical Instructions

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

A list of the MCS@J-51Logical Instructions

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Logical Instructions

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Logical Instructions

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Logical Instructions

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Logical Instructions

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Logical Instructions

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Logical Instructions

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Logical Instructions

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Logical Instructions

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Logical Instructions

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Logical Instructions

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Logical Instructions

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Logical Instructions

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Logical Instructions

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Logical Instructions

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Boolean/BIT Manipulation Instructions

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Boolean/BIT Manipulation Instructions

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Boolean/BIT Manipulation Instructions

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Boolean/BIT Manipulation Instructions

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Boolean/BIT Manipulation Instructions

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Boolean/BIT Manipulation Instructions

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Boolean/BIT Manipulation Instructions

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Boolean/BIT Manipulation Instructions

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Boolean/BIT Manipulation Instructions

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Bit Addressable RAM

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Using BIT Directive

❖ The BIT directive is a directive to assign the bit-addressable I/O and RAM locations.
❖ It allows a program to assign the I/O or RAM bit at the beginning of the program, making
it easier to modify them.

❖ An LED is connected to pin P1.7. Write a program to toggle the LED forever.
LED BIT P1.7 ;using BIT directive
HERE: CPL LED ;toggle LED
LCALL DELAY ;delay
SJMP HERE ;repeat forever
❖ A switch is connected to pin P1.7 and an LED to pin P2.0. Write a program to get the
status of the switch and send it to the LED.
SW BIT P1.7 ;assign bit
LED BIT P2.0 ;assign bit
HERE: MOV C,SW ;get the bit from the port
MOV LED,C ;send the bit to the port
SJMP HERE ;repeat forever
DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

Jump Instruction's

❖ The table lists a single “JMP addr” instruction, but in fact there are three - SJMP, LJMP
and AJMP - which differ in the format of the destination address.
❖ JMP is a generic mnemonic which can be used if the programmer does not care which
way the jump is encoded.

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Conditional Jump instruction's

❖ Table shows the list of conditional jumps available to the MCS-51 user.
❖ All of these jumps specify the destination address by the relative offset method and so are
limited to a jump distance of –128 to +127 bytes from the instruction following the conditional
jump instruction.
❖ Important to note, however, the user specifies to the assembler the actual destination
address the same way as the other jump as a label or a 8-bit constant.

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Jump instruction's

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Jump instruction's

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Jump instruction's

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Jump instruction's

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Jump instruction's

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Jump instruction's

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Jump instruction's

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Jump instruction's

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Jump instruction's

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Jump instruction's

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Jump instruction's

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Jump instruction's

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Illustration of address computation

Using the following list file, verify the jump forward address calculation.
Line PC Opcode Mnemonic Operand
01 0000 ORG 0000
02 0000 78 00 MOV R0,#0
03 0002 74 55 MOV A,#55H
04 0004 60 03 JZ NEXT ; PC =PC+2 and then add displacement
05 0006 08 INC R0
06 0007 04 AGAIN: INC A
07 0008 04 INC A
08 0009 24 77 NEXT: ADD A,#77h
09 000B 50 05 JNC OVER ; PC =PC+2 and then add displacement
10 000D E4 CLR A
11 000E F8 MOV R0,A
12 000F F9 MOV R1,A
13 0010 FA MOV R2,A
14 0011 FB MOV R3,A
15 0012 2B OVER: ADD A,R3
16 0013 50 F2 JNC AGAIN; PC =PC+2 and add displacement(-0EH = F2H)
17 0015 80 FE HERE: SJMP HERE; PC =PC+2 and add displacement (-02H= FEH)
18 0017 END
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Example
Analyze the stack for the first LCALL instruction in the following program.
01 0000 ORG 0
02 0000 74 55 BACK: MOV A,#55H ;load A with 55H
03 0002 F5 90 MOV P1,A ;send 55H to port 1
04 0004 7C 99 MOV R4,#99H
05 0006 7D 67 MOV R5,#67H
06 0008 12 03 00 LCALL DELAY ;time delay
07 000B 74 AA MOV A,#0AAH ;load A with AA
08 000D F5 90 MOV P1,A ;send AAH to port 1
09 000F 12 03 00 LCALL DELAY
10 0012 80 EC SJMP BACK ;keep doing this
11 0014 ;————————this is the delay subroutine
12 0300 ORG 300H
13 0300 C0 04 DELAY: PUSH 4 ;PUSH R4
14 0302 C0 05 PUSH 5 ;PUSH R5
15 0304 7C FF MOV R4,#0FFH ;R4=FFH
16 0306 7D FF NEXT: MOV R5,#0FFH ;R5=255
17 0308 DD FE AGAIN: DJNZ R5,AGAIN
18 030A DC FA DJNZ R4,NEXT
19 030C D0 05 POP 5 ;POP into R5
20 030E D0 04 POP 4 ;POP into R4
21 0310 22 RET ;return to caller
22 0311 END ;end of asm file
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Example

❖ First notice that for the PUSH and POP instructions we must specify the
direct address of the register being pushed or popped. Here is the stack
frame.

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