A B C D E F G H

00
P2132-A01

M
NVG GK208 DDR3 64BIT

0
RD 17 SI
DVI-I/DVI-D + HDMI + VGA
1 1

TABLE OF CONTENTS
Page
1
Description
Table of Contents
(C 96 C
)2 7 ON
2 PCI EXPRESS
3 GPU FRAME BUFFER: PARTITION A
4 DDR3 Memories

0 F
5 DECOUPLING FOR CORE POWER_TOP

吳 15 jo ID
2 2

6 DACA VGA
7 IFPAB TMDS
8 IFPC HDMI

積 04 ne EN
9 UNSED IFPD, IFPE & IFPF
10 MISC INTERFACES
11 STRAPS & FAN

源 27 pe TI
12 POWER SUPPLY I: PEXVDD, 5V
13 POWER SUPPLY II: FBVDDQ
14 POWER SUPPLY III: NVVDD

01 i( AL
15 DECOUPLING FOR CORE POWER_BOTTOM
3 3

(0 裴
00 RM 亮
4

11 A工 樂 4

60 程 )
1) 課
5 5

NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY

ASSEMBLY BASE LEVEL GENERIC SCHEMATIC ONLY SANTA CLARA, CA 95050, USA
PAGE DETAIL Table of Contents
NV_PN 600-12132-BASE-QS1
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL PCB REV P2132-A01 PAGE 1 OF 15
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS. BOM REV A DATE 14-MAR-2013

A B C D E F G H
 A B C D E F G H

PCI EXPRESS

00
CN1
NONPHY-X8-75PIN
12V_PEX CON_X8
12V_PEX

M
TRUE COMMON
5.5A

0.6MM
C61 C62

0
12V B1 +12V
10UF 0.1UF
B2 +12V

RD 17 SI
16V 16V 3V3_PEX
A2 +12V
10% 10%
1 X5R X7R TRUE A3 +12V 1
1206 0402 3A B3 +12V/RSVD
COMMON COMMON 0.4MM

3.3V B8 +3V3
A9 +3V3
A10 +3V3
GND
SNN_3V3AUX B10 +3V3AUX

(C 96 C
3V3_PEX G1A
PEX_PRSNT A1 B5 PEX_SMCLK R110 0 I2CS_SCL
PRSNT1 SMCLK OUT
10

SMDAT B6 PEX_SMDAT 0402 +0.05R COMMON R103 0 I2CS_SDA 10 BGA595

BI COMMON
0402 +0.05R COMMON
C76
1/14 PCI_EXPRESS
4.7UF
6.3V GK208/GF117/GF119
20%
B4 SNN_PEX_WAKE_R* AB6 PEX_VDD

)2 7 ON
X5R GND PEX_WAKE NC
0603 A4 GND 0.1uF for PEX Gen2 default 1530mA GK208
COMMON B7 GND PEX_IOVDD AA22
A12 A11 PEX_RST* PEX_RST_R* AC7 AB23
GND PERST OUT
12 12
IN PEX_RST PEX_IOVDD
B13 AC24 C171 C170 C131 C128 C163 C172
GND GND PEX_IOVDD
SNN_PEX_CLKREQ* 1UF 1UF 4.7UF 10UF 22UF 22UF
A15 GND AC6 PEX_CLKREQ PEX_IOVDD AD25
NET_NAME DIFF_PAIR NV_NETCLASS 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
B16 GND PEX_IOVDD AE26
CLOSE TO CONNECTOR NV_NETCLASS DIFF_PAIR NET_NAME 10% 10% 20% 20% 20% 20%
B18 A13 PEX_REFCLK AE8 AE27
GND REFCLK PEX_REFCLK PEXGEN3_SIGNALS PEX_REFCLK PEX_IOVDD X5R X5R X5R X5R X5R X5R
NO STUFF DEFAULT PEX_REFCLK*
A18 GND REFCLK A14 PEX_REFCLK PEXGEN3_SIGNALS AD8 PEX_REFCLK 0402 0402 0603 0805 0805 0805

F
COMMON COMMON COMMON COMMON COMMON COMMON

0
PEX_TXX0 10% X7R PEX_TX0
PERP0 A16 PEX_TXX0 PEXGEN3_SIGNALS
0402 16V COMMON PEXGEN3_SIGNALS PEX_TXX0 AC9 PEX_TX0
A17 PEX_TXX0* C134 0.1UF C133 0.1UF PEX_TX0* AB9
PERN0 PEX_TXX0 PEXGEN3_SIGNALS PEXGEN3_SIGNALS PEX_TXX0 PEX_TX0
GND 0402 16V X7R COMMON
10%
B14 PEX_RX0 AG6

吳 15 jo ID
2 PETP0 PEX_RX0 PEXGEN3_SIGNALS PEX_RX0 GND 2
B15 PEX_RX0* AG7 AA10
END OF X1 PETN0 PEX_RX0 PEXGEN3_SIGNALS PEX_RX0 PEX_IOVDDQ
PEX_IOVDDQ AA12
A21 PEX_TXX1 0402 16V
10% X7R COMMON PEX_TX1 AB10 AA13 C132 C165 C164 C173 C129 C130
PERP1 PEX_TXX1 PEXGEN3_SIGNALS
C137 0.1UF
PEXGEN3_SIGNALS PEX_TXX1 PEX_TX1 PEX_IOVDDQ 1UF 1UF 4.7UF 10UF 22UF 22UF
A22 PEX_TXX1* C139 0.1UF PEX_TX1* AC10 AA16
PERN1 PEX_TXX1 PEXGEN3_SIGNALS PEXGEN3_SIGNALS PEX_TXX1 PEX_TX1 PEX_IOVDDQ 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
0402 16V
10% X7R COMMON
PEX_IOVDDQ AA18
10% 10% 20% 20% 20% 20%
B19 PEX_RX1 AF7 AA19
PETP1 PEX_RX1 PEXGEN3_SIGNALS PEX_RX1 PEX_IOVDDQ X5R X5R X5R X5R X5R X5R
B20 PEX_RX1* AE7 AA20 0402 0402 0603 0805 0805 0805
PETN1 PEX_RX1 PEXGEN3_SIGNALS PEX_RX1 PEX_IOVDDQ
A20 GND PEX_IOVDDQ AA21 COMMON COMMON COMMON COMMON COMMON COMMON
PEX_TXX2 10% PEX_TX2
A25 X7R AD11 AB22

積 04 ne EN
0402 16V COMMON
PERP2 PEX_TXX2 PEXGEN3_SIGNALS
C146 0.1UF
PEXGEN3_SIGNALS PEX_TXX2 PEX_TX2 PEX_IOVDDQ
B22 A26 PEX_TXX2* C147 0.1UF PEX_TX2* AC11 AC23
GND PERN2 PEX_TXX2 PEXGEN3_SIGNALS PEXGEN3_SIGNALS PEX_TXX2 PEX_TX2 PEX_IOVDDQ
0402 16V
10% X7R COMMON
PEX_IOVDDQ AD24
A24 B23 PEX_RX2 AE9 AE25 GND
GND PETP2 PEX_RX2 PEXGEN3_SIGNALS PEX_RX2 PEX_IOVDDQ
B24 PEX_RX2* AF9 AF26
PETN2 PEX_RX2 PEXGEN3_SIGNALS PEX_RX2 PEX_IOVDDQ PLACE CLOSE TO GPU OPTION
B26 GND PEX_IOVDDQ AF27
PEX_TXX3 10% X7R PEX_TX3
PERP3 A29 PEX_TXX3 PEXGEN3_SIGNALS
0402 16V COMMON PEXGEN3_SIGNALS PEX_TXX3 AC12 PEX_TX3
A28 A30 PEX_TXX3* C156 0.1UF C155 0.1UF PEX_TX3* AB12
GND PERN3 PEX_TXX3 PEXGEN3_SIGNALS PEXGEN3_SIGNALS PEX_TXX3 PEX_TX3
B29 GND 0402 16V
10% X7R COMMON

源 27 pe TI
A31 B27 PEX_RX3 AG9
GND PETP3 PEX_RX3 PEXGEN3_SIGNALS PEX_RX3
B32 B28 PEX_RX3* AG10
GND END OF X4 PETN3 PEX_RX3 PEXGEN3_SIGNALS PEX_RX3
PEX_TXX4 10% PEX_TX4
PERP4 A35 PEX_TXX4 PEXGEN3_SIGNALS
0402 16V X7R COMMON PEXGEN3_SIGNALS PEX_TXX4 AB13 PEX_TX4
CON_PCI_EXPRESS
A36 PEX_TXX4* C162 0.1UF C160 0.1UF PEX_TX4* AC13
GND PERN4 PEX_TXX4 PEXGEN3_SIGNALS PEXGEN3_SIGNALS PEX_TXX4 PEX_TX4
B48 PRSNT2 0402 16V
10% X7R COMMON
B33 PEX_RX4 AF10
PETP4 PEX_RX4 PEXGEN3_SIGNALS PEX_RX4
B34 PEX_RX4* AE10
PETN4 PEX_RX4 PEXGEN3_SIGNALS PEX_RX4
A34 GND 3V3_PLL

01 i( AL
PEX_TXX5 10% X7R PEX_TX5
PERP5 A39 PEX_TXX5 PEXGEN3_SIGNALS
0402 16V COMMON PEXGEN3_SIGNALS PEX_TXX5 AD14 PEX_TX5
B36 A40 PEX_TXX5* C167 0.1UF C166 0.1UF PEX_TX5* AC14 AA8 0.189 Amps GK208
GND PERN5 PEX_TXX5 PEXGEN3_SIGNALS PEXGEN3_SIGNALS PEX_TXX5 PEX_TX5 PEX_PLL_HVDD
0402 16V
10% X7R COMMON
PEX_PLL_HVDD AA9
A38 B37 PEX_RX5 AE12
3 GND PETP5 PEX_RX5 PEXGEN3_SIGNALS PEX_RX5 3
B38 PEX_RX5* AF12
PETN5 PEX_RX5 PEXGEN3_SIGNALS PEX_RX5
B40 GND PEX_SVDD_3V3 AB8
PEX_TXX6 10% PEX_TX6
PERP6 A43 PEX_TXX6 PEXGEN3_SIGNALS
0402 16V X7R COMMON PEXGEN3_SIGNALS PEX_TXX6 AC15 PEX_TX6
A42 A44 PEX_TXX6* C169 0.1UF C168 0.1UF PEX_TX6* AB15
GND PERN6 PEX_TXX6 PEXGEN3_SIGNALS PEXGEN3_SIGNALS PEX_TXX6 PEX_TX6
0402 16V X7R COMMON
10%
B44 B41 PEX_RX6 AG12

(0
GND PETP6 PEX_RX6 PEXGEN3_SIGNALS PEX_RX6
B42 PEX_RX6* AG13
PETN6 PEX_RX6 PEXGEN3_SIGNALS PEX_RX6

裴
A46 GND
PEX_TXX7 10% PEX_TX7
B47 GND PERP7 A47 PEX_TXX7 PEXGEN3_SIGNALS
0402 16V X7R COMMON PEXGEN3_SIGNALS PEX_TXX7 AB16 PEX_TX7
B49 A48 PEX_TXX7* C175 0.1UF C174 0.1UF PEX_TX7* AC16
GND PERN7 PEX_TXX7 PEXGEN3_SIGNALS PEXGEN3_SIGNALS PEX_TXX7 PEX_TX7
A49 GND 0402 16V
10% X7R COMMON
B45 PEX_RX7 AF13
PETP7 PEX_RX7 PEXGEN3_SIGNALS PEX_RX7
B46 PEX_RX7* AE13
END OF X8 PETN7 PEX_RX7 PEXGEN3_SIGNALS PEX_RX7

00 RM 亮
GND SNN_PEX_TX8 AD17 PEX_TX8 NC
SNN_PEX_TX8* AC17 PEX_TX8 NC
SNN_PEX_RX8 AE15 PEX_RX8 NC
SNN_PEX_RX8* AF15 PEX_RX8 NC
SNN_PEX_TX9 AC18 F2 NVVDD_SENSE
PEX_TX9 NC VDD_SENSE OUT
14
SNN_PEX_TX9* AB18 PEX_TX9 NC

11 A工 樂
SNN_PEX_RX9 AG15 F1 SNN_GND_SENSE
PEX_RX9 NC GND_SENSE
SNN_PEX_RX9* AG16 PEX_RX9 NC
SNN_PEX_TX10 AB19 PEX_TX10 NC
SNN_PEX_TX10* AC19 PEX_TX10 NC

4
SNN_PEX_RX10 AF16 PEX_RX10 NC 4
SNN_PEX_RX10* AE16 PEX_RX10 NC

60
SNN_PEX_TX11 AD20 PEX_TX11 NC

)
SNN_PEX_TX11* AC20 PEX_TX11 NC
SNN_PEX_RX11 AE18 PEX_RX11

程
NC
SNN_PEX_RX11* AF18 PEX_RX11 NC
SNN_PEX_TX12 AC21 PEX_TX12 NC
SNN_PEX_TX12* AB21 PEX_TX12 NC

1)
SNN_PEX_RX12 AG18 AF22 SNN_PEX_TSTCLK_OUT
PEX_RX12 NC PEX_TSTCLK_OUT
SNN_PEX_RX12* AG19 AE22 SNN_PEX_TSTCLK_OUT* PEX_VDD
PEX_RX12 NC PEX_TSTCLK_OUT
SNN_PEX_TX13 AD23 PEX_PLLVDD R147 0

課
PEX_TX13 NC
SNN_PEX_TX13* AE23 0603 +0.05R COMMON
PEX_TX13 NC 1.05V
C161 C159 C157 C158
0.130 Amps GK208 0.1UF 1UF 4.7UF 10UF
SNN_PEX_RX13 AF19 PEX_RX13 NC PEX_PLLVDD AA14
16V 6.3V 6.3V 6.3V
SNN_PEX_RX13* AE19 PEX_RX13 NC PEX_PLLVDD AA15
10% 10% 20% 20%
X7R X5R X5R X5R
SNN_PEX_TX14 AF24 0402 0402 0603 0805
PEX_TX14 NC
SNN_PEX_TX14* AE24 COMMON COMMON COMMON COMMON
PEX_TX14 NC
SNN_PEX_RX14 AE21 PEX_RX14 NC
SNN_PEX_RX14* AF21 PEX_RX14 NC
AD9 GPU_TESTMODE R139 10K GND
TESTMODE GND
SNN_PEX_TX15 AG24 0402 5% COMMON
PEX_TX15 NC
SNN_PEX_TX15* AG25 PEX_TX15 NC PLACE CLOSE TO GPU

5
SNN_PEX_RX15 AG21 PEX_RX15 NC 5
SNN_PEX_RX15* AG22 PEX_RX15 NC

GF119 GF117
AF25 PEX_TERMP R152 2.49K
GK208 PEX_TERMP GND
0402 COMMON
1%
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY

ASSEMBLY BASE LEVEL GENERIC SCHEMATIC ONLY SANTA CLARA, CA 95050, USA
PAGE DETAIL PCI EXPRESS
NV_PN 600-12132-BASE-QS1
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL PCB REV P2132-A01 PAGE 2 OF 15
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS. BOM REV A DATE 14-MAR-2013

A B C D E F G H
 A B C D E F G H

GPU FRAME BUFFER: PARTITION A

00 M
0
RD 17 SI
1 G1B 1
BGA595
COMMON

2/14 FBA
FBA_D<0> E18 F3 FB_CLAMP
4,5
BI FBA_D0 NC FB_CLAMP
4,5 FBA_D<1> F18 FBA_D1
BI R130
4,5 FBA_D<2> E16 FBA_D2 GF119 GF117/GK208
BI 10K
F17

(C 96 C
4,5 FBA_D<3> FBA_D3
BI 5%
4,5 FBA_D<4> D20 FBA_D4 0402
BI
4,5 FBA_D<5> D21 FBA_D5 COMMON
BI
4,5 FBA_D<6> F20 FBA_D6
BI
4,5 FBA_D<7> E21 FBA_D7
BI
4,5 FBA_D<8> E15 FBA_D8
BI
4,5 FBA_D<9> D15 FBA_D9
BI
4,5 FBA_D<10> F15 FBA_D10 GND
BI
F13

)2 7 ON
4,5 FBA_D<11> FBA_D11
BI
4,5 FBA_D<12> C13 FBA_D12
BI
4,5 FBA_D<13> B13 FBA_D13
BI
4,5 FBA_D<14> E13 FBA_D14
BI
4,5 FBA_D<15> D13 FBA_D15
BI
4,5 FBA_D<16> B15 FBA_D16
BI
4,5 FBA_D<17> C16 FBA_D17
BI PD REQUIRED FOR INITIALIZATION
4,5 FBA_D<18> A13 FBA_D18
BI
4,5 FBA_D<19> A15 FBA_D19
BI

F
FBA_D<20> B18 FBA_CMD<0> FBA_CMD<3>
4,5 FBA_D20

0
BI
4,5 FBA_D<21> A18 FBA_D21
BI R160 R157
4,5 FBA_D<22> A19 FBA_D22
BI 10K 10K
4,5 FBA_D<23> C19 FBA_D23
BI LOWER CHANNEL 5% LOWER CHANNEL 5%
FBA_D<24> B24

吳 15 jo ID
2 4,5
BI FBA_D24 0402 0402 2
ODT CKE
4,5 FBA_D<25> C23 FBA_D25 COMMON COMMON
BI
4,5 FBA_D<26> A25 FBA_D26
BI
4,5 FBA_D<27> A24 FBA_D27
BI
4,5 FBA_D<28> A21 FBA_D28
BI
4,5 FBA_D<29> B21 FBA_D29 GND GND
BI
4,5 FBA_D<30> C20 FBA_D30
BI
4,5 FBA_D<31> C21 FBA_D31
BI
FBA_D<32> R22 FBA_CMD<16> FBA_CMD<19>
4,5
BI FBA_D32
R24 C27 FBA_CMD<0>

積 04 ne EN
4,5 FBA_D<33> FBA_D33 FBA_CMD0 4,5
BI BI R161 R158
FBA_D<34> T22 C26 SNN_FBA_CMD1
4,5
BI FBA_D34 FBA_CMD1 10K 10K
FBA_D<35> R23 E24 FBA_CMD<2>
4,5
BI FBA_D35 FBA_CMD2 BI
4,5
5% 5%
FBA_CMD<3> UPPER CHANNEL UPPER CHANNEL
4,5 FBA_D<36> N25 FBA_D36 FBA_CMD3 F24 4,5
0402 0402
BI BI ODT CKE
FBA_D<37> N26 D27 FBA_CMD<4>
4,5
BI FBA_D37 FBA_CMD4 BI
4,5 COMMON COMMON
FBA_D<38> N23 D26 FBA_CMD<5>
4,5
BI FBA_D38 FBA_CMD5 BI
4,5
FBA_D<39> N24 F25 FBA_CMD<6>
4,5
BI FBA_D39 FBA_CMD6 BI
4,5
FBA_D<40> V23 F26 FBA_CMD<7>
4,5
BI FBA_D40 FBA_CMD7 BI
4,5
FBA_D<41> V22 F23 FBA_CMD<8> GND GND
4,5
BI FBA_D41 FBA_CMD8 BI
4,5

源 27 pe TI
FBA_D<42> T23 G22 FBA_CMD<9>
4,5
BI FBA_D42 FBA_CMD9 BI
4,5
FBA_D<43> U22 G23 FBA_CMD<10>
4,5
BI FBA_D43 FBA_CMD10 BI
4,5
FBA_D<44> Y24 G24 FBA_CMD<11> FBA_CMD<20>
4,5
BI FBA_D44 FBA_CMD11 BI
4,5
FBA_D<45> AA24 F27 FBA_CMD<12>
4,5
BI FBA_D45 FBA_CMD12 BI
4,5
R163
FBA_D<46> Y22 G25 FBA_CMD<13>
4,5
BI FBA_D46 FBA_CMD13 BI
4,5
10K
FBA_D<47> AA23 G27 FBA_CMD<14>
4,5
BI FBA_D47 FBA_CMD14 BI
4,5
5%
FBA_CMD<15> RST
4,5 FBA_D<48> AD27 FBA_D48 FBA_CMD15 G26 4,5
0402
BI BI
FBA_D<49> AB25 M24 FBA_CMD<16>
4,5
BI FBA_D49 FBA_CMD16 BI
4,5 COMMON
FBA_D<50> AD26 M23 SNN_FBA_CMD17
4,5 FBA_D50 FBA_CMD17

01 i( AL
BI
FBA_D<51> AC25 K24 FBA_CMD<18>
4,5
BI FBA_D51 FBA_CMD18 BI
4,5
FBA_D<52> AA27 K23 FBA_CMD<19>
4,5
BI FBA_D52 FBA_CMD19 BI
4,5
FBA_D<53> AA26 M27 FBA_CMD<20> GND
4,5
BI FBA_D53 FBA_CMD20 BI
4,5
FBA_D<54> W26 M26 FBA_CMD<21>
3 4,5
BI FBA_D54 FBA_CMD21 BI
4,5
3
FBA_D<55> Y25 M25 FBA_CMD<22>
4,5
BI FBA_D55 FBA_CMD22 BI
4,5
FBA_D<56> R26 K26 FBA_CMD<23>
4,5
BI FBA_D56 FBA_CMD23 BI
4,5
FBA_D<57> T25 K22 FBA_CMD<24>
4,5
BI FBA_D57 FBA_CMD24 BI
4,5
FBA_D<58> N27 J23 FBA_CMD<25>
4,5
BI FBA_D58 FBA_CMD25 BI
4,5
FBA_D<59> R27 J25 FBA_CMD<26>
4,5
BI FBA_D59 FBA_CMD26 BI
4,5
V26 J24 FBA_CMD<27>

(0
4,5 FBA_D<60> FBA_D60 FBA_CMD27 4,5
BI BI
FBA_D<61> V27 K27 FBA_CMD<28>
4,5
BI FBA_D61 FBA_CMD28 BI
4,5

裴
FBA_D<62> W27 K25 FBA_CMD<29>
4,5
BI FBA_D62 FBA_CMD29 BI
4,5
FBA_D<63> W25 J27 FBA_CMD<30>
4,5
BI FBA_D63 FBA_CMD30 BI
4,5
J26 SNN_FBA_CMD31
FBA_CMD31
CLK Termination
4,5 FBA_DQM<0> D19 FBA_DQM0
BI
4,5 FBA_DQM<1> D14 FBA_DQM1
BI
4,5 FBA_DQM<2> C17 FBA_DQM2

00 RM 亮
BI
4,5 FBA_DQM<3> C22 FBA_DQM3
BI
FBA_DQM<4> P24 FBA_CLK0
4,5
BI FBA_DQM4 3,4,4
IN
4,5 FBA_DQM<5> W24 FBA_DQM5
BI R155
4,5 FBA_DQM<6> AA25 FBA_DQM6
BI
SNN_FBA_DEBUG0 80.6
4,5 FBA_DQM<7> U25 FBA_DQM7 FBA_DEBUG0 F22
BI 1%
J22 SNN_FBA_DEBUG1
FBA_DEBUG1 0402
COMMON
FBA_DQS_WP<0> E19 FBA_CLK0*
4,5
BI FBA_DQS_WP0 3,4,4
IN
FBA_DQS_WP<1> C15 NET_NAME DIFF_PAIR NV_NETCLASS

11 A工 樂
4,5
BI FBA_DQS_WP1
FBA_DQS_WP<2> B16 D24 FBA_CLK0
4,5
BI FBA_DQS_WP2 FBA_CLK0 FBA_CLK0 FB_CLK OUT
3,4,4
FBA_DQS_WP<3> B22 D25 FBA_CLK0*
4,5
BI FBA_DQS_WP3 FBA_CLK0 FBA_CLK0 FB_CLK
OUT
3,4,4
FBA_DQS_WP<4> R25 N22 FBA_CLK1
4,5
BI FBA_DQS_WP4 FBA_CLK1 FBA_CLK1 FB_CLK
OUT
3,4,4
FBA_DQS_WP<5> W23 M22 FBA_CLK1*
4,5
BI FBA_DQS_WP5 FBA_CLK1 FBA_CLK1 FB_CLK
OUT
3,4,4

4,5 FBA_DQS_WP<6>AB26 FBA_DQS_WP6

BI
4,5 FBA_DQS_WP<7> T26 FBA_DQS_WP7
BI
4 4

FBA_DQS_RN<0> F19 D18 SNN_FBA_WCK01

FBA_DQS_RN0 FBA_WCK01

60
4,5
BI
FBA_DQS_RN<1> C14 C18 SNN_FBA_WCK01*
4,5
BI FBA_DQS_RN1 FBA_WCK01

)
FBA_DQS_RN<2> A16 D17 SNN_FBA_WCK23
4,5
BI FBA_DQS_RN2 FBA_WCK23
FBA_DQS_RN<3> A22 D16 SNN_FBA_WCK23* FBA_CLK1
4,5
BI FBA_DQS_RN3 FBA_WCK23 3,4,4
IN
FBA_DQS_RN<4> P25 T24 SNN_FBA_WCK45
4,5 FBA_DQS_RN4 FBA_WCK45

程
BI R156
FBA_DQS_RN<5> W22 U24 SNN_FBA_WCK45*
4,5
BI FBA_DQS_RN5 FBA_WCK45 80.6
FBA_DQS_RN<6> AB27 V24 SNN_FBA_WCK67
4,5
BI FBA_DQS_RN6 FBA_WCK67 1%
FBA_DQS_RN<7> T27 V25 SNN_FBA_WCK67*
4,5
BI FBA_DQS_RN7 FBA_WCK67 0402
COMMON
FBA_CLK1*

1)
3,4,4
IN

FB_PLLAVDD F16 1V_PLL

P22

課
FB_PLLAVDD

FB_PLLAVDD FB_DLLAVDD H22

GF117 GF119/GK208

SNN_FB_VREF D23 FB_VREF_PROBE

5 5

NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY

ASSEMBLY BASE LEVEL GENERIC SCHEMATIC ONLY SANTA CLARA, CA 95050, USA
PAGE DETAIL GPU FRAME BUFFER: PARTITION A
NV_PN 600-12132-BASE-QS1
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL PCB REV P2132-A01 PAGE 3 OF 15
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS. BOM REV A DATE 14-MAR-2013

A B C D E F G H
 A B C D E F G H

DDR3 Memories

00 M
0
RD 17 SI
M1C M2B M3B M4B

1 FBGA96 FBGA96 CMD MAPPING FBGA96 FBGA96 1

CMD MAPPING BGA100 FBVDDQ BGA100 FBVDDQ BGA100 FBVDDQ BGA100 FBVDDQ
<31..0> <63..32>
COMMON COMMON COMMON COMMON
<31..0> <63..32> ODT
FBA_CMD<11> J3 B2 FBA_CMD<11> J3 B2 CMD0 FBA_CMD<11> J3 B2 FBA_CMD<11> J3 B2
4,5
BI RAS VDD 4,5
BI RAS VDD 4,5
BI RAS VDD 4,5
BI RAS VDD
CMD0 ODT FBA_CMD<15> FBA_CMD<15> CMD1 FBA_CMD<15> FBA_CMD<15>
4,5 K3 CAS VDD D9 4,5 K3 CAS VDD D9 4,5 K3 CAS VDD D9 4,5 K3 CAS VDD D9
CMD1 BI BI CMD2 CS0* BI BI
FBA_CMD<28> L3 G7 FBA_CMD<28> L3 G7 FBA_CMD<28> L3 G7 FBA_CMD<28> L3 G7
4,5
BI WE VDD 4,5
BI WE VDD CMD3 CKE
4,5
BI WE VDD 4,5
BI WE VDD
CMD2 CS0* FBA_CMD<2> FBA_CMD<2> FBA_CMD<18> FBA_CMD<18>
4,5 L2 CS/CS0 VDD K2 4,5 L2 CS/CS0 VDD K2 4,5 L2 CS/CS0 VDD K2 4,5 L2 CS/CS0 VDD K2
CMD3 CKE BI BI CMD4 A9 A9 BI BI
VDD K8 VDD K8 VDD K8 VDD K8
CMD4 A9 A9 FBA_CMD<7> FBA_CMD<7> CMD5 A6 A6 FBA_CMD<7> FBA_CMD<7>
N3 N1 N3 N1 N3 N1 N3 N1

(C 96 C
CMD5 A6 A6
4,5
BI A0 VDD 4,5
BI A0 VDD CMD6 A3 A3
4,5
BI A0 VDD 4,5
BI A0 VDD
FBA_CMD<10> P7 N9 FBA_CMD<10> P7 N9 FBA_CMD<10> P7 N9 FBA_CMD<10> P7 N9
CMD6 A3 A3
4,5
BI A1 VDD 4,5
BI A1 VDD CMD7 A0 A0
4,5
BI A1 VDD 4,5
BI A1 VDD
FBA_CMD<24> P3 R1 FBA_CMD<24> P3 R1 FBA_CMD<24> P3 R1 FBA_CMD<24> P3 R1
CMD7 A0 A0
4,5
BI A2 VDD 4,5
BI A2 VDD CMD8 A8 A8
4,5
BI A2 VDD 4,5
BI A2 VDD
FBA_CMD<6> N2 R9 FBA_CMD<6> N2 R9 FBA_CMD<6> N2 R9 FBA_CMD<6> N2 R9
CMD8 A8 A8 4,5
BI A3 VDD 4,5
BI A3 VDD CMD9 A12 A12 4,5
BI A3 VDD 4,5
BI A3 VDD
FBA_CMD<22> P8 FBA_CMD<22> P8 FBA_CMD<22> P8 FBA_CMD<22> P8
CMD9 A12 A12 4,5
BI A4 4,5
BI A4 CMD10 A1 A1 4,5
BI A4 4,5
BI A4
FBA_CMD<26> P2 FBA_CMD<26> P2 FBA_CMD<26> P2 FBA_CMD<26> P2
CMD10 A1 A1 4,5
BI A5 4,5
BI A5 CMD11 RAS* RAS* 4,5
BI A5 4,5
BI A5
FBA_CMD<5> R8 FBA_CMD<5> R8 FBA_CMD<5> R8 FBA_CMD<5> R8
CMD11 RAS* RAS* 4,5
BI A6 4,5
BI A6 CMD12 A13 A13 4,5
BI A6 4,5
BI A6
FBA_CMD<21> R2 A1 FBA_CMD<21> R2 A1 FBA_CMD<21> R2 A1 FBA_CMD<21> R2 A1
CMD12 A13 A13 4,5
BI A7 VDDQ 4,5
BI A7 VDDQ CMD13 BA1 BA1 4,5
BI A7 VDDQ 4,5
BI A7 VDDQ
FBA_CMD<8> T8 A8 FBA_CMD<8> T8 A8 FBA_CMD<8> T8 A8 FBA_CMD<8> T8 A8

)2 7 ON
CMD13 BA1 BA1 4,5
BI A8 VDDQ 4,5
BI A8 VDDQ CMD14 A14 A14 4,5
BI A8 VDDQ 4,5
BI A8 VDDQ
FBA_CMD<4> R3 C1 FBA_CMD<4> R3 C1 FBA_CMD<4> R3 C1 FBA_CMD<4> R3 C1
CMD14 A14 A14 4,5
BI A9 VDDQ 4,5
BI A9 VDDQ CMD15 CAS* CAS* 4,5
BI A9 VDDQ 4,5
BI A9 VDDQ
FBA_CMD<25> L7 C9 FBA_CMD<25> L7 C9 CMD16 ODT FBA_CMD<25> L7 C9 FBA_CMD<25> L7 C9
CMD15 CAS* CAS* 4,5
BI A10/AP VDDQ 4,5
BI A10/AP VDDQ 4,5
BI A10/AP VDDQ 4,5
BI A10/AP VDDQ
CMD16 ODT FBA_CMD<23> R7 D2 FBA_CMD<23> R7 D2 CMD17 FBA_CMD<23> R7 D2 FBA_CMD<23> R7 D2
4,5
BI A11 VDDQ 4,5
BI A11 VDDQ 4,5
BI A11 VDDQ 4,5
BI A11 VDDQ
CMD17 FBA_CMD<9> N7 E9 FBA_CMD<9> N7 E9 CMD18 CS0* FBA_CMD<9> N7 E9 FBA_CMD<9> N7 E9
4,5
BI A12/BC VDDQ 4,5
BI A12/BC VDDQ 4,5
BI A12/BC VDDQ 4,5
BI A12/BC VDDQ
CMD18 CS0* FBA_CMD<12> T3 F1 FBA_CMD<12> T3 F1 CMD19 CKE FBA_CMD<12> T3 F1 FBA_CMD<12> T3 F1
4,5
BI A13 VDDQ 4,5
BI A13 VDDQ 4,5
BI A13 VDDQ 4,5
BI A13 VDDQ
CMD19 CKE FBA_CMD<14> T7 H2 FBA_CMD<14> T7 H2 CMD20 RST RST FBA_CMD<14> T7 H2 FBA_CMD<14> T7 H2
4,5
BI A14 VDDQ 4,5
BI A14 VDDQ 4,5
BI A14 VDDQ 4,5
BI A14 VDDQ
CMD20 RST RST FBA_CMD<30> M7 H9 FBA_CMD<30> M7 H9 CMD21 A7 A7 FBA_CMD<30> M7 H9 FBA_CMD<30> M7 H9
4,5
BI 30 A15/BA3 VDDQ 4,5
BI 30 A15/BA3 VDDQ 4,5
BI 30 A15/BA3 VDDQ 4,5
BI 30 A15/BA3 VDDQ
CMD21 A7 A7 CMD22 A4 A4

F
CMD22 A4 A4 CMD23 A11 A11

0
CMD23 A11 A11 CMD24 A2 A2
CMD24 A2 A2 CMD25 A10 A10
CMD25 A10 A10 CMD26 A5 A5
CMD26 A5 A5 CMD27 BA2 BA2

吳 15 jo ID
2 CMD27 BA2 BA2 FBA_CMD<29> FBA_CMD<29> CMD28 WE* WE* FBA_CMD<29> FBA_CMD<29>
2
4,5 M2 BA0 4,5 M2 BA0 4,5 M2 BA0 4,5 M2 BA0
CMD28 WE* WE* BI BI CMD29 BA0 BA0 BI BI
FBA_CMD<13> N8 FBA_CMD<13> N8 FBA_CMD<13> N8 FBA_CMD<13> N8
CMD29 BA0 BA0
4,5
BI BA1 4,5
BI BA1 CMD30 A15 A15
4,5
BI BA1 4,5
BI BA1
FBA_CMD<27> M3 FBA_CMD<27> M3 FBA_CMD<27> M3 FBA_CMD<27> M3
CMD30 A15 A15
4,5
BI BA2 4,5
BI BA2 4,5
BI BA2 4,5
BI BA2
VSSQ B1 VSSQ B1 VSSQ B1 VSSQ B1
FBA_CMD<3> K9 B9 FBA_CMD<3> K9 B9 FBA_CMD<19> K9 B9 FBA_CMD<19> K9 B9
4,5
BI CKE/CKE0 VSSQ 4,5
BI CKE/CKE0 VSSQ 4,5
BI CKE/CKE0 VSSQ 4,5
BI CKE/CKE0 VSSQ
FBA_CLK0 J7 D1 FBA_CLK0 J7 D1 FBA_CLK1 J7 D1 FBA_CLK1 J7 D1
3,3,4
IN CLK VSSQ 3,3,4
IN CLK VSSQ 3,3,4
IN CLK VSSQ 3,3,4
IN CLK VSSQ
FBA_CLK0* K7 D8 FBA_CLK0* K7 D8 FBA_CLK1* K7 D8 FBA_CLK1* K7 D8
3,3,4
IN CLK VSSQ 3,3,4
IN CLK VSSQ 3,3,4
IN CLK VSSQ 3,3,4
IN CLK VSSQ
VSSQ E2 VSSQ E2 VSSQ E2 VSSQ E2
E8 E8 E8 E8

積 04 ne EN
VSSQ VSSQ VSSQ VSSQ
VSSQ F9 VSSQ F9 VSSQ F9 VSSQ F9
SNN_FBA1_NC_J2 J1 NC/ODT1 G1 SNN_FBA2_NC_J2 J1 NC/ODT1 G1 SNN_FBA3_NC_J2 J1 NC/ODT1 G1 SNN_FBA4_NC_J2 J1 NC/ODT1 G1
VSSQ VSSQ VSSQ VSSQ
SNN_FBA1_NC_J10 J9 NC/CKE1 G9 SNN_FBA2_NC_J10 J9 NC/CKE1 G9 SNN_FBA3_NC_J10 J9 NC/CKE1 G9 SNN_FBA4_NC_J10 J9 NC/CKE1 G9
VSSQ VSSQ VSSQ VSSQ
SNN_FBA1_NC_L2 L1 NC/CS1 SNN_FBA2_NC_L2 L1 NC/CS1 SNN_FBA3_NC_L2 L1 NC/CS1 SNN_FBA4_NC_L2 L1 NC/CS1
SNN_FBA1_NC_L10 L9 NC/ZQ1 SNN_FBA2_NC_L10 L9 NC/ZQ1 SNN_FBA3_NC_L10 L9 NC/ZQ1 SNN_FBA4_NC_L10 L9 NC/ZQ1

VSS A9 VSS A9 VSS A9 VSS A9

VSS B3 VSS B3 VSS B3 VSS B3

源 27 pe TI
VSS E1 VSS E1 VSS E1 VSS E1
VSS G8 VSS G8 VSS G8 VSS G8
VSS J2 VSS J2 VSS J2 VSS J2
VSS J8 VSS J8 VSS J8 VSS J8
VSS M1 VSS M1 VSS M1 VSS M1
FBA_CMD<20> T2 M9 FBA_CMD<20> T2 M9 FBA_CMD<20> T2 M9 FBA_CMD<20> T2 M9
4,5
BI RESET VSS 4,5
BI RESET VSS 4,5
BI RESET VSS 4,5
BI RESET VSS
VSS P1 VSS P1 VSS P1 VSS P1
FBA_CMD<0> K1 P9 FBA_CMD<0> K1 P9 FBA_CMD<16> K1 P9 FBA_CMD<16> K1 P9
4,5
BI ODT/ODT0 VSS 4,5
BI ODT/ODT0 VSS 4,5
BI ODT/ODT0 VSS 4,5
BI ODT/ODT0 VSS
VSS T1 VSS T1 VSS T1 VSS T1

01 i( AL
FBA0_ZQ0 L8 T9 FBA0_ZQ1 L8 T9 FBA0_ZQ2 L8 T9 FBA0_ZQ3 L8 T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS
FBVDDQ
R166 R162 R164 R159
243 243 243 243
3 1% 1% 1% 1% R165 3
0402 GND 0402 GND 0402 GND 0402 GND
1K
COMMON COMMON COMMON COMMON
1%
0402
0.75V COMMON
VREFDQ H1 VREFDQ H1 VREFDQ H1 VREFDQ H1
M8 M8 M8 M8

(0
GND VREFCA GND VREFCA GND VREFCA GND VREFCA
C190 C187 R167
0.1UF 0.1UF 1K

裴
16V 16V 1%
10% 10% 0402
FB_VREF COMMON
X7R X7R
0402 0.3MM 0402
COMMON COMMON

00 RM 亮
GND
GND
CLOSE TO MEMORY
M2C M1B M3C M4A FBVDDQ PLACE TOPSIDE FBVDDQ M4
FBGA96 FBGA96 FBGA96 FBGA96 M1
BGA100 BGA100 BGA100 BGA100
COMMON COMMON COMMON COMMON
FBA_D<0> F8 FBA_D<16> C8 FBA_D<32> H3 FBA_D<48> A3 C188 C202 C191 C180 C205 C184 C178 C182 C176

11 A工 樂
4,5
BI DQ0 4,5
BI DQ0 4,5
BI DQ0 4,5
BI DQ0 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 10UF
4,5 FBA_D<1> F7 DQ1 4,5 FBA_D<17> A7 DQ1 4,5 FBA_D<33> F2 DQ1 4,5 FBA_D<49> C3 DQ1
BI BI BI BI 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
4,5 FBA_D<2> H8 DQ2 4,5 FBA_D<18> D7 DQ2 4,5 FBA_D<34> G2 DQ2 4,5 FBA_D<50> C2 DQ2
BI BI BI BI 10% 10% 10% 10% 10% 10% 10% 10% 20%
4,5 FBA_D<3> H7 DQ3 4,5 FBA_D<19> B8 DQ3 4,5 FBA_D<35> E3 DQ3 4,5 FBA_D<51> A2 DQ3 X5R X5R X5R X5R X5R X5R X5R X5R X5R
BI BI BI BI
4,5 FBA_D<4> E3 DQ4 4,5 FBA_D<20> C3 DQ4 4,5 FBA_D<36> F8 DQ4 4,5 FBA_D<52> A7 DQ4 0402 0402 0402 0402 0402 0402 0402 0402 0805
BI BI BI BI
4,5 FBA_D<5> F2 DQ5 4,5 FBA_D<21> A3 DQ5 4,5 FBA_D<37> F7 DQ5 4,5 FBA_D<53> B8 DQ5 COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON
BI BI BI BI
4,5 FBA_D<6> H3 DQ6 4,5 FBA_D<22> C2 DQ6 4,5 FBA_D<38> H8 DQ6 4,5 FBA_D<54> D7 DQ6
BI BI BI BI
4 4,5 FBA_D<7> G2 DQ7 4,5 FBA_D<23> A2 DQ7 4,5 FBA_D<39> H7 DQ7 4,5 FBA_D<55> C8 DQ7 4
BI BI BI BI C203 C185 C208 C209 C177 C179 C210 C181
1UF 1UF 4.7UF 4.7UF 1UF 1UF 4.7UF 4.7UF
FBA_DQM<0> E7 DQM FBA_DQM<2> D3 DQM FBA_DQM<4> E7 DQM FBA_DQM<6> D3 DQM GND GND

60
4,5 4,5 4,5 4,5
BI BI BI BI 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
4,5 FBA_DQS_WP<0> F3 DQS 4,5 FBA_DQS_WP<2> C7 DQS 4,5 FBA_DQS_WP<4> F3 DQS 4,5 FBA_DQS_WP<6> C7 DQS
BI BI BI BI 10% 10% 20% 20% 10% 10% 20% 20%

)
4,5 FBA_DQS_RN<0> G3 DQS* 4,5 FBA_DQS_RN<2> B7 DQS* 4,5 FBA_DQS_RN<4> G3 DQS* 4,5 FBA_DQS_RN<6> B7 DQS* X5R X5R X5R X5R X5R X5R X5R X5R
BI BI BI BI
0402 0402 0603 0603 0402 0402 0603 0603
COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON

程
M1A M2A M4C M3A

FBGA96 FBGA96 FBGA96 FBGA96

BGA100 BGA100 BGA100 BGA100
COMMON COMMON COMMON COMMON FBVDDQ M2 GND FBVDDQ M3 GND
E3 A3 F8 B8

1)
4,5 FBA_D<8> DQ0 4,5 FBA_D<24> DQ0 4,5 FBA_D<40> DQ0 4,5 FBA_D<56> DQ0
BI BI BI BI
4,5 FBA_D<9> H3 DQ1 4,5 FBA_D<25> C3 DQ1 4,5 FBA_D<41> E3 DQ1 4,5 FBA_D<57> D7 DQ1
BI BI BI BI
4,5 FBA_D<10> F2 DQ2 4,5 FBA_D<26> A2 DQ2 4,5 FBA_D<42> H8 DQ2 4,5 FBA_D<58> C8 DQ2
BI BI BI BI C199 C189 C201 C197 C186 C192 C196 C195
4,5 FBA_D<11> G2 DQ3 4,5 FBA_D<27> C2 DQ3 4,5 FBA_D<43> H7 DQ3 4,5 FBA_D<59> A7 DQ3
BI BI BI BI 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
F7 A7 F7 C3

課
4,5 FBA_D<12> DQ4 4,5 FBA_D<28> DQ4 4,5 FBA_D<44> DQ4 4,5 FBA_D<60> DQ4
BI BI BI BI 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
4,5 FBA_D<13> H7 DQ5 4,5 FBA_D<29> B8 DQ5 4,5 FBA_D<45> H3 DQ5 4,5 FBA_D<61> C2 DQ5
BI BI BI BI 10% 10% 10% 10% 10% 10% 10% 10%
4,5 FBA_D<14> F8 DQ6 4,5 FBA_D<30> D7 DQ6 4,5 FBA_D<46> G2 DQ6 4,5 FBA_D<62> A2 DQ6 X5R X5R X5R X5R X5R X5R X5R X5R
BI BI BI BI
4,5 FBA_D<15> H8 DQ7 4,5 FBA_D<31> C8 DQ7 4,5 FBA_D<47> F2 DQ7 4,5 FBA_D<63> A3 DQ7 0402 0402 0402 0402 0402 0402 0402 0402
BI BI BI BI
COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON

4,5 FBA_DQM<1> E7 DQM 4,5 FBA_DQM<3> D3 DQM 4,5 FBA_DQM<5> E7 DQM 4,5 FBA_DQM<7> D3 DQM
BI BI BI BI
4,5 FBA_DQS_WP<1> F3 DQS 4,5 FBA_DQS_WP<3> C7 DQS 4,5 FBA_DQS_WP<5> F3 DQS 4,5 FBA_DQS_WP<7> C7 DQS
BI BI BI BI C198 C183 C206 C207 C204 C193 C200 C194
4,5 FBA_DQS_RN<1> G3 DQS* 4,5 FBA_DQS_RN<3> B7 DQS* 4,5 FBA_DQS_RN<5> G3 DQS* 4,5 FBA_DQS_RN<7> B7 DQS*
BI BI BI BI 1UF 1UF 4.7UF 4.7UF 1UF 1UF 4.7UF 4.7UF
GND
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
10% 10% 20% 20% 10% 10% 20% 20%
GND
X5R X5R X5R X5R X5R X5R X5R X5R
0402 0402 0603 0603 0402 0402 0603 0603
COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON

5 MEMORY DECOUPLING 5
GND GND

NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY

ASSEMBLY BASE LEVEL GENERIC SCHEMATIC ONLY SANTA CLARA, CA 95050, USA
PAGE DETAIL DDR3 Memories
NV_PN 600-12132-BASE-QS1
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL PCB REV P2132-A01 PAGE 4 OF 15
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS. BOM REV A DATE 14-MAR-2013

A B C D E F G H
 A B C D E F G H

DECOUPLING FOR CORE POWER_TOP

00 M
G1C

BGA595
G1E

BGA595
COMMON
G1F

BGA595
COMMON

0
NVVDD COMMON

11/14 NVVDD
FBVDDQ 12/14 FBVDDQ 13/14 GND

RD 17 SI
K10 VDD A2 GND GND M13
1
K12 VDD B26 FBVDDQ AB17 GND GND M15 1
C123 C124 K14 C25 AB20 M17
0.1UF 0.1UF VDD FBVDDQ GND GND
K16 C145 C151 C149 C148 E23 AB24 N10
16V 16V
VDD 0.1UF 0.1UF 0.1UF 0.1UF FBVDDQ GND GND
K18 VDD E26 FBVDDQ AC2 GND GND N12
10% 10% 16V 16V 16V 16V
X7R X7R L11 VDD F14 FBVDDQ AC22 GND GND N14
10% 10% 10% 10%
0402 0402 L13 VDD X7R X7R X7R X7R F21 FBVDDQ AC26 GND GND N16
COMMON COMMON L15 VDD 0402 0402 0402 0402 G13 FBVDDQ AC5 GND GND N18
L17 VDD COMMON COMMON COMMON COMMON G14 FBVDDQ AC8 GND GND P11
M10 G15 AD12 P13

(C 96 C
VDD FBVDDQ GND GND
M12 VDD G16 FBVDDQ AD13 GND GND P15
GND M14 VDD G18 FBVDDQ A26 GND GND P17
M16 VDD GND G19 FBVDDQ AD15 GND GND P2
M18 VDD G20 FBVDDQ AD16 GND GND P23
C113 C114 C120 C119 N11 G21 AD18 P26
1UF 1UF 1UF 1UF VDD FBVDDQ GND GND
N13 VDD H24 FBVDDQ AD19 GND GND P5
6.3V 6.3V 6.3V 6.3V
N15 VDD H26 FBVDDQ AD21 GND GND R10
10% 10% 10% 10% C142 C143 C150 C144
N17 J21 AD22 R12

)2 7 ON
X5R X5R X5R X5R VDD 1UF 1UF 1UF 1UF FBVDDQ GND GND
0402 0402 0402 0402 P10 VDD K21 FBVDDQ AE11 GND GND R14
6.3V 6.3V 6.3V 6.3V
COMMON COMMON COMMON COMMON P12 VDD L22 FBVDDQ AE14 GND GND R16
10% 10% 10% 10%
P14 VDD X5R X5R X5R X5R L24 FBVDDQ AE17 GND GND R18
P16 VDD 0402 0402 0402 0402 L26 FBVDDQ AE20 GND GND T11
P18 VDD COMMON COMMON COMMON COMMON M21 FBVDDQ AB11 GND GND T13
GND R11 VDD N21 FBVDDQ AF1 GND GND T15
R13 VDD R21 FBVDDQ AF11 GND GND T17
R15 VDD T21 FBVDDQ AF14 GND GND U10
C111 C108 C98 C100 GND

F
R17 VDD V21 FBVDDQ AF17 GND GND U12

0
4.7UF 4.7UF 4.7UF 4.7UF
T10 VDD W21 FBVDDQ AF20 GND GND U14
6.3V 6.3V 6.3V 6.3V
T12 VDD AF23 GND GND U16
20% 20% 20% 20%
X5R X5R X5R X5R T14 VDD AF5 GND GND U18
T16 AF8 U2

吳 15 jo ID
0603 0603 0603 0603 VDD GND GND
2 C141 C152 C153 C140 2
COMMON COMMON COMMON COMMON T18 VDD AG2 GND GND U23
4.7UF 4.7UF 4.7UF 4.7UF
U11 VDD AG26 GND GND U26
6.3V 6.3V 6.3V 6.3V
U13 VDD AB14 GND GND U5
20% 20% 20% 20%
U15 VDD X5R X5R X5R X5R B1 GND GND V11
GND U17 VDD 0603 0603 0603 0603 B11 GND GND V13
V10 VDD COMMON COMMON COMMON COMMON B14 GND GND V15
V12 VDD B17 GND GND V17
V14 VDD B20 GND GND Y2
C81 C80 C88 C93 C87 C92 V16 B23 Y23

積 04 ne EN
10UF 10UF 10UF 10UF 10UF 10UF VDD GND GND
V18 VDD GND B27 GND GND Y26
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
B5 GND GND Y5
20% 20% 20% 20% 20% 20%
X5R X5R X5R X5R X5R X5R B8 GND
0603 0603 0603 0603 0603 0603 E11 GND
COMMON COMMON COMMON COMMON COMMON COMMON E14 GND
PLACE CLOSE GPU E17 GND
E2 GND
E20 GND

源 27 pe TI
GND E22 GND
E25 GND
E5 GND
FBVDDQ E8
C115 C85 C68 C105 GND
H2 GND
22UF 22UF 22UF 22UF R143 40.2
FB_CAL_PD_VDDQ D22 FB_CAL_PD_VDDQ H23 GND
6.3V 6.3V 6.3V 6.3V
0402 1% COMMON H25 GND
20% 20% 20% 20%
X5R X5R X5R X5R H5 GND
0805 0805 0805 0805 C24 FB_CAL_PU_GND R154 40.2 K11
FB_CAL_PU_GND GND

01 i( AL
COMMON COMMON COMMON COMMON 0402 1% COMMON K13 GND
K15 GND
B25 FB_CAL_TERM_GND R153 40.2 K17
FB_CALTERM_GND GND
3
0402 1% COMMON L10 GND 3
GND L12 GND
Adjustable depending on GPU
L14 GND
GND L16 GND
L18 GND
PLACE CLOSE TO GPU L2 GND
L23

(0
GND
L25 GND

裴
L5 GND GND AA7
M11 GND GND AB7

C65 C64 C104 C77 C75 C89 GND GND

10UF 10UF 10UF 10UF 10UF 10UF

00 RM 亮
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
20% 20% 20% 20% 20% 20%
X5R X5R X5R X5R X5R X5R
G1D
0805LP 0805LP 0805LP 0805LP 0805LP 0805LP
COMMON COMMON COMMON COMMON COMMON COMMON
BGA595
COMMON
3V3_PEX

0.19 Amps GK208

14/14 XVDD/VDD33
GND LP CAPS OPTION NEAR GPU SNN_NC_AD10 AD10 G10

11 A工 樂
NC VDD33
SNN_NC_AD7 AD7 NC VDD33 G12
SNN_NC_B19 B19 G8 C122 C117
NC VDD33 1UF 4.7UF
VDD33 G9
6.3V 6.3V
10% 20%
SNN_NC_F11 F11 3V3AUX_NC X5R X5R
0402 0603

4 3V3_PLL V5 FERMI_RSVD1_NC COMMON COMMON

4
V6 FERMI_RSVD2_NC

60
GND

)
PLACE CLOSE TO GPU
CONFIGURABLE

程
POWER CHANNELS
3V3_PEX * nc on substrate

G1 XPWR_G1
G2

1)
XPWR_G2
G3 XPWR_G3
G4 XPWR_G4
G5 XPWR_G5
G6

課
XPWR_G6
G7 XPWR_G7
3V3_PLL

V1 XPWR_V1
V2 XPWR_V2

W1 XPWR_W1
W2 XPWR_W2
W3 XPWR_W3
W4 XPWR_W4

5 5

NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY

ASSEMBLY BASE LEVEL GENERIC SCHEMATIC ONLY SANTA CLARA, CA 95050, USA
PAGE DETAIL DECOUPLING FOR CORE POWER_TOP
NV_PN 600-12132-BASE-QS115ci203
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL PCB REV P2132-A01 PAGE 5 OF 15
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS. BOM REV A DATE 14-MAR-2013

A B C D E F G H
 A B C D E F G H

DACA VGA

00 M
0
RD 17 SI
1 1

(C 96 C
)2 7 ON
2

G1G
0
吳 15 jo ID F 2

積 04 ne EN
DDC_5V
BGA595
COMMON R35 2.2K
3/14 DACA 0402 5% COMMON
3V3_PLL
GF119/GK208 GF117 GF117 GF119/GK208
0.070 Amps
W5 DACA_VDD NC NC I2CA_SCL B7
NC I2CA_SDA A7
DACA_VREF AE2 DACA_VREF TSEN_VREF

源 27 pe TI
DDC_5V
DACA_RSET AF2 DACA_RSET NC NC DACA_HSYNC AE3
DACA_VSYNC AE4 R39 2.2K
C125 R129 NC
0402 5% COMMON
0.1UF 124
16V 1%
0402 DACA_RED AG3
10% NC
X7R COMMON
0402 DACA_GREEN AF4
COMMON
NC

01 i( AL
NC DACA_BLUE AF3
PLACE CLOSE TO BGA

3 3
GND

(0 裴
00 RM 亮
4

11 A工 樂 4

60 程 )
1) 課
5 5

NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY

ASSEMBLY BASE LEVEL GENERIC SCHEMATIC ONLY SANTA CLARA, CA 95050, USA
PAGE DETAIL DACA VGA
NV_PN 600-12132-BASE-QS115ci203
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL PCB REV P2132-A01 PAGE 6 OF 15
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS. BOM REV A DATE 14-MAR-2013

A B C D E F G H
 A B C D E F G H

IFPAB TMDS
00 M
0
RD 17 SI
1 1

(C 96 C
G1H

BGA595

)2 7 ON
F
G1K NVVDD

0
COMMON

4/14 IFPAB BGA595

COMMON
GF117 GF119/GK208

吳 15 jo ID
2 7/14 IFPEF 2
NC IFPA_TXC AC4
NC IFPA_TXC AC3 GF119/GK208
GF119/GK208 GF117 GF117
NVVDD
R134 1K IFPAB_RSET AA6 DVI-DL DVI-SL/HDMI DP
GND IFPAB_RSET NC GF117
0402 1% COMMON
NC IFPA_TXD0 Y3 NC I2CY_SDA I2CY_SDA IFPE_AUX J3 SNN_IFPE_AUX*

Y4 GF119 GK208 J2 SNN_IFPE_AUX

NC IFPA_TXD0 NC I2CY_SCL I2CY_SCL IFPE_AUX
J7 IFPEF_PLLVDD NC
3V3_PLL V7 IFPAB_PLLVDD NC
AA2 J1

積 04 ne EN
NC IFPA_TXD1 NC TXC TXC IFPE_L3
W7 IFPAB_PLLVDD NC NC IFPA_TXD1 AA3 IFPE_L3 K1
NC TXC TXC
K7 IFPEF_PLLVDD NC
0.095 Amps
IFPE_L2 K3
AA1 NC TXD0 TXD0 K2
NC IFPA_TXD2 NC TXD0 TXD0 IFPE_L2
NC IFPA_TXD2 AB1
K6 IFPEF_RSET NC IFPE_L1 M3
NC TXD1 TXD1
IFPE_L1 M2
NC TXD1 TXD1
NC IFPA_TXD3 AA5

源 27 pe TI
NC IFPA_TXD3 AA4 IFPE_L0 M1
NC TXD2 TXD2 N1
NC TXD2 TXD2 IFPE_L0

NC IFPB_TXC AB4
NC FOR GK208
NC IFPB_TXC AB5 IFPE
1V_PLL
GF119/GK208 GF117
W6 IFPA_IOVDD NC NC IFPB_TXD4 AB2 NC HPD_E GPIO18 C2 SNN_GPIO18
HPD_E
IFPB_TXD4 AB3

01 i( AL
0.144 Amps NC
Y6 IFPB_IOVDD NC GF117
AD2 GF119 GK208
NC IFPB_TXD5
3 NC IFPB_TXD5 AD3 H6 IFPE_IOVDD NC 3
GF119/GK208
J6 GF117
IFPF_IOVDD NC
AD1 DVI-DL DVI-SL/HDMI DP
NC IFPB_TXD6
NC IFPB_TXD6 AE1 NC I2CZ_SDA IFPF_AUX H4 SNN_IFPF_AUX*

NC I2CZ_SCL IFPF_AUX H3 SNN_IFPF_AUX

(0
NC IFPB_TXD7 AD5

裴
NC IFPB_TXD7 AD4 NC TXC IFPF_L3 J5
NC TXC IFPF_L3 J4

NC TXD3 TXD0 IFPF_L2 K5

NC TXD3 TXD0 IFPF_L2 K4

NC GPIO14 B3 NC TXD4 TXD1 IFPF_L1 L4

00 RM 亮
IFPAB IFPF NC TXD4 TXD1 IFPF_L1 L3

NC TXD5 TXD2 IFPF_L0 M5

NC TXD5 TXD2 IFPF_L0 M4

NC FOR GK208

NC F7 SNN_GPIO19

11 A工 樂
HPD_F GPIO19

4 4

60 程 )
1) 課
5 5

NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY

ASSEMBLY BASE LEVEL GENERIC SCHEMATIC ONLY SANTA CLARA, CA 95050, USA
PAGE DETAIL IFPAB TMDS
NV_PN 600-12132-BASE-QS1
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL PCB REV P2132-A01 PAGE 7 OF 15
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS. BOM REV A DATE 14-MAR-2013

A B C D E F G H
 A B C D E F G H

00
IFPC HDMI

0
RD 17 SI M C568
0402
0.1UF
16V
10%
X7R
3V3_PROT

R515
1

(C 96 C
COMMON 100K
5%
0402
S D COMMON
3 2 2 3
D S
COMMON COMMON
R512 SOT23 SOT23
12V_PEX 12V_PEX
100K G
Q503 Q12
5%

)2 7 ON
G

1
0402 R510
COMMON
10K R511
ED121
5% 10K
0402 5%
COMMON 0402
GND 3 1B1C1E COMMON
Q502 C
1B DP_MODE_D 3 1G1D1S
SOT23
Q505 D
COMMON

F
2 E

0
SOT23 G1
COMMON DP_MODE_C
DP_MODE_E 2 S
60V
0.26A@25C

吳 15 jo ID
3R
2 C572 0.31A R516 2
0.3W@25C
0.01UF +/-20V 1M
GND
16V 5%
ED120
10% 0402
X7R COMMON
0402
COMMON GND

GND

積 04 ne EN
GND

1
Q504 G G Q10

SOT23 SOT23
COMMON COMMON
3 D S 2 I2CW_SCL_R 2 S D 3
IFPC_RSET
R513 R514

源 27 pe TI
R128 G1I 100K 100K D1612
1K 5% 5%
BGA595
0402 0402
IFPC_TXC_R* 5 DNI 6 IFPC_TXC_R*
1% COMMON
0402 COMMON COMMON IFPC_TXC_R 4 D Y4 7 IFPC_TXC_R
ED122 3 C Y3 8
COMMON 5/14 IFPC
IFPC C570 0.1UF IFPC_TXD0_R*
GND
2 GND GND1 9
GND
IFPC_TXD0_R*
GF119/GK208 GF117 0402 16V IFPC_TXD0_R 1 B Y2 10 IFPC_TXD0_R
T6 10% A Y1
IFPC_RSET NC GF117 GF119/GK208 GND GND
GND X7R
RCLAMP0524P

01 i( AL
COMMON
DVI/HDMI DP
0.095 Amps D1613
3V3_PLL M7 IFPC_PLLVDD NC NC I2CW_SDA IFPC_AUX N5 I2CZ_SDA

3
N7 IFPC_PLLVDD NC NC I2CW_SCL IFPC_AUX N4 I2CZ_SCL IFPC_TXD1_R* 5 DNI 6 IFPC_TXD1_R* 3
IFPC_TXD1_R 4 D Y4 7 IFPC_TXD1_R
3 C Y3 8
IFPC_TXC* C24 0.1UF GND GND
NC TXC IFPC_L3 N3 10% IFPC_TXC_C* 3 4 R2728 DNI IFPC_TXD2_R* 2 GND GND1 9 IFPC_TXD2_R*
N2 IFPC_TXC 10% C23 0.1UF X7R 0402 16V COMMON IFPC_TXC_C RN8 1 2 IFPC_TXD2_R 1 B Y2 10 IFPC_TXD2_R
NC TXC IFPC_L3
X7R 0402 16V COMMON A Y1

R3 IFPC_TXD0* 10% C21 0.1UF 3 4 R2729 DNI

(0
IFPC_L2 IFPC_TXD0_C* RCLAMP0524P
NC TXD0 IFPC_TXD0 C22 0.1UF
TXD0 IFPC_L2 R2 10% X7R 0402 16V COMMON IFPC_TXD0_C RN9 1 2
NC

裴
X7R 0402 16V COMMON
R1 IFPC_TXD1* 10% C26 0.1UF IFPC_TXD1_C* 3 4 R2730 DNI
NC TXD1 IFPC_L1
T1 IFPC_TXD1 10% C28 0.1UF X7R 0402 16V COMMON IFPC_TXD1_C RN10 1 2
NC TXD1 IFPC_L1
PLACE UNDER GPU IFPC_TXD2*
X7R 0402 16V COMMON
C27 0.1UF
NC IFPC_L0 T3 10% IFPC_TXD2_C* 3 4 R2731 DNI
TXD2 IFPC_TXD2 C25 0.1UF
NC TXD2 IFPC_L0 T2 10% X7R 0402 16V COMMON IFPC_TXD2_C RN11 1 2
X7R 0402 16V COMMON

00 RM 亮
0.072 Amps
P6 GPIO15 C3 3V3_PEX J2
1V_PLL IFPC_IOVDD NC NC

IFPC_TXD2_R 1
R12 2 ML_Lane_0p
10k GND_0
IFPC_TXD2_R* 3
5% ML_Lane_0n
0402
Hotplug Detection IFPC_TXD1_R 4

11 A工 樂
COMMON
GPIO15_IFPD_HPD 3 5 ML_Lane_1p
1B1C1E
Q15 C IFPC_TXD1_R* 6 GND_1
INS17016992 1B 15_DP_D_HPD_R_Q 1 R21 100k2 15_DP_D_HPD_R 1 R25 0ohm
2 ML_Lane_1n
SOT23_1B1C1E
COMMON
0402 5% COMMON 0603 COMMON IFPC_TXD0_R 7
2 E 8 ML_Lane_2p
GND_2

1
R15 C18 C16 IFPC_TXD0_R* 9
100k 220pF 220pF ML_Lane_2n
4 5% 50V 50V 4
0402
IFPC_TXC_R 10
5% 5%
11 ML_Lane_3p

60
COMMON C0G C0G

2
IFPC_TXC_R* 12 GND_3
GND 0402 0402
ML_Lane_3n

)
COMMON COMMON
DP_POWER 13
14 Pin_13
GND GND GND

程
Pin_14
15
16 AUX_CHp
17 GND_6
AUX_CHn

1)
15_DP_D_HPD_C 18 G4
Hot_Det G4 G3
20 G3 G2
3V3_PEX DP_POWER 19 DP_PWR G2 G1

課
PWR_RTN G1

1
C2540 DISPLAYPORT
ED119 22uF
6.3V GND
F503 DP

2
2 1 R9
5.1M
5%
POLYSWITCH
0402
C229 COMMON

1uF
COMMON
10% 6.3V
X5R
5 5
0402
GND GND

NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY

ASSEMBLY BASE LEVEL GENERIC SCHEMATIC ONLY SANTA CLARA, CA 95050, USA
PAGE DETAIL IFPC HDMI
NV_PN 600-12132-BASE-QS1
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL PCB REV P2132-A01 PAGE 8 OF 15
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS. BOM REV A DATE 14-MAR-2013

A B C D E F G H
 A B C D E F G H

00
UNSED IFPD, IFPE & IFPF 3V3_PROT

C569 0.1UF
0402 16V
10%

M
X7R R520
COMMON 100K
5%

0
0402
S D COMMON

RD 17 SI
3 2IFPD_AUX_BYP*2 3 IFPD_AUX_C*
D S
COMMON COMMON
1 R518 SOT23 SOT23 1
G 12V_PEX 12V_PEX
100K
Q507 Q14
5% G

1
0402 R521
COMMON
10K R522
ED124
5% 10K
0402 5%
COMMON 0402
3

(C 96 C
GND 1B1C1E COMMON
Q508 C
1B DP_MODE* 3 1G1D1S
SOT23
Q509 D
COMMON
2 E
SOT23 G1
COMMON DP_MODE_R
DP_MODE 2 S
60V
0.26A@25C

)2 7 ON
3R
C573 0.31A R523
0.3W@25C
0.01UF +/-20V 1M
GND
16V 5%
ED123
10% 0402
X7R COMMON
0402
COMMON GND

GND

F
GND

1
Q506 G G Q13

吳 15 jo ID
2 2
SOT23 SOT23
COMMON COMMON
3 D S 2 IFPD_AUX_BYP 2 S D 3 IFPD_AUX_C
IFPC_RSET
R517 R519 D1610
R131 G1J 100K 100K
IFPD_L0_R 5 DNI 6 IFPD_L0_R
1K 5% 5% D Y4
BGA595
0402 0402
IFPD_L0_R* 4 7 IFPD_L0_R*
1% COMMON
0402 COMMON COMMON 3 C Y3 8
GND GND
ED126 2 GND GND1 9

積 04 ne EN
COMMON 6/14 IFPD IFPD_L1_R IFPD_L1_R
C571 0.1UF IFPD_L1_R* 1 B Y2 10 IFPD_L1_R*
GF119/GK208 GF117 0402 16V A Y1

U6 GF117 GF119/GK208 10% RCLAMP0524P

IFPD_RSET NC GND GND
GND X7R
COMMON
DVI/HDMI DP
D1611
0.095 Amps
3V3_PLL T7 IFPD_PLLVDD NC NC I2CX_SDA IFPD_AUX P4 IFPD_AUX* IFPD_L2_R 5 DNI 6 IFPD_L2_R
P3 IFPD_AUX IFPD_L2_R* 4 D Y4 7 IFPD_L2_R*
NC I2CX_SCL IFPD_AUX

源 27 pe TI
R7 IFPD_PLLVDD NC
3 C Y3 8
GND GND
IFPD_L3_R 2 GND GND1 9 IFPD_L3_R
R5 IFPD_L3* 10% C36 0.1UF IFPD_L3_C* 3 4 R2734 DNI IFPD_L3_R* 1 B Y2 10 IFPD_L3_R*
NC TXC IFPD_L3
R4 IFPD_L3 10% C32 0.1UF X7R 0402 16V COMMON IFPD_L3_C RN13 1 2 A Y1
NC TXC IFPD_L3
X7R 0402 16V COMMON RCLAMP0524P
T5 IFPD_L2* 10% C35 0.1UF IFPD_L2_C* 3 4 R2735 DNI
NC TXD0 IFPD_L2
T4 IFPD_L2 10% C31 0.1UF X7R 0402 16V COMMON IFPD_L2_C RN14 1 2
NC TXD0 IFPD_L2
X7R 0402 16V COMMON
U4 IFPD_L1* 10% C34 0.1UF IFPD_L1_C* 3 4 R2732 DNI
TXD1 IFPD_L1

01 i( AL
NC
IFPD NC TXD1 IFPD_L1 U3 IFPD_L1 10% C30 0.1UF X7R 0402 16V COMMON IFPD_L1_C RN15 1 2
X7R 0402 16V COMMON
V4 IFPD_L0* 10% C33 0.1UF IFPD_L0_C* 3 4 R2733 DNI
NC TXD2 IFPD_L0
V3 IFPD_L0 10% C29 0.1UF X7R 0402 16V COMMON IFPD_L0_C RN12 1 2
3 NC TXD2 IFPD_L0 3
X7R 0402 16V COMMON

3V3_PEX
0.072 Amps
R6 D4 J3
1V_PLL IFPD_IOVDD NC NC GPIO17
R11 IFPD_L0_R 1

(0
GF119/GK208 GF117 10k ML_Lane_0p
2
GND_0

裴
5%
IFPD_L0_R* 3
0402
COMMON
Hotplug Detection ML_Lane_0n
GPIO17_IFPD_HPD 3 1B1C1E IFPD_L1_R 4
Q4 C 5 ML_Lane_1p
INS17007852 1B DP_D_HPD_R_Q 1 R20 100k2 DP_D_HPD_R 1 R24 0ohm
2 IFPD_L1_R* 6 GND_1
SOT23_1B1C1E
0402 5% COMMON 0603 COMMON
ML_Lane_1n
COMMON
2 E IFPD_L2_R 7

00 RM 亮
ML_Lane_2p

1
R14 C17 C15 8
100k 220pF 220pF GND_2
IFPD_L2_R* 9
5% 50V 50V ML_Lane_2n
0402 5% 5%
COMMON C0G C0G IFPD_L3_R 10

2
11 ML_Lane_3p
GND 0402 0402
COMMON COMMON IFPD_L3_R* 12 GND_3
ML_Lane_3n
GND GND DP_POWER GND 13
14 Pin_13

11 A工 樂
Pin_14
15
16 AUX_CHp
17 GND_6
AUX_CHn
DP_D_HPD_C 18 G4
Hot_Det G4 G3
4 G3 4
20 G2
19 DP_PWR G2 G1

60
PWR_RTN G1

)
ED125 DISPLAYPORT

1
程
C2541 GND
22uF
6.3V
DP

2
R10
5.1M

1)
5%
0402
COMMON

課
GND GND

5 5

NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY

ASSEMBLY BASE LEVEL GENERIC SCHEMATIC ONLY SANTA CLARA, CA 95050, USA
PAGE DETAIL UNSED IFPD, IFPE & IFPF
NV_PN 600-12132-BASE-QS1
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL PCB REV P2132-A01 PAGE 9 OF 15
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS. BOM REV A DATE 14-MAR-2013

A B C D E F G H
 A B C D E F G H

MISC INTERFACES

00
STUFF 100KOHM IF I2CS CONNECT TO SMBUS

3V3_PEX

M
G1N R109 R102
2.2K 2.2K

0
BGA595
COMMON 5% 5%
0402 0402

RD 17 SI
8/14 MISC1 COMMON COMMON
D9 I2CS_SCL DDC_5V
1 I2CS_SCL GENERIC_SEZ2
IN
2
1
I2CS_SDA D8 I2CS_SDA
GENERIC_SEZ2 2
BI

I2CC_SCL A9 SNN_I2CC_SCL

B9 SNN_I2CC_SDA R1 R5
I2CC_SDA 2.2K 2.2K
GF119 5% 5%
GF117 GK208 0402 0402
SNN_THERMDN E12 THERMDN COMMON COMMON
C9

(C 96 C
NC I2CB_SCL
SNN_THERMDP F12 THERMDP NC I2CB_SDA C8

JTAG_TCK AE5 JTAG_TCK

TP504
JTAG_TMS AD6 JTAG_TMS
TP503
JTAG_TDI AE6 JTAG_TDI
TP501
JTAG_TDO AF6 JTAG_TDO
TP502
JTAG_TRST* AG4 C6 GPIO0_NVVID4

)2 7 ON
TP505 JTAG_TRST GPIO0 OUT
14

GPIO1 B2 GPIO1_NVVID3 14
R137 OUT
GPIO2 D6 SNN_GPIO2
10K
GPIO3 C7 SNN_GPIO3
5%
0402 GPIO4 F9 SNN_GPIO4

COMMON GPIO5 A3 GPIO5_NVVID1 14

OUT
GPIO6 A4 GPIO6_NVVID2 14
OUT
GK208 GPIO7 B6 SNN_GPIO7

OVERT GPIO8 A6 GPIO_THERM_OVERT* 12,14

OUT
GND

F
GPIO9 F8 SNN_GPIO9

0
JTAG GPIO10 C5 SNN_GPIO10

GPIO11 E7 GPIO11_NVVID0 14
OUT
GPIO12 D7 SNN_GPIO12

B4 SNN_GPIO13

吳 15 jo ID
2 GPIO13 2

GK208 GF117 GF119

GPIO16 NC GPIO16 D5 GPIO16_FAN_PWM 11

OUT
GPIO20 NC GPIO20 E6 SNN_GPIO20

GPIO8 NC GPIO21 C4 SNN_GPIO8

積 04 ne EN
3V3_PEX

G1M

BGA595 3V3_PEX
U6

源 27 pe TI
COMMON

10/14 MISC2 11 SO8

IN R150
11 SO8
IN 10K
11 COMMON
GF117/GF119/GK208 IN 5%
0402
7 HOLD VCC 8
SNN_VMON_IN0 E10 VMON_IN0 NC COMMON 3 WP
SNN_VMON_IN1 F10 D12 ROM_CS* R151 33 ROM_CS_R* 1 C154
VMON_IN1 NC ROM_CS CS 0.1UF
0402 5% COMMON
R140 100 16V
ROM_SI B12 ROM_SI ROM_SI_R 5 SI

01 i( AL
10%
ROM_SO A12 ROM_SO 0402 5% COMMON 2 SO X7R
STRAP0 D1 C12 ROM_SCLK R145 100 ROM_SCLK_R 6 4 0402
11
IN STRAP0 ROM_SCLK SCK GND
11
STRAP1 D2 STRAP1 0402 5% COMMON COMMON
IN
3 11
STRAP2 E4 STRAP2 3
IN
11 STRAP3 E3 STRAP3
IN
11
STRAP4 D3 STRAP4 GND
IN
BIOS
GF119 GF117
GK208
SNN_STRAP5 C1

(0
STRAP5_NC NC
BUFRST D11 SNN_BUFRST*

裴
MULTISTRAP_REF0_GND F6 MULTISTRAP_REF0_GND NC PGOOD D10 SNN_PGOOD

R135 GF117 GF117

40.2K GF119 GF119
GK208 GK208
1%
0402
SNN_STARP_REF1 F4 MULTISTRAP_REF1_GND NC
COMMON NC CEC E9 SNN_GPU_CEC

00 RM 亮
SNN_STARP_REF2 F5 MULTISTRAP_REF2_GND NC GF117
GK208
GF119
GND

11 A工 樂
G1L

BGA595
COMMON

9/14 XTAL_PLL
0.142 Amps

1V_PLL L6 PLLVDD
4
M6 SP_PLLVDD 4
3V3_PEX
N6 VID_PLLVDD 3V3_PEX

60
NC
R61 R64

)
10K GF119/GK208 GF117 10K
5% 5%

程
0402 0402
COMMON COMMON
SMART FAN STRAP
XTALSSIN A10 XTALSSIN XTALOUTBUFF C10 XTALOUTBUFF
XTAL_SSIN XTAL_OUTBUFF Inverted PWM%
R62 R65 0 0 0 (100% HIGH)
10K 10K 0 1 33 (67% HIGH)
XTALIN C11 B10 XTALOUT

1)
5%
XTALIN XTALOUT 5% 1 0 50 (50% HIGH)
0402 0402
1 1 67 (33% HIGH)
COMMON COMMON

課
Y1 27MHZ
XTAL XTAL
GND GENERIC_DEZ1 HC49SA 30PPM GENERIC_DEZ1
GND
COMMON

C55 C56
15PF 15PF
50V 50V
5% 5%
C0G C0G
0402 0402
COMMON COMMON

GND GND
5 5

NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY

ASSEMBLY BASE LEVEL GENERIC SCHEMATIC ONLY SANTA CLARA, CA 95050, USA
PAGE DETAIL MISC INTERFACES
NV_PN 600-12132-BASE-QS1
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL PCB REV P2132-A01 PAGE 10 OF 15
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS. BOM REV A DATE 14-MAR-2013

A B C D E F G H
 A B C D E F G H

Page13: PCI-E Reset, STRAPS & FAN

00 M
0
RD 17 SI
1 1

Multilevel Straps

0000
0001
5.1K to GND
10K to GND
1000
1001
5.1K to VCC
10K to VCC

(C 96 C
)2 7 ON
0010
0011
0100
15K to GND
20K to GND
24.9K to GND
1010
1011
1100
15K to VCC
20K to VCC
24.9K to VCC
GK208 Straps
0101 30.1K to GND 1101 30.1K to VCC
0110 34.8K to GND 1110 34.8K to VCC
0111 45.3K to GND 1111 45.3K to VCC

R141
0402 1%
34.8K
COMMON
OUT

ROM_SI
10

R142
0402 1%
34.8K
COMMON
3V3_PEX
Bit Signal

03:

02:

01:
0
吳 15 jo ID
RAMCFG[3]

RAMCFG[2]

RAMCFG[1]
F Values

0000
0001
0010
0011
Reserved
256Mx16 DDR3 X16 64bit Micron
256Mx16 DDR3 X16 64bit Hynix
256Mx16 DDR3 X16 64bit Samsung
ROM_SI
2

積 04 ne EN
0101 128Mx16 DDR3 X16 64bit Micron
10
OUT 00: RAMCFG[0] 0110 128Mx16 DDR3 X16 64bit Hynix
0111 128Mx16 DDR3 X16 64bit Samsung
R149 34.8K ROM_SO R148 34.8K
03: FB[1] 01 128MB
0402 1% COMMON 0402 1% COMMON
10 256MB
02: FB[0]
ROM_SO
D1

源 27 pe TI
01: SMB_ALT_ADDR 0 DISABLED 1 ENABLED
10
OUT
30V 12V_PEX
00: VGA_DEVICE 0 DISABLED 1 ENABLED 200MA

R146 34.8K ROM_SCLK R144 34.8K

FAN CIRCUIT SOT23
COMMON
03: PCI_DEVID_EXT SKU0 0 SKU1 TBD
0402 1% COMMON 0402 1% COMMON 1 FAN
3 1 +12V J4
2 2 GND
02: SUB_VENDOR 0 NO_BIOS 1 BIOS MALE
ROM_SCLK 2.5MM
0

01 i( AL
01: PCI_DEVID_EXT_BIT5 SKU0 0 SKU1 TBD C40 C41 NORM
10UF 1UF COMMON
10
OUT 16V 16V
3V3_PEX R54 0
00: PEX_PLL_EN_TERM100 0 DISABLED 1 ENABLED 10% 10%
0402 +0.05R COMMON
3 X5R X5R 3
R83 34.8K STRAP0 R82 34.8K SOT23_1G1D1S
COMMON 1206 0603
0402 COMMON 0402 COMMON 03: USER[3] 0000 INIT R37 COMMON COMMON
1% 1%
02: USER[2] 1K GPIO16_FAN_Q L4 100uH
10 Strap0 1G1D1S 3 0.300
GPIO16_FAN_GND
OUT 01: USER[1] 5% D Q3 0.300 SMD_4_5X4 COMMON
0402
00: USER[0]
COMMON
R71 34.8K STRAP1 R70 34.8K GPIO16_FAN_PWM 1G PLACE NEAR FAN CONNECTOR R55

(0
10
03: 3GIO_PADCFG_LUT_ADR[3] 0000 DSKTOP_DEFAULT 1000 DSKTOP_HTHRS IN
S 0
0402 1% COMMON 0402 1% COMMON 2
R33

裴
0001 MOBILE_DEFAULT 1001 MOBILE_HTHRS_NAMP +0.05R
10K 0402
02: 3GIO_PADCFG_LUT_ADR[2] 0010 MOBILE_NTHRS_LLAMP 1010 MOBILE_HTHRS_LLAMP
0011 MOBILE_NTHRS_LAMP 1011 MOBILE_HTHRS_LAMP
Strap1 5%
COMMON

0402
01: 3GIO_PADCFG_LUT_ADR[1] 0100 MOBILE_NTHRS_HAMP 1100 MOBILE_HTHRS_HAMP
COMMON
0101 MOBILE_NTHRS_HHAMP 1101 MOBILE_HTHRS_HHAMP
10
OUT 00: 3GIO_PADCFG_LUT_ADR[0] 0110 MOBILE_NTHRS_HHHAMP 1110 MOBILE_HTHRS_HHHAMP
GND
0111 MOBILE_NTHRS_HHHHAMP 1111 MOBILE_HTHRS_HHHHAMP

00 RM 亮
R69 34.8K STRAP2 R68 34.8K GND GND
03: PCI_DEVID[3] SKU0 0100
0402 1% COMMON 0402 1% COMMON
02: PCI_DEVID[2]
OUT
10
01: PCI_DEVID[1]
Strap2
00: PCI_DEVID[0]
R75 34.8K STRAP3 R74 34.8K
03: SOR3_EXPOSED 0 DISABLED 1 ENABLED
0402 1% COMMON 0402 1% COMMON

02: SOR2_EXPOSED 0 DISABLED 1 ENABLED

Strap3

11 A工 樂
01: SOR1_EXPOSED 0 DISABLED 1 ENABLED
10
OUT

00: SOR0_EXPOSED 0 DISABLED 1 ENABLED

R73 34.8K STRAP4 R72 34.8K
02: PCIE_SPEED_CHANGE_GEN3 0 DISABLED 1 ENABLED
0402 1% COMMON 0402 1% COMMON

4 01: PCIE_MAX_SPEED 0 GEN1 1 GEN23

Strap4 4
GND

60
00: DP_PLL_VDD_3V3 0 USE1V8 1 USE3V3

程 )
1) 課
5 5

NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY

ASSEMBLY BASE LEVEL GENERIC SCHEMATIC ONLY SANTA CLARA, CA 95050, USA
PAGE DETAIL STRAPS & FAN
NV_PN 600-12132-BASE-QS115ci203
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL PCB REV P2132-A01 PAGE 11 OF 15
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS. BOM REV A DATE 14-MAR-2013

A B C D E F G H
 A B C D E F G H

POWER SUPPLY I: PEXVDD, 5V

00
PEX_VDD
1.05V
1V_PLL
0.300
LB1 220R@100MHz

M
BEAD_0805 COMMON

C121 C116 C110 C103 C101

0
0.1UF 1UF 10UF 10UF 10UF
U1

RD 17 SI
16V 6.3V 6.3V 6.3V 6.3V
VFIX=5V 10% 10% 20% 20% 20%
1 IGO,IGOI X7R X5R X5R X5R X5R 1
12V_PEX 12V COMBINED_IGO DDC_5V 0402 0402 0603 0603 0805
COMMON COMMON COMMON COMMON COMMON COMMON
0.400 5V
R56 0 PS_5V_PROT_D FR1 1.8 PS_5V_PROT 1 3 0.400
IN OUT
0402 +0.05R 0.400 1206_F 5% COMMON
C39 C43 C42

GND/ADJ
COMMON
1UF 0.1UF 1UF

TAB
16V 16V 16V
10% 10% 10%
2D2 1

(C 96 C
X5R X7R X5R
SOD323 COMMON 0603 0402 0603

2
4
COMMON COMMON COMMON
GND
GND GND GND

GND

)2 7 ON 3V3_PEX
3.3V
3V3_PLL

F
5V = 5V @ 165mA 0.300

0
LB2 220R@100MHz
BEAD_0805 COMMON

C107 C112 C109 C99 C118

吳 15 jo ID
2 0.1UF 1UF 10UF 10UF 10UF 2
16V 6.3V 6.3V 6.3V 6.3V
Stuff SM78MCDCYR 315-0848-000 default 10% 10% 20% 20% 20%
X7R X5R X5R X5R X5R
315-0598-000:PS78M05G-T43R
0402 0402 0603 0603 0805
315-0535-000:UA78M05CDCYR COMMON COMMON COMMON COMMON COMMON
315-0525-000:APL78L05ECTRG
315-0848-000:SM78MCDCYR

積 04 ne EN GND

12V_PEX

源 27 pe TI PEX_VDD = 1.05V MEC2

MEC4

01 i( AL
COOLING SOLUTION 4PIN
SMD
COMMON
R95 Iripple=0.2A @ Iout=2A 4 connected mounting pins
COMMON

750 U5 EMI CLIP

FBVDDQ
3 3

1
2
3
4
5%
0603 SO08_I190X150_TI118X102 PEX_VDD
COMMON COMMON
3 VIN VOUT 6

PS_1V05_VCNTL 4 C79 R100 C82 GND 1

VCNTL DNI 3.57K 10UF GND
C69 C670 C671

(0
10UF R94 C72 16V Rt 1% 6.3V 1uF 10uF
2 EN 0402
560 1UF 10% 20%

裴
6.3V 6.3V 6.3V
20% 5% 6.3V
FB 7 X7R COMMON X5R 10% 20%
X5R
SNN_PS_PEXVDD_POK 1 POK 0402 0805 X5R X5R
GND
0603 10%
0603 9 PS_1V05_FB COMMON COMMON 0402 0603
COMMON X5R GND MEC5
COMMON 0402 SNN_PS_PEXVDD_NC 5 8 COMMON COMMON
NC GND R99 MEC3
COMMON SMD
11.3K GND GND COMMON
GND SMD
Rb 1% COMMON

00 RM 亮
0402
EMI CLIP
GND COMMON
EMI CLIP
GND

Vout = Vref * (1+Rtop/Rbot)

1.053 = 0.8 * (1+3.57k/11.3k) GND
1 GND
1 GND
PEX_VDD

11 A工 樂
GND
GND

Backdrive Prevention
4 4
MT2
MT_Hole_0.136 TM 5.5 BM 7.0 MT1 FM1 FM5

60
MT_Hole_0.136 TM 5.5 BM 7.0 1 SW_FB 1 SW_FB

)
PLACE BUFFER on BACKSIDE

3V3_PEX F_PAD_X F_PAD_X

程
C83 FM2 FM6
100PF
1 SW_FB 1 SW_FB
50V
5

5%
U502

1)
1
C0G
0402
Vout = 0.8V * (1+Rt/Rb) Reserve J8 ‐ J12 for Impedance F_PAD_X F_PAD_X

2
PEX_RST* 2
4
SC70_5
OUT
2 COMMON 3V3_PEX
1.05V = 0.8V * (1+3.57k/11.5k) check 1
FM3
SW_FB
IN
DNI DNI

課
COMMON GND
1G1D1S 3 DNI
3

R503 D Q16
10K DNI J11 J12 F_PAD_X
J8 J9
5%
3 R107 100K PEX_RST_D 1G SOT23 3 1 3 1 FM4
0402 1G1D1S
D Q18 0402 COMMON S
COMMON
2 4 2 4 2 1 SW_FB
COMMON GND 5% -20V
-3.0A
0.070@-4.5V,0.115R@-2.5V impedence impedence
R80 0 SOT23
PEX_RST_R* 1G COMMON
-9A
N/A X_PIN1*2 X_PIN1*2 GND GND GND GND
0402 +0.05R COMMON S 2 C74 100PF +12/-12V

C73 GND GND F_PAD_X

GND 60V 0402 50V
100PF 0.26A@25C
5%
3R 3V3_PROT MEM CLK HDMI/DVI TMDS signals
50V 0.31A C0G
5%
0.3W@25C
COMMON
MEM Data MEM CMD FBA_CLK0 / FBA_CLK0* IFPC_TXD0 / IFPC_TXD0*
+/-20V
C0G FBA_D<54> FBA_CMD<28> BOTTOM TOP
0402 R86 10K TOP BOTTOM 0.12MM / 0.101MM / 80ohm +/- 10% 0.1MM / 0.12MM / 90ohm +/- 10%
COMMON 0402 5% COMMON 0.102MM / 52ohm +/- 10% 0.102MM / 52ohm +/- 10% Reference L3 GND Reference L2 GND
5 GND Reference L2 GND Reference L3 FBVDDQ 5
GND 3V3_PROT = 3.3V @ 230mA

NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY

ASSEMBLY BASE LEVEL GENERIC SCHEMATIC ONLY SANTA CLARA, CA 95050, USA
PAGE DETAIL POWER SUPPLY I: PEXVDD, 5V
NV_PN 600-12132-BASE-QS1
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL PCB REV P2132-A01 PAGE 12 OF 15
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS. BOM REV A DATE 14-MAR-2013

A B C D E F G H
 A B C D E F G H

POWER SUPPLY II: FBVDDQ

00 M
0
RD 17 SI
1 1

12V_PEX

12V_PEX

(C 96 C
ER1595
2R2
ER1801
1R EB16
ED2 Chock 1.2u

)2 7 ON
BAT54S

EC1801 12V_M
1000pF

F
EC183 EC182 EC181

0
EC124 ER1596 22uF 22uF 22uF
MVDD_BOOT BOOT_C_M

0.1uF 0R

吳 15 jo ID
2 2

2
ER307 EQ40
UG_M UG_R_M 1 4

0R APM3023 SOT223 FBVDDQ

3
EMU42
1 8 PHASE_M
BOOT Phase EL64
2 7 ,IND CHOKE,1.6uH,20%,DIP-7.4x7.4x8.5/5.0mm,18A,5.8mOhm,8.5T,0.7mm,
HG COMP

積 04 ne EN
R234
1 2 3 6
GND FB

PGND
18K

1
4 5 ER308 EQ41 C1034 C1035 C1036

+
LG VCC LG_M LG_R_M 1 4 EC164 EC159 EC169 EC346 EC347 EC348 EC184 100pF 100pF 100pF
9 uP1543 10uF 10uF 10uF 10uF 10uF 10uF 820uF

2
R101
0R APM3023 SOT223

3
DNI
1%
0402

源 27 pe TI
COMMON ER12
FB_M
12V_PEX
1.62K C1038 C1039 C1040
ER13 1000pF 1000pF 1000pF

1
EC7 Rtop ER11
R236
0R
1.05K

4700pF 0

01 i( AL

2
ER20
2R2 Rbot

3
C1042 C1043 C1044 3
10nF 10nF 10nF

2
EMU42_VCC
R235
DNI
ER21
30K

1
EC1693 FBVDDQ = 0.6 * ( 1+ ( ER12 / ER13 ) )

(0
EC168 10pF

裴
0.1uF
EC1694
22nF

12V_PEX
NVVDD MVDD_COMP

00 RM 亮
2

R843
5.1K
1

PWR_ENABLE#

11 A工 樂
R841
4.75K
2

PSEQ_VDDCUP 1 Q840
1

MMBT3904

C841
2

DNI
4 GND
4
DNI
2

GND

60 )
3

PSEQ_MVDD_EN
R846
2 1 1 Q842

程
MMBT3904
5.1K
2

GND

1) 課
5 5

NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY

ASSEMBLY BASE LEVEL GENERIC SCHEMATIC ONLY SANTA CLARA, CA 95050, USA
PAGE DETAIL POWER SUPPLY II: FBVDDQ
NV_PN 600-12132-BASE-QS1
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL PCB REV P2132-A01 PAGE 13 OF 15
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS. BOM REV A DATE 14-MAR-2013

A B C D E F G H
 A B C D E F G H

POWER SUPPLY III: NVVDD

00
12V_PEX

CLOSE TO FET

M
C49 C48 C46 C60 C47
0.1UF 10UF 10UF 10UF 10UF

0
16V 16V 16V 16V 16V
10% 10% 10% 10% 10%

RD 17 SI
X7R X5R X5R X5R X5R
0402 1206 1206 1206 1206
1 1
COMMON COMMON COMMON COMMON COMMON

12V_PEX GND

(C 96 C
R90
0
2G1D4S D 7
+0.05R U3 Q6
0402
COMMON 0.400 300-0627-000
VR =0.6V
0.400
R63 0 PS_NVVDD_UG_R 1 G COMBI_2G1D4S 300-0642-000
PSOP8 COMMON
COMMON 0402 +0.05R COMMON 5 S 2 25V 300-0618-000
PS_NVVDD_VCC 5 VCC 1 PS_NVVDD_BOOT C57 0.1UF 3 11.3A@25C

BOOT 0.400 9.3m@10V

98A
4

)2 7 ON
0.400 12V 0402 16V 1.95W@25C
C67 10% 6 +/-20V
Iripple = 5A @Iout = 15A NVVDD
1UF X7R
16V COMMON
PS_NVVDD_UG
10% HDRV 2
131-0613-000
X5R
0603 PHASE 8 PS_NVVDD_PHASE
0.400
L5 0.470uH 16A 1.00V 0.400
COMMON TH COMMON

2G1D4S D 7 0.0008R C51 C45

PS_NVVDD_EN 7 COMP/EN Q5 C50 C78 C94
GND 50A 820uF 820uF
2200PF 10UF 10UF

F
0.200 300-0654-000 41A

0
50V 6.3V 6.3V COMMON COMMON
3 GND LDRV 4
PS_NVVDD_LG
0.400 1 G COMBI_2G1D4S 300-0644-000
20% 20%
COMMON 10% 20% 20%
9 GND PS_NVVDD_FB
FB 6 0.200 5 S 2 25V
14A@25C
300-0619-000
X7R X5R X5R 2.5V 2.5V
3 5.2m@10V 0402 WILL STUFF 0.47UH: 0805 0805 AL POLYMER AL POLYMER
R67 C44 4 146A
COMMON 131-0479-000
R93 COMMON COMMON 5.0A@105C 5.0A@105C

吳 15 jo ID
2W@25C
2 10K 100PF 100 2

PS_NVVDD_FET_RC
+/-20V 0.007R 0.007R
6 131-0425-000
TH_D63P25 TH_D63P25
5% Roc 50V 5%
GND 131-0467-000
0402 5% 0402
COMMON 131-0611-000 COMMON
C0G
0402 0.400 131-0612-000 LOCAL SENSE
COMMON GND 131-0613-000 NEAR VRM GND GND GND GND

R57
2.2
GND GND
5%

積 04 ne EN
1206
C66 15PF
COMMON
0402 50V
5%
C0G
C59 COMMON
GND
0.01UF R105 0 PS_NVVDD_FB_RC C71 6800PF
16V
12V_PEX 0402 +0.05R COMMON 0.200 0402 50V
10%
3V3_PEX 10%
X7R

源 27 pe TI
X7R
0402 COMMON
R66 COMMON REMOTE SENSE
10K C58 PS_NVVDD_CP_RC R81 15K R98 Rt 1.18K PS_NVVDD_VSEN R97 0 NVVDD_SENSE 2
R120 5% 15PF IN
0.200 0402 5% COMMON 0402 1% COMMON 0.200 0402 +0.05R COMMON
1K 0402 50V
COMMON 1B1C1E 3
5% C 5% C70
Q7B C0G
0402 R79 R87 1000PF
COMMON 1B1C1E 6 PS_NVVDD_EN* B5 0402
R106 C Q7A SOT363
COMMON
10K 3.48K 50V
NO STUFF
COMMON 10%
10K THERM_OVERT_R* B2 E 4 5% R85 Rb 1% R91 DEFAULT
10,12

01 i( AL
IN 0402 60.4K 0402 14.3K X7R
SOT363
0402 5% COMMON COMMON COMMON 0402
COMMON
GPIO_THERM_OVERT* Rb0 1% 1% Rb2
E 1 0402 0402
COMMON
R96 C63
COMMON COMMON
10K 1UF
3 5% 16V 3
0402 10%
GND
6 GPIO11_NVVDDCTL GND
COMMON X5R 1G1D1S
D Q9A GPIO6_NVVDDCTL 3
0603 0.200 1G1D1S
NVVDD Power Sequencing COMMON GND GND Q8B D
SOT363
10 GPIO11_NVVID0 2G COMMON
IN SOT363
S 1 G5 GPIO6_NVVID2

(0
COMMON 10
R76 IN
GND GND GND GND 60V 4 S
10K

裴
0.115A R78
7.5R@4.5V; 5R@10V; 60V
5% 0.8A 0.115A 10K
0.2W@25C 7.5R@4.5V; 5R@10V;
0402 +/-20V R88 R92 0.8A 5%
COMMON 0.2W@25C
0402
29.4K 7.15K +/-20V
COMMON
1% 1%
GND 0402 0402
Rb1 Rb3
Vout = Vref * (1+Rtop/Rbot) COMMON COMMON GND
GND

00 RM 亮
GND

VID[4:0] NVVDD GPIO5_NVVDDCTL

1G1D1S 6
D Q8A 0.200 3V3_PEX
00000 0.8000V
00001 0.8125V SOT363
10 GPIO5_NVVID1 2G COMMON
00010 0.825OV IN R89
S 1
00011 0.8375V R77 GPIO1_NVVDDCTL 10K
Bootup Voltage set to 0.9000V 60V 3 1G1D1S
10K R104
00100 0.8500V 0.115A
Q9B D 5%

11 A工 樂
7.5R@4.5V; 5R@10V;
5% 3.57K 0402
00101 0.8625V 0.8A

0402
0.2W@25C COMMON
00110 0.875OV +/-20V Rb4 1% SOT363 G5 GPIO1_NVVID3
COMMON COMMON 10
0402 IN
00111 0.8875V PWM Freq Vref(V)
COMMON 4 S
DEFAULT 01000 0.9000V APW8722: 300kHz, 0.6V
GND 60V
01001 0.9125V EM5303AGE: 300kHz, 0.6V 0.115A
7.5R@4.5V; 5R@10V;
01010 0.925OV RT8120AGS: 300kHz, 0.6V 0.8A
GND 0.2W@25C
01011 0.9375V AP3586AMTG: 300kHz, 0.6V +/-20V

4 01100 0.9500V 4
01101 0.9625V
GND

60
01110 0.975OV
01111 0.9875V

)
10000 1.0000V
10001 1.0125V

程
10010 1.025OV
10011 1.0375V
10100 1.0500V Vout = Vref * (1+Rt/Rb)
10101 1.0625V
10110 1.075OV 0.8V = 0.6V * (1+1.18k/3.48k)

1)
10111 1.0875V
11000 1.1000V
11001 1.1125V
values for Rb1, Rb2 GPIO0_NVVDDCTL 3 1G1D1S
11010 1.125OV Vref Rb1 Rb2 Rb3 Rb4 Rb5 Q11 D

課
11011 1.1375V
Rb3, Rb4 and Rb5
11100 1.1500V SOT23_1G1D1S G1 GPIO0_NVVID4
11101 1.1625V
will be calculated based COMMON IN
10
2 S
11110 1.1750V 0.6V 60.4k 29.4k 14.3k 7.15k 3.57k R84
11111 1.1875V
on the needed voltages 60V
0.3A 10K
2R@10V
0.8A 5%
0.35W
+/-20V 0402
COMMON
GND

GND

5 5

NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY

ASSEMBLY BASE LEVEL GENERIC SCHEMATIC ONLY SANTA CLARA, CA 95050, USA
PAGE DETAIL POWER SUPPLY III: NVVDD
NV_PN 600-12132-BASE-QS1
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL PCB REV P2132-A01 PAGE 14 OF 15
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS. BOM REV A DATE 14-MAR-2013

A B C D E F G H
 A B C D E F G H

DECOUPLING FOR CORE POWER_BOTTOM

00 M
0
RD 17 SI
1 1

(C 96 C
)2 7 ON
0 F
NVVDD

吳 15 jo ID
2 2
C509 C506 C517 C513 C512 C511 C510 C514 C520 C519 C518
1UF 1UF 1UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
10% 10% 10% 20% 20% 20% 20% 20% 20% 20% 20%
X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
0402 0402 0402 0805 0805 0805 0805 0805 0805 0805 0805
COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON

積 04 ne EN
GND

DECOUPLING FOR NVVDD UNDER GPU

源 27 pe TI
FBVDDQ PEX_VDD 1V_PLL

C508 C505 C503 C516 C502 C501 C521 C507 C504 C515

01 i( AL
1UF 1UF 1UF 4.7UF 1UF 1UF 4.7UF 1UF 1UF 4.7UF
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
10% 10% 10% 20% 10% 10% 20% 10% 10% 20%
X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
0402 0402 0402 0603 0402 0402 0603 0402 0402 0603
3 3
COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON

GND GND GND

(0 裴
DECOUPLING FOR FBVDDQ UNDER GPU DECOUPLING FOR PEX_VDD UNDER GPU DECOUPLING FOR 1V_PLL UNDER GPU

00 RM 亮
4

11 A工 樂 4

60 程 )
1) 課
5 5

NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY

ASSEMBLY BASE LEVEL GENERIC SCHEMATIC ONLY SANTA CLARA, CA 95050, USA
PAGE DETAIL DECOUPLING FOR CORE POWER_BOTTOM
NV_PN 600-12132-BASE-QS1
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL PCB REV P2132-A01 PAGE 15 OF 15
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS. BOM REV A DATE 14-MAR-2013

A B C D E F G H