Low-Temperature Soldering-TPCAG2LTS

Low-Temperature Soldering
Morgana Ribas, et al.

Alpha Assembly Solutions
The Printed Circuit Assembler’s Guide to...™
Morgana Ribas, Tom Hunsinger, Traian Cucu,
Ramakrishna H V, Garian Lim and Mike Murphy
ALPHA ASSEMBLY SOLUTIONS
© 2018 BR Publishing, Inc.

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About the Authors
Morgana Ribas, Ph.D.
Manager, Metals Technology Group—R&D
Morgana is a metallurgical engineer with a
master's degree in extractive metallurgy from
UFRGS in Brazil and a Ph.D. from Rice University in
the United States. Currently, Dr. Ribas is manager
for the metals technology group at Alpha Assembly
Solutions. Her work has appeared in more than 50
publications, including technical journals, confer-
ence proceedings, and patents.
Tom Hunsinger
Vice President of Global Marketing
Tom has over 13 years of experience in the elec-
tronics assembly industry. He has held several
positions in both the United States and Asia
while working to provide innovative products and
assembly solutions.
Traian Cucu, Ph.D.

Group Leader, Global Applications and Technologies Expert
Group (GATE)—R&D
Traian received his master’s degree in electrical
and power engineering from Politehnica Univer-
sity of Timisoara in Romania, and his Ph.D. in
electronics, telecommunications, and information
technologies from Polytechnic University of Bucha-
rest, also in Romania. He has been working in the electronic assembly industry
since 1999 and had his work published in more than 40 publications, including
technical journals, conference proceedings, and application notes.
About the Authors
Ramakrishna H V, Ph.D.
Manager of Chemistry
Dr. Ramakrishna H V received both a bachelor’s and
master’s degree in polymer science and a Ph.D. in
polymer science and technology from the University of
Mysore in India. With more than 10 years of experience
in the formulation of soldering materials, he is currently
the manager for solder paste development activities at
Alpha Assembly Solutions, India.
Garian Lim
Interconnect Solution Portfolio Manager
Alpha Advanced Materials
Garian is the interconnect solution portfolio manager
for Alpha Advanced Materials (AAM). He is responsible
for soldering product solutions for semiconductor pack-
aging applications. He has more than 10 years of expe-
rience working with materials in the semiconductor
assembly market. Garian has a bachelor’s and master’s
degree in mechanical engineering from Nanyang Tech-
nological University of Singapore.
Mike Murphy
Director of Marketing—Core Products
Mike has been in the electronics assembly industry for
over 20 years in a variety of technical and commercial
roles. He has presented at numerous industry events
and published many technical articles. In his current
role, Mike oversees a global team of portfolio manage-
ment professionals who are responsible for the total life
cycle management of a diverse range of specialty mate-
rials for the global electronics assembly market.
Peer Reviewers
Dr. Raiyo Aspandiar
Senior Engineer
Intel Corporation
Raiyo Aspandiar has worked at Intel Corporation
in the boards and system assembly facility in Hills-
boro, Oregon, since 1983. He was part of the team
that introduced surface mount technology to Intel.
Over the years, he has participated in the develop-
ment of PCBs and assembly processes for moth-
erboards and mobile modules, which contained
a myriad of packages for the Intel microprocessors, chip sets, and connectors.
Currently, Raiyo is working on and low-temperature soldering development. Raiyo
has published more than 65 technical papers and is the joint holder of 15 patents
in the electronics packaging and manufacturing field. He is also a former member
of the SMTA Board of Directors and the SMTA Technical Committee and received
the SMTA Member of Technical Distinction Award in 2009. He is a graduate of
Stanford University and the Indian Institute of Technology Bombay.
Happy Holden
Consulting Technical Editor
I-Connect007
Happy Holden is the retired director of electronics
and innovations for Gentex Corporation. Happy is
the former chief technical officer for the world’s
largest PCB fabricator, Hon Hai Precision Indus-
tries (Foxconn). Prior to Foxconn, Happy was the
senior PCB technologist for Mentor Graphics and
the advanced technology manager at Nan Ya/Westwood Associates and Merix.
Happy previously worked at Hewlett-Packard for over 28 years as director of PCB
R&D and manufacturing engineering manager. He has been involved in advanced
PCB technologies for over 47 years.
Contents
1 Introduction
Chapter 1
3 Low-Temperature Soldering
Chapter 2
9 History and Overview of Low-Temperature Solders
Chapter 3
19 Second Generation Low-Temperature Solders
Chapter 4
29 Using the Right Chemistry
Chapter 5
39 Advanced Applications for Low-Temperature Solders
49 Conclusion
50 Glossary
54 References
56 About Alpha Assembly Solutions

Introduction
With the movement to use lead-free solder in electronics assembly,
a great deal of research and focus has been placed into the search
for viable alternatives to SnPb alloys. It is clear that the domi-
nant alloys used in modern electronics assembly are variants on
the SnAgCu (commonly known as SAC) alloy system. Over time,
however, several factors have combined to contribute to an increase
in the use of alternative alloys with lower melting points. This book
provides an introduction to the evolution of modern low-tempera-
ture soldering, illustrates the importance of chemistry when devel-
oping low-temperature solder (LTS), and discusses advanced and
emerging applications where lower melting point alloys can provide
unique assembly solutions.
1
Chapter 1
Ever since the printed circuit board (PCB) assembly industry moved to lead-free
assembly processes, low-temperature soldering has been a hot topic and a top
priority on the new alloys agenda. But what is the definition of low-tempera-
ture alloys? The basic structure of the assembly remains the same as SnPb
materials. An alloy (usually containing
tin) is used to create a joint between
a pad and a component termination.
The joint plays a mechanical and elec-
trical role, and sometimes a thermal
role. Figure 1.1 shows a typical joint
formed with a SAC305 alloy used to
assemble a surface mount device
(SMD) capacitor to a PCB. Figure 1.2
illustrates a cross section of a typical
lead-free joint.
Figure 1.1: SMD assembled with solder paste. The concept of low-temperature
solder materials has seen slight
changes ever since the transition
from lead-containing to lead-free
assembly processes. It all started
with the adoption of the SAC family of
lead-free alloys when a low-temper-
ature process was understood to be
any process using alloys with lower
processing temperatures (lower
melting points) than the SAC family.
This meant everything below 220°C.
Figure 1.2: Cross-section of a lead-free SMD joint.
3
Table 1.1: Lead-free alloys commonly used in the assembly industry.
Table 1.1 provides examples of solidus/liquidus temperatures for common

SAC and low-temperature alloys used in the industry. This is an informative
non-exhaustive list, as there are many more alloys used in the field.
As the assembly industry was look-ing for alternatives for lead-free alloys
that would deliver a performance close to or better than SAC alloys, a more
granular hierarchy came into use, although nothing has been standardized
or generally agreed upon across the industry. Figure 1.3 presents a proposed
hierarchy and set of definitions.
The joint in lead-free processes (both SAC and low-temperature alloys) is still
formed in the same way as the lead-containing process. The connection is
made between the leads/contacts and sometimes spheres of a component
and a copper pad. The same pad/component finishes are used with the obser-
vation that all the lead-containing materials have been replaced by lead-free
materials. SAC alloys are typically used instead of lead-containing alloys for the
hot air solder leveling (HASL) process. As a result, the joint will have the same
Figure 1.3: Classification of the assembly process based on the peak reflow temperature.
4
type of intermetallic compound (IMC)
(SnCu, SnNi, etc.) (Figure 1.4). There
will be a noticeable difference in the
intermetallic thickness between a
SAC process and a low-temperature
assembly process. When compared
with a joint formed with a SAC alloy
in a SAC assembly process, the joint
formed with a low-temperature, high
bismuth content alloy will have a
thinner intermetallic.
Figure 1.4: Lead-free joint structure with an
SnNi IMC layer. There have been numerous studies
looking to find the right lead-free, low-temperature alloy for the assembly
industry. High bismuth content alloys (35–60% bismuth) have emerged as the
top choice, as the sum of their properties best serves the needs of the assembly
industry today. Recently, more families of alloys with liquidus temperatures
below or very close to 200°C have come under scrutiny as the industry aims
to improve solder performance even further without increasing the assembly
temperatures. Figure 1.5 shows the BiSn phase diagram [1].
Although lead-free alloys containing bismuth were initially considered during
the transition to lead-free materials, they have dropped from the list of candi-
dates due to the lower melting ternary SnBiPb phase. Once the industry moved
to lead-free materials, however, the concern of the low-melting ternary SnBiPb
phase was reduced, and bismuth containing alloys became interesting again.
Figure 1.5: BiSn phase diagram [1].

5
Looking at the assembly processes, high bismuth content alloys could theoret-
ically be used in both wave soldering processes and surface mount technology
(SMT). However, the high bismuth content alloys expand in volume as they
cool down and solidify, which can be a problem for wave soldering equipment.
The expanding material could break parts of the equipment—wave nozzles,
pumps, guides—if the machine is stopped for maintenance or is stopped
during normal breaks in production flow. In SMT (using solder paste), the alloy
is used in powder to prevent expansion from creating a problem.
For the SMT process (using solder paste), new requirements need to be consid-
ered while formulating fluxes due to high bismuth content alloys. The lower
reflow temperature employed to form a joint with high bismuth content alloys
and the bismuth compounds are new variables that need to be examined
when chemistry platforms are considered for the flux development. Namely,
activator platforms activated at a lower temperature, are capable of coping
with oxides and other metal compounds at the reflow temperatures are used
for low-temperature alloys. For the no-clean solder pastes, the rosin/resin
systems are still used because they perform best from an electrical reliability
point of view by creating a residue that is electrically benign after the reflow
process. Today, there are commercially available bismuth-containing solder
pastes for both the no-clean process and the cleanable process (water soluble
solder pastes).
The main deposition process for high bismuth content alloy pastes is stencil
printing, but there are still other deposition processes employed, such as
dispensing, jetting, dipping, etc. There are also chemistries available today that
are capable of achieving the rheological properties needed for each of the
aforementioned deposition processes, making the process very flexible and
allowing a wider process window for manufacturers.
Why look at a low-temperature assembly process in the first place? The
answers to this question have changed since the transition to lead-free mate-
rials and are twofold. One component is related to the assembly process and
the second to the environment, although they are intertwined and create
a compelling value proposition. Looking at the assembly component, low-
temperature materials enable the use of a “two-tier” assembly process for
double-sided populated boards, or same side assembly with multiple steps. A
SAC process is used for the first reflow and a low-temperature process is used
for the second reflow. This avoids having a second reflow of the joints that
were assembled in the first step and can be extended to a multi-tier process
when alloys are chosen accordingly (Table 1.1).
Another benefit, particularly for high bismuth content alloys, is that the
6
low-temperature assembly process enables a smooth transition from wave
soldering (using SAC materials) to a pin-in-paste process (reflow process)
without the need to change any of the materials. This is because the lower
processing temperatures/peak temperatures used for the low-temperature
SMT assembly process are in the same range that a populated PCB would expe-
rience in a SAC wave assembly process (the peak reflow for the low-tempera-
ture SMT process is in the range of 155–165°C for the SnBi and SnBiAg family
of alloys). By using lower peak temperatures during assembly, thermal stress
on components is greatly reduced, which leads to significantly lower failure
rates. This has a positive impact on the repair volume because it decreases
the number of units that need repair for the fully assembled units after the
assembly process. It also has a positive impact on the field returns, which
positively influences the production cost. An additional benefit brought by the
transition to low-temperature SMT assembly is potential energy savings by
moving from a SAC SMT assembly process to a low-temperature SMT process
because there is less energy needed to heat up and maintain an oven in func-
tion. As more processes are migrating to low-temperature and more data is
becoming available, a quantifiable model can be developed.
From the environmental point of view, a low-temperature process is a greener
process versus a SAC assembly process because it reduces the carbon foot-
print of the assembly facility. Considering the present legislation and the
existing trend towards a greener planet, this becomes an important benefit
that enables the industry to move towards more environmentally friendly
processes.
Lately, high bismuth content alloys made a large impact when they have
enabled the use of high density microprocessors with multiple dies on the
same package. These are big packages with thousands of I/Os that are prone
to severe warpage during the SAC reflow process. By migrating to a low-
temperature process (e.g., using one of the high-reliability, low-temperature
(HRL) alloys), warpage during the liquidus state can be substantially reduced
or eliminated, allowing high-performance chips to be used in new designs by
board manufacturers. The lower warpage of the packages reduces the risk of
forming certain types of solder joint defects, thereby improving solder joint
quality and yield.
Lead-free assembly processes have been used for a while now, and low-
temperature materials have been available and used in niche applications.
However, in the past few years, the combination of new component designs,
reliability requirements, the revival of environmentally conscience processes,
and the recent low-temperature alloy developments have made the low-
temperature assembly process a compelling candidate.
7
Chapter 2
History and Overview of

Low-Temperature Solders
From the Roman aqueducts to the artistic creations of the past millennia [2],
the soldering evolution from gold-based to tin-lead solders has been dictated
by human needs. For the fledgling electronics industry of the early 1900s, the
use of eutectic SnPb solders became a natural choice. It was largely available,
relatively low in cost, had good wetting, and a melting temperature (183°C)
that was low enough for electronics components.
As health-related concerns about lead poisoning grew, starting with its ban
from plumbing use, it was just a matter of time before the electronics industry
had to review its use in solder. The European Union’s Restriction of Hazardous
Substances (RoHS) Directive was introduced in 2001 and established a time-
line for eliminating lead from soldering on electronics. SAC solder alloys were
chosen as the best alternative to eutectic SnPb.
The replacement of SnPb by SAC solder alloys brought many changes to the
electronics assembly and packaging segments. For example, SAC305 (96.5%
tin, 3% silver, 0.5% copper) melts between 217°C and 221°C and requires
reflow temperatures of at least 240–255°C. This represented an increase of
20–35°C in reflow temperatures. Consequently, PCBs and components were
redesigned to include materials that could withstand the higher reflow temper-
atures required by SAC solder alloys [3]. This was the first major inflection point
in electronics assembly where the soldering technology had to adapt to meet
human needs.
Reducing the soldering temperature has been on top of the industry’s wish list
since the adoption of lead-free soldering. Reduced soldering temperatures can
significantly reduce energy and materials costs, which make it a very compel-
ling proposition. Why has its adoption been so slow?
Basically, the soldering temperature is dictated by the melting behavior of a
solder alloy. Once the soldering temperature reaches the solidus temperature
of the solder material, the alloy starts its transformation from a solid to liquid
9
state. It becomes completely liquid at the liquidus temperature. If the liquidus
and solidus temperatures are the same, the alloy is eutectic. However, if this
transformation is completed within a range of temperatures (i.e., the solidus
and liquidus temperatures are different), then the alloy is non-eutectic. Table
2.1 shows examples of eutectic and non-eutectic solder alloys.
Table 2.1: Melting temperatures of known solder alloys.
Alloying additions such as bismuth, indium, and gallium can be used to reduce
the melting temperature of tin-based solders. Among these, SnBi alloys have
a competitive advantage over SnIn or SnGa due to their lower cost and higher
availability. In the late ‘90s, SnBi alloys gathered a lot of attention as possible
substitutes for eutectic SnPb. From a manufacturing point of view, using a
binary eutectic alloy composition was quite attractive, but there were concerns
about limitations due to its lower melting point. For example, the National
Center for Manufacturing Sciences concluded that Sn-58Bi could potentially
replace eutectic SnPb for consumer electronics and telecommunications, but
it excluded under-the-hood and aerospace applications[4]. It showed moderate
fatigue life, higher than eutectic SnPb solder, but lower than SAC or SnAg [4–5].
Another reason the eutectic Sn-58Bi was not considered as a substitute for
SnPb was its poor resistance to drop and mechanical shock. Eutectic SnBi
solders are brittle and have poor resistance to mechanical drop shock.
However, these issues can be addressed by using certain performance addi-
tives to increase its ductility, strength, mechanical reliability, and fatigue life.
Plastic deformation in an atomic lattice can be controlled by mechanisms such
as solid solution strengthening, grain refinement, and precipitate strength-
ening. Bismuth is one of the few elements that forms a solid solution with tin:
up to about 4 wt% in solid solution and 10 wt% at the eutectic temperature
[1, 6]. In this mechanism, some of the tin atoms are substituted by the larger
bismuth atoms, which creates strain in the atomic lattice that contributes to
the strengthening of the tin matrix.
Tensile strength tests are relatively simple to execute and can evaluate how
10
Figure 2.1: Schematic stress-strain curve and test specimen used in tensile testing.
much a material can deform when pulled to its complete rupture. Figure 2.1
shows a schematic stress-strain curve obtained during a tensile test. The first
(linear) part of the curve represents the elastic deformation of the material
(i.e., a deformation that can be recovered once the stress is removed). The
maximum elastic deformation is marked by the yield point, which is generi-
cally given at a permanent deformation of 0.2% of the original length of the
sample. Once the material passes this point, it also undergoes plastic defor-
mation, which cannot be reversed to its original dimensions, marking the yield
strength (YS) of the material. The ultimate tensile strength is the maximum
stress that a material can sustain before its rupture point.
When the concentration of bismuth in the alloy is above its solubility limit in
tin, bismuth precipi-
tates are formed in
the tin-rich phase,
which can affect the
mechanical properties
of the resulting alloy.
For example, Figure
2.2 presents the ulti-
mate tensile strength
(UTS) and elonga-
tion of SnBi alloys
with bismuth content
decreasing from 58 to
Figure 2.2: Tensile properties of SnBi alloys [7]. 40 wt%. There is little
variation in the tensile
strength, which is sometimes within its standard deviation. The yield strength
(not shown) follows the same trend as the UTS, so the elastic deformation is
only slightly affected by the bismuth content. However, the significant increase
in elongation when decreasing bismuth from 58 to 40 wt% shows that the
plastic deformation of SnBi alloys is highly dependent on its bismuth content.
11
Figure 2.3a shows that eutectic SnBi alloy microstructures have a distinct
appearance, with bismuth lamellas precipitating in a tin-rich phase [8–9]. Micro-
structure refinement is generally associated with higher resistance to plastic
deformation caused by dislocation movement. Small additions of silver can be
used for refining the eutectic microstructure [10], as exemplified in Figure 2.3b
for Sn-57.6Bi-0.4Ag. However, other alloying additions such as nickel, copper,
and cobalt can refine the eutectic microstructure even further [11]. Figure 2.3c
shows the microstructure of Alpha’s patented SBX02 solder alloy, which does
not contain silver but is more refined than standard Sn-57.6Bi-0.4Ag.
(a) (b) (c)

Figure 2.3: (a) Sn-58Bi, (b) Sn-57.6Bi-0.4Ag, and
(c) SBX02 microstructures (Bi: light grey, Sn: dark grey).
The effect of adding small alloying elements to the eutectic SnBi is also visible
in the mechanical properties of other eutectic SnBi alloys (Figure 2.4). The
addition of 0.4 wt% silver results in 6% higher UTS, whereas increasing silver
content to 1 wt% raises the UTS 8%, which are both above UTS 5% standard
deviation. However, changes in yield strength and elongation with silver addi-
tion in the range between 0.4 to 1 wt% are within the respective standard
deviations. Other elemental additions used in SBX02 result in further improve-
ment of UTS (10%), yield strength (14%), and elongation (37%), which are all
Figure 2.4: UTS, YS, elongation, and elastic modulus (E) of eutectic SnBi alloys.
12
above their respective standard deviations. Such improvement over Sn-58Bi
mechanical properties is a result of SBX02 microalloying additions that are
designed for microstructure refinement and strengthening.
The improved mechanical properties of SBX02 also result in improved drop
shock resistance due to a combination of solid solution strengthening, grain
refinement, precipitate hardening, and diffusion modifiers[7, 12]. The first three
were described earlier in this chapter, whereas diffusion modifiers are minor
alloying additions that control the growth of interfacial intermetallics and
interfacial voids in the solder alloy. The choice of which alloying element(s) to
add depends on its relationship with the alloy system and the resulting ther-
modynamic and kinetic properties. The effect of such additions in the alloy
can be verified from testing the mechanical properties of the bulk alloy (e.g.,
tensile test) or by using proxy tests for evaluating the solder joint performance
(e.g., shear strength, thermal cycling, and drop shock tests).
For example, Figure 2.5 shows the cumulative failures of drop shock tests using
CTBGA84 components and conducted as per the JEDEC standard JESD22-B111,
which is used to evaluate corresponding board-level drop performance of
handheld electronic devices. The drop shock characteristic life (63.2% failures)
of Sn-58Bi is very low (about 118 drops). Small silver additions of 0.4 wt%
contribute to precipitate strengthening of the alloy, as silver has limited solu-
bility in the eutectic phase, which improves the drop shock characteristic life
in 25% to about 147 drops. SBX02 alloy composition yields drop shock char-
acteristic life to about 306 drops, 160% higher than Sn-58Bi and 108% higher
Figure 2.5: Drop shock performance of eutectic SnBi solders.
13
than Sn-57.6Bi-0.4Ag. It is important to note that these results were obtained
using ball grid array (BGA) components with SAC305 balls (i.e., SnBi solder and
SAC305 form mixed solder joints that reflowed under a regular soak profile
with peak reflow temperature around 175°C).
Another important property that characterizes solder joint mechanical reli-
ability is its performance under thermal cycling. In case a solder joint transi-
tions between extreme cold and hot environments, stresses are generated
due to the coefficient of thermal expansion (CTE) mismatch between substrate
and solder alloy. However, the thermomechanical reliability of the solder joint
depends on the ability of the solder alloy to withstand these stresses. One way
to evaluate this is through testing high-temperature creep properties of the
solder alloy. Creep is a time-dependent deformation that can occur when the
homologous temperature (TH) is generally above 0.5.
It is important to note that as this process is time-dependent and thermally
activated, the mechanical strength of an alloy will be less impacted at lower
temperatures. For example, SAC305’s homologous temperature at 25°C is 0.6,
and at 125°C it reaches 0.8. Considering the definition of creep, SAC305 solder
joints can start creeping at room temperature. However, it is well known that it
will not degrade at this temperature for several years under normal operating
conditions, but instead will degrade faster at 125°C (TH=0.8).
Eutectic SnBi solders at 85°C have a homologous temperature of 0.87 (i.e.,
its solder joints will undergo permanent deformation under stress and have
degraded mechanical performance). Table 2.2 shows the creep behavior of
SBX02 compared with Sn-57.6Bi-0.4Ag at 85°C and 150 N. Creep rupture time
indicates the creep strength, whereas creep strain indicates the creep elonga-
tion. SBX02 and Sn-57.6Bi-0.4Ag have comparable creep elongation. However,
minor alloying additions in SBX02 result in remarkable improvement of creep
strength over Sn-57.6Bi-0.4Ag, which is an indication of higher fatigue resis-
tance. Comparatively, SAC305 creep strength would be one order of magni-
tude higher, if measured in the same experimental conditions, because its
homologous temperature is lower (TH = 0.72).
The fatigue life of a solder joint is generally estimated by performing thermal
cycling tests. In these tests, the number of failures can be actively monitored
Table 2.2: Creep behavior at 85°C and 150 N load.
14
Table 2.3: Failures after thermal cycling test.
by measuring discontinuities in electrical resistance or passively monitored by

cross-sectioning and analyzing solder joints for crack occurrences. Table 2.3
shows the cumulative failures of Sn-57.6Bi-0.4Ag and SBX02 under a thermal
cycling profile from -40°C (10 min.) to +125°C (10 min.) tested per the IPC9701
standard. These failures refer to CTBGA84 components using SAC305 balls
that form mixed eutectic SnBi/SAC305 solder joints and were reflowed using
an ordinary soak reflow profile with around 175°C peak. At 200 thermal cycles,
Sn-57.6Bi-0.4Ag already had 17.7% failures and increased to 23.5% at 800
cycles. In the case of SBX02, a single component out of 36 failed around 500
cycles, and no more failures were observed until the test was interrupted.
The early failures of Sn-57.6Bi-0.4Ag were well characterized by this data, but
SBX02 performance could be even better if its single failure is an outlier.
Figure 2.6 shows cross-sectioning
and a microscopic analysis of solder
joints samples at 200, 500, and 1,000
cycles. Small cracks are visible in
Sn-57.6Bi-0.4Ag within 200 cycles,
confirming the electrical disconti-
nuity data. Progressively larger cracks
are observed in the joints at 500 and
1,000 cycles. For example, Figure
2.7 shows an example of the failure
mode in Sn-57.6Bi-0.4Ag with a brittle
fracture at the interfacial intermetal-
Figure 2.6: Eutectic SnBi/SAC305 mixed solder lics. The first identifiable crack with
joints after thermal cycling. SBX02 can be seen between 500 and
800 thermal cycles, but it is so small
that it cannot be seen at solder joint
magnification level.
Microscopic evaluation of chip resis-
tors after thermal cycling provides
information about the thermal
cycling performance of eutectic SnBi
Figure 2.7: Failure mode of Sn-56.7Bi-0.4Ag
solder after thermal cycling.
solder joints. Unlike the BGAs evalu-
15
Figure 2.8: Eutectic SnBi solder joints after thermal cycling.
ated here that form SAC305/SnBi mixed solder joints, the solder joints in the
chip resistors are made entirely of the low-temperature alloys. Figure 2.8
shows cross-sections of chip resistor solder joints after 200, 500, 800, and
1,000 cycles. Both alloys formed similar solder fillets that indicate compa-
rable joint formation. Some voids were visible in both alloys, but cracks were
identified much later than in the BGAs. For Sn-57.6Bi-0.4Ag, cracks appeared
between 800 and 1,000 cycles, whereas no cracks were observed for SBX02
until the test was interrupted. Figure 2.9 shows the effect of thermal cycling
on the shear strength of 1206 chip resistors assembled Sn-57.6Bi-0.4Ag and
SBX02. Both alloys demonstrated similar behavior and shear strength up to
200 thermal cycles, but around 500 cycles, Sn-57.6Bi-0.4Ag decreased in shear
strength and cracks became clearly visible at 800 thermal cycles.
Figure 2.9: Effect of thermal cycling on shear strength.
16
Key Takeaways
• Although mechanical properties alone are not sufficient to predict
drop shock behavior of an alloy, they serve as a good indication of its
performance.
• High-temperature creep properties provide useful insight into thermal
fatigue performance of the alloys.
• Drop shock characteristic life of SBX02 is 160% higher than Sn-58Bi.
• There are eight times more thermal cycling failures in Sn-57.6Bi-0.4Ag
than SBX02 at 800 cycles.
• Cracks after thermal cycles are visible in mixed Sn-57.6Bi-0.4Ag/
SAC305 BGA cross sections before 200 cycles, which is much earlier than
SBX02 (above 500 cycles).
17
Chapter 3
Second Generation
Microalloying additions are very effective in improving mechanical shock and
thermal reliability of eutectic SnBi solder alloys, as shown in the previous
chapter. Even though solder pastes using eutectic alloys, such as SBX02,
provide an excellent solution for reducing energy and operational costs,
the use of low-temperature solders has remained relatively small in the
past decade. There are many reasons for this. For example, the economic
benefits of switching to a low-temperature solder paste have not provided
enough incentive to compensate for a performance that is not on par with
SAC solders. However, the current outlook for low-temperature solder pastes
is quickly changing. According to the 2017 International Electronics Manufac-
turing Initiative (iNEMI) roadmap, the use of low-temperature solder pastes
will grow from approximately 1–10% by 2021, to potentially reaching 20%
by 2027 [13]. In 2015, the iNEMI initiated the “BiSn-Based Low-Temperature
Soldering Process and Reliability Project,” which is dedicated to studying these
new low-temperature solder alloys and pastes [14].
Why can we expect to see such an accelerated rate of adopting low-temper-
ature alloys? As discussed in the first chapter, miniaturization of portable
electronics and higher package complexity, including increasingly thinner
flip chip BGAs, and multistep assembly processes are key drivers behind a
renewed interest for low-temperature solders. Recent investigations show
that assembling ultra-thin microprocessors with standard lead-free solders,
such as Sn-3Ag-0.5Cu (217–221°C melting range), results in dynamic warpage
on the package substrate and PCB [15-17]. Such defects can be mitigated and
SMT yields increased when using low-temperature solders that reflow below
200°C [18–19]. Furthermore, lower reflow temperatures may enable usage of
cheaper substrates, adding to the already significant reduction in energy and
operational costs. Besides that, some reports translate the resulting energy
savings into noteworthy reductions in carbon emissions [20].
19
As mentioned earlier, microalloying additions can improve the mechanical and
thermal reliability performance of eutectic SnBi alloys, but most available SnBi
solders do not match SAC’s drop shock performance[16, 18]. The drop shock
characteristic life of Sn-45Bi is 42% higher than that of eutectic Sn-58Bi. Further
reduction of bismuth content to 40 wt% results in another 77% increase in its
drop shock characteristic life, but 60Sn-40Bi drop shock is still 40% lower than
SAC305. As shown in the previous chapter (Figure 2.2), it is possible to increase
the elongation of SnBi alloys without degrading their mechanical strength by
decreasing the bismuth content in the alloy.
The BiSn phase diagram (Figure 1.5) from Chapter 1 shows the temperatures
at which various SnBi compositions transition from solid to liquid states and
vice versa. Its invariant temperature (i.e., eutectic point) is 138.6°C [6], which is
commonly said to correspond to an alloy with 42 wt% tin and 58 wt% bismuth.
Other SnBi alloy compositions move away from the eutectic point and have
distinct solidus and liquidus temperatures. The solidus temperature of the
SnBi alloys corresponds to the eutectic point, while the temperature at which
the alloy completely transforms into liquid rises above it (Table 3.1). Consid-
Table 3.1: Melting temperatures and liquid fraction of various alloys.
ering that solder pastes usually reflow at temperatures 25–30°C above the
alloy melting point, as per the BiSn phase diagram, Sn-40Bi would have the
minimum acceptable bismuth content for a SnBi alloy to stay within the 200°C
reflow temperature limit that enables higher yields and energy savings, as
previously described. For example, further bismuth reductions as in Sn-35Bi
would require reflow temperatures around 210°C.
Table 3.1 also shows the amount of liquid fraction during melting of assorted
SnBi alloys at various temperatures. The ability to form mixed SnBi/SAC solder
joints when reflowing at temperatures below the SAC melting point depends
on its atomic diffusion properties and the amount of SnBi liquid fraction. Since
atomic diffusion is temperature and time dependent, the formation of an
interdiffusion zone between SnBi and SAC alloys at the same reflow tempera-
20
For example, at 138°C, the eutectic Sn-58Bi completely converts from solid
to liquid. When reducing the bismuth content below the eutectic to 55 wt%,
the solder becomes completely liquidus at 144°C. At this same temperature,
further bismuth reduction to 50 wt% results in 96% liquid solder, whereas
Sn-45Bi shows a drastic reduction to 78% liquid fraction. This is certainly
another point of consideration when selecting a low-temperature solder, as
the melting behavior influences the reflow profile and their ability to form
SnBi/SAC mixed solder joints.
As shown in the previous chapter, the use of alloying additions improves

mechanical properties and drop shock resistance through a combination of
solid solution strengthening, grain refinement, precipitate hardening, and
diffusion modifiers. Table 3.2 shows the effects of additives such as silver
and indium on the melting behavior of eutectic and non-eutectic alloys.
Adding 0.4 wt% silver causes a small increase in the liquidus temperature to
142°C. However, raising it to 1 wt% does not modify the liquidus tempera-
ture further in eutectic or non-eutectic alloys. Another 1 wt% In addition into
Sn-58Bi slightly lowers the solidus and liquidus to 133 and 137°C, respectively.
* Peak @ 100°C
Table 3.2: Effect of additives on SnBi solder alloys melting temperature.
However, indium content above 3 wt% may be a concern for SnBi thermal
reliability at 100–125°C due to an undesirable reduction in its solidus tempera-
ture to 125°C and a low melting temperature peak in its differential scanning
calorimetry (DSC) curve around 100°C that indicates a presence of low melting
temperature compounds.
On the following page, Figure 3.1 shows the mechanical properties of these
alloys in terms of UTS, YS, elongation, and Young’s modulus (E). Sn-57Bi-1Ag
has higher strength than Sn-57.6Bi-0.4Ag, but lower elongation. Reducing
bismuth content from 58 to 38 wt% produces similar results, with just slightly
higher tensile strength and Young’s modulus.
21
Figure 3.1: UTS, YS, elongation, and Young’s modulus (E)
of eutectic and non-eutectic SnBi alloys.
An additional 1 wt% indium has no effect on the mechanical properties, but

Sn-58Bi-1Ag-3In has lower tensile and yield strength, and considerably lower
elongation. These results are somewhat expected as higher bismuth content in
eutectic alloys and alloying additions, such as silver, cause strengthened alloy
microstructure and reduced elongation. However, a non-eutectic solder alloy,
such as HRL1 (SnBi+2% additives), with the right mixture of alloying additions
will also have a strong combination of tensile strength, yield strength, elon-
gation, and Young’s modulus [21]. Further, HRL1 shows appropriate melting
behavior, with a melting range between 138 and 151°C and 99% conversion
into liquid solder by 144°C (Figure 3.2).
Figure 3.2: DSC curve showing HRL1 melting behavior.
SnBi solder melting behavior and microstructure affect the reflow profile in
SnBi/SAC mixed solder joints because they influence in its ability to form the
mixed solder joint. Figure 3.3 shows the formation of an HRL1/SAC305 solder
joint as observed in a reflow simulator.
22
Figure 3.3: Real-time images of a mixed HRL1/SAC305 solder joint during reflow.
The first frame shows the SAC305 ball on HRL1 solder paste at the beginning
of the heating ramp. The next frame shows that the appearance of the SAC305
ball and the HRL1 solder paste remaining the same at 137°C while the HRL1
solder paste starts melting at 139°C. The solder paste is completely molten at
150°C, which is around the HRL1 liquidus temperature, but there is a partial
collapse of the SAC305 ball by 188°C. This phenomenon is further clarified by
the cross sections of HRL1/SAC solder joints reflowed using a 90–100-sec. soak
(100–120°C), and 60–90 sec. above liquidus profile with 180, 190, and 200°C
peak reflow temperatures in Figure 3.4.
Figure 3.4: Mixed HRL1/SAC305 solder joint height at different peak reflow temperatures.
The solder joint height is higher when using a peak reflow temperature of
180°C, but there is a clear SAC305 ball collapse when the solder joint is reflowed
at 190°C. When reflowed at 200°C, the mixing of SAC305 and HRL1 can be
observed. Figure 3.5 shows what happens when reflowing an SnBi solder ball
and solder paste. The first frame shows the eutectic SnBi solder ball sitting on
the HRL1 solder paste.
Like the mixed HRL1/SAC305 solder joints shown in Figure 3.3, the appear-
ance of the ball and paste is the same as the as-soldered until 137°C, while
both the SnBi solder ball and HRL1 solder paste start melting at 139°C. HRL1
solder paste is completely molten at 142°C, whereas the eutectic SnBi solder
ball is still collapsing. Both the SnBi solder ball and the HRL1 solder paste form
23
Figure 3.5: Real-time images of SnBi/HRL1 solder joint during reflow.
a unique solder joint by 150°C. This confirms the data obtained through DSC
analysis that about 97% of HRL1 becomes liquid by 142°C. One of the most
interesting aspects of Figure 3.4 is the clear joint formed between HRL1 and
SAC305, which arises from the alloy melting behavior and microstructure.
Figure 3.6 shows an enlargement of the area between the HRL1 and SAC305
alloys.
Figure 3.6: Cross-section of mixed HRL1/SAC305 solder joint reflowed at 190°C.

There is an interdiffuse area between these two alloys (indicated by the red box
in Figure 3.6), which is favored when the homologous temperature is around
0.94. The formation of this interdiffuse area can be enhanced by thermal acti-
vation, time, and the presence of diffusion modifiers in the alloy composition.
HRL1 microalloying additions have a very positive effect on its drop shock reli-
ability. Figure 3.7 shows the drop shock performance of HRL1/SAC305 mixed
solder joint, compared to Sn-57.6Bi-0.4Ag/SAC305 and SAC305/SAC305 solder
joints formed on CTBGA84.
There is a dramatic increase in the drop shock characteristic life switching from
the eutectic Sn-57.6Bi-0.4Ag alloy to the non-eutectic HRL1 solder. Indeed,
HRL1 drop shock performance (951 drops characteristic life) is equal or better
than Sn-3Ag-0.5Cu (875 drops) [22]. The remarkable drop shock performance of
24
Figure 3.7: Drop shock performance of mixed HRL1/SAC305 solder joint using paste flux A.
HRL1/SAC305 mixed solder joints is also observed when using different paste
flux chemistry, as well as on solder joints where HRL1 is the only solder alloy
present. Figure 3.8 shows the cumulative failures from a drop shock test of
BGA84 (with SAC305 solder balls) and LGA84. The testing assemblies with only
HRL1 as solder interconnect material (land grid array, or LGA) show a drop
shock characteristic life of 803 drops, which is equal to SAC305 (783 drops).
Figure 3.8: Drop shock performance of HRL1 solder joints using paste flux B.
25
In this case, the characteristic life of the mixed HRL1/SAC305 solder joints is
slightly lower than in the previous test, but this is an expected trend since drop
shock proxy test results usually vary from 10–20%. Thus, considering the test
methodology repeatability, HRL1’s drop shock characteristic life is between
82–100% of SAC305 performance for both mixed HRL1/SAC305 and homoge-
neous HRL1 solder joints.
Interestingly, HRL1’s superior mechanical reliability is equally shown in its
ability to withstand stresses caused by thermal cycling. Figure 3.9 shows how
the shear strength of 1206 chip resistors is affected by thermal cycling from
-40°C to +125°C (10-minute dwell time).
Figure 3.9: Effect of thermal cycling on shear strength reduction of 1206 chip resistors.
The measured HRL1, eutectic SnBi, and SAC305 solder alloys initial shear forces
are very similar—11.2, 10.6, and 10.1 kgf, respectively. However, there is a clear
distinction in performance within 500 cycles between the SnBi solder alloys
and SAC305 because SnBi alloys better retain their shear strength despite
the extreme temperature exposure. By 1,000 cycles, it is already clear that
HRL1’s microstructure has a superior ability to retain shear strength despite
cyclic stresses caused by thermal cycling. At 1,500 cycles, HRL1’s reduction in
shear strength is very small and five times better than SAC305 or eutectic SnBi
solder alloys. Drop shock results (Figures 3.7 and 3.8) and results on the effect
of thermal cycling on shear strength (Figure 3.9) refer to test vehicles reflowed
at 190°C peak temperature.
26
Key Takeaways
• Bismuth content and alloying additions in SnBi solder alloys need to
be optimized to enable reflow profiles with peak temperature lower
than 200°C and usage up to 100–125°C.
• Reduction of bismuth alone does not bring drop shock performance
close enough to that of a SAC alloy. A balanced alloy composition, such
as HRL1 solder, is key for achieving superior drop shock performance.
• HRL1 drop shock performance for both mixed HRL1/SAC305 and
homogeneous HRL1 solder joints demonstrates that it can be used in
applications that require SAC305 mechanical shock reliability.
27
Chapter 4
Using the Right Chemistry
In SAC reflow process, certain components tend to warp (frowning to smiley

or vice versa). Around 175–185°C, the chips become flat with no warpage. The
expectation is that future chips could see even higher warpage. Today’s limit is
about 180–200 µ, but there are reports that the numbers could go as high as
250 µ. At lower reflow temperature (<200°C), these chips do not warp much,
but can still cause defects like NWO and HIP. Due to the miniaturization of
electronic gadgets like cellphones, laptops, and tablets, the higher probability
of using increasingly thinner chips in motherboards is expected. A proven
solution for soldering these thinner chips is low-temperature solder.
These changes in electronics assembly materials, such as solder paste, to meet

and fulfill the requirements of today’s rapidly changing technology require
major innovation to develop new chemistry platforms for low-temperature
soldering. A new chemistry platform needs innovative, versatile, and multi-
functional chemical molecules as its building blocks.
Addressing Warpage Defects Through “Right Chemistry”

Organic flux in solder paste helps to remove the protective coatings on PCBs
and make the metal surfaces active and wettable by the solder alloy. In the
SMT process, flux promotes wetting of the surfaces to be joined by controlling
the surface tension that determines the wetting process. Additionally, paste
flux provides the right rheology to balance paste printability, tack, and slump
characteristics.
A solder flux formulation may contain as many as 15 or more ingredients from

the following categories:
29
• Rosins/resins: Provide wetting and lubricity during reflow and thix-
otropy across the temperature range the paste experiences during
storage, printing, and reflow.
• Activators: Functional molecules—often organic acids—that reduce

metal oxide layers in the bonding pad and alloy powder surfaces.
• Solvents: Used to adjust viscosity, wetting, and compatibility of the

flux components.
• Other additives: A range of additives (often proprietary) are utilized to

adjust wetting, melt viscosity, residue modulus, or surface cleaning.
Often, multiple components from each category may be used. The flux must
enable the paste to have a reasonable shelf life, be printable or dispensable,
reflow at the right temperature range, and leave minimal residue. In other
words, each component of the flux must be tuned to the alloy composition
and melt profile to take full advantage of the low-temperature processing.
When developing solder paste, the rosins/resins are generally chosen based
on their softening temperature. Above its softening temperature, the rosins
will not be very tacky and the viscosity of the paste will drop significantly. To
solve one of the major warpage defects (NWO), modified rosins and resins
are used in paste flux formulations. Figure 4.1 schematically explains NWO
defect formation.
Figure 4.1: Mechanism of formation of NWO defect with

low softening temperature and low tack rosins [23].
Minimizing or eliminating NWO defects by using the right flux chemistry

means having rosins/resins that provide some tackiness to the solder paste
at peak reflow temperature. Figure 4.2 schematically explains the minimiza-
tion of an NWO defect.
When alternative softening temperature rosins/resins are used in devel-
oping solder paste, the corresponding product will have minimal chances of
exhibiting NWO defects due to their high melt viscosity and high tackiness at
elevated temperature. Solder paste is likely to firmly hold both the pad and
the component in reflow at elevated temperature during maximum compo-
nent warpage conditions. At this stage, the solder paste will stretch as the
30
Figure 4.2: Mechanism of minimization of NWO defect with
high softening temperature and high tack rosins [23].
package undergoes warpage. Paste stretching will continue until the reflow
process completes. In the cooling zone, the molten solder undergoes solidifi-
cation, forms a strong solder joint with the pad, and eliminates the formation
of NWO defects. (Figure 4.3).
Figure 4.3: Solder paste behavior at peak reflow temperature.
ICT-Compatible LTSs Through “Right Chemistry”

In-circuit tests (ICTs) are very important to meet and qualify the solder paste
for use. In an ICT, an electrical probe tests a populated PCB to check for shorts,
opens, resistance, capacitance, and other basic quantities that will show
whether the assembly was correctly fabricated or not. It may be performed
with a bed of nails type tester, specialized test equipment, or a flying probe/
fixtureless in-circuit test (FICT).
The ICT can be affected by the amount and type of residue present on the PCB
after reflow. In general, the more the residue, the more likely the ICT will detect
a failure. As the rosin/resin is the major solid content of the flux, the amount of
residue on the reflowed PCB depends on the content of the rosin/resin. If the
residue is not penetrable, the probe of the ICT cannot make contact with the
solder and may result in ultimate failure of the test. Though not much litera-
ture is available on the type of residue to achieve maximum probable or pin
testable paste, the following summary is based on the in-house experience of
achieving the best-in-class pin/probable paste.
31
Flux residue can be categorized into three types, depending on the physical
nature: hard and brittle, soft and tacky, and soft and non-tacky. Each type of
residue has its own advantages and disadvantages. Hard and brittle residues
are difficult to pass pin testability. Though soft and tacky residues initially
pass the pin test, the failure rate can rise over time due to accumulation of
residue at tip of the pin, which does not allow the pin to contact the soldered
pads. Soft and non-tacky residues might be able to comfortably pass a pin test
because the residue allows the pin to contact the solder pad by penetrating
the pin through the residue. Hard and brittle residue can result from using
an unmodified, disproportionated rosin. This type of residue can also occur
through a chemical reaction with other ingredients of the organic flux. Figure
4.4 shows the behavior of one type of residue in the ICT.
Figure 4.4: Impact of hard and brittle residue on pin testability.
When the probe tries to make a contact with the solder joint, hard and brittle
residue will not allow the probe to make contact.
Soft and tacky residue is the result of using different rosins and raw materials
as flexible polymeric materials in the flux formulation. The residue appears to
be soft and penetrable by the probe, but tacky in nature. The tackiness of the
residue can also contribute to failing the ICT (Figure 4.5).
Figure 4.5: Impact of soft and tacky residue on the ICT.
32
Figure 4.6: Impact of soft and non-tacky residue on the ICT.
When testing begins, the probe of the ICT can easily penetrate and make
contact with solder. As the test progresses, the tacky residue can stick to the
probe and the ICT probe cannot make contact due to the accumulation of
tacky residue at the tip of the probe (Figure 4.8a). This type of residue can also
result in an ICT failure due to the high tackiness of the residue.
Soft and non-tacky residue is the result of combining modified rosins with
flexible polymer molecules. Due to the hydrogenation process, the degree of
rosin crosslinking is very minimum after reflow. The best pin-probable residue
can be further achieved by employing other additives that can make the final
residue soft and non-tacky. Soft and non-tacky residues have higher ICT yields
because the residue allows the probe of the ICT to make contact after several
thousand contacts by the same probe (Figures 4.6 and 4.8b).
Figure 4.7: Pin test summary results of three experimental lab samples.
Various formulations were studied for pin probe ability by employing different
types of rosins/resins with combinations of other additives (Figure 4.7). As
previously explained, the formulations where only rosins were used showed
33
poor pin testability and the residue was found to be hard for the pin to pene-
trate. Formulations with other additives showed better pin testability because
their residue was found to be soft and non-tacky. Figures 4.7 and 4.8 show
results for these residue types.
Figure 4.8: (a) Soft and tacky residue and (b) soft and non-tacky residue.
Thermal-Mechanical Properties Enhanced by Crosslinkable Chemistry

Joint properties of low-temperature solders can be improved and enhanced
by applying a reinforcing material in the form of a crosslinkable flux. Solder
joint reinforcement of LTSs may result in better drop shock, thermal cycling/
shock, shear strength, fatigue strength during PCB flexing, and other thermal-
mechanical performance attributes. In addition, solder joint reinforcement
reduces voids, VOCs, and spatter; results in protection of the joint from the
environment; and may be compatible with other epoxy-based underfill/adhe-
sive materials.
Figure 4.9 presents a schematic view of a solder joint using an epoxy solder
paste. In this example, an electronic component with a BGA ball is joined to the
Figure 4.9: Schematic representation of a crosslinkable

epoxy collar formation around the solder joint.
34
PCB through the low-temperature solder, which sits on a copper pad. Inter-
metallic compounds form the interface between the electronic component
and the solder, and between the solder and the copper pad. The epoxy paste
surrounds the solder by forming a crosslinked epoxy collar and improving
the solder joint adhesion to the substrate upon curing, which improves
the mechanical performance attributes. A drop shock test is performed as
described in JESD22-B111.
A crosslinkable epoxy solder paste can enhance drop shock properties and
thermal cycling performance when used with low-temperature solders.
Figures 4.10 and 4.11 show improvement in drop shock and thermal cycling
properties of epoxy flux over non-epoxy flux. Drop shock test was carried out
as per the JEDEC standard with BGA 84 components.
1000
900
800
700
Number of Drops
600
500
400
300
200
100
0
Non-epoxy Flux Epoxy Flux
Figure 4.10: Comparison of drop shock property epoxy flux with non-epoxy flux.
1600
1400
1200
Number of Cycles
1000
800
600
400
200
0
Non-epoxy Flux Epoxy Flux
Figure 4.11: Comparison of thermal cycling performance of epoxy flux with non-epoxy flux.
35
Figure 4.12: Low-temperature transfer efficiency by area ratio.
LTS Transfer Efficiency and Bottom Terminal Component Void Performance

Having the appropriate solder paste volume on a PCB largely depends on
solder paste rheology. Rheology is dictated by the flux components of the
solder paste. Careful selection of paste flux chemicals plays a significant part
in determining solder paste printing and processing. Better transfer efficiency
can be achieved by having right chemistry in low-temperature soldering.
Figure 4.12 represents the transfer ability of low-temperature solder paste. It
shows that effective transfer efficiency can be achieved for area ratios of 0.5
and above with low-temperature pastes when type four powder is used with a
carefully-engineered flux vehicle.
Regulatory Considerations
All components of the paste flux are subject to regulatory guidelines, both
in the country of manufacture and in the country of use. These regulatory
requirements are constantly evolving—always in the direction of tighter limits
and heightened scrutiny. Because mandated formulation changes interrupt
the supply chain and require revalidation, regulatory experts maintain a watch
across the globe for pending changes and proactively respond to ensure that
all of our assembly products are safe and compliant.
36
Key Takeaways
• Choosing the right chemistry for low-temperature solders is important
because reflow temperatures are around 75–80°C less than the stan-
dard reflow for SAC alloys.
• Fluxes may contain 15 or more components, all of which need to be
selected and adjusted to work with the composition and melt profile of
the low-temperature alloy.
• The flux must allow the paste to have a reasonable shelf life, allow the
paste to print or dispense, facilitate the alloy to wet and flow, leave little
residue after reflow, and not diminish the reliability of the solder joint.
• A deep understanding of metallurgy and chemistry is needed to
develop low-temperature solder pastes that are optimized to deliver the
most reliable solder joint.
37
Chapter 5
Advanced Applications for

LTS Applications for Advanced Semiconductor Packaging
The rapid development of semiconductor technology and heterogeneous
integration of end product functions has driven the industry toward increas-
ingly finer transition node processes, from 10 nm down to 7 nm.
The interconnect pitch of silicon die is reduced due to transistors; however,
interconnect density has continued to shrink. In order to bridge the gap
between high density interconnect and pitch to achieve better performance,
package on package (PoP) and fan-out PoP technology provide solutions.
Recently, the system-in-package (SiP) solution is also generating more atten-
tion. By integrating multiple silicon dies of various functions onto a package, a
single package capable of delivering a wide range of application functions can
be developed.
LTS Solutions to Fan-Out/Advanced PoP Warpage Challenges
The adoption of fan-out packages is becoming mainstream, driven largely by
Apple’s adoption of the TSMC’s integrated fan-out (InFO) package [24] (Figure 5.1).
Figure 5.1: A10 processor with memory package. (Source: Prismark/Binghamton University)
39
Fan-out wafer-/panel-level package technology is getting more attention for
advanced packages because of the combined features of low profile, small
form factor, and high bandwidth with fine line redistribution layer (RDL)
routability [25]. Fan-out technology is also capable of scaling very large body
sizes with the possibility for 3D interconnection via PoP configurations, as
seen on Apple’s A10 application processor where the mobile processor is
connected with memory through a package stack format.
Another advanced PoP package is MCeP (molded core embedded package)
(Figure 5.2). (MCeP® is the registered trademark of Shinko Electric Industries
Co.) It is an advanced PoP that utilizes copper core solder balls as a standoff
to connect the top interposer layer with the bottom package. The top inter-
poser then allows for a top package, for example, a memory package, to be
connected to the bottom package.
Figure 5.2: MCeP demonstration.

As advanced packages get larger with a thinner form factor, the warpage chal-
lenges of the PoP prestack process become even more severe. The thermal
stress and warpage encounter by the package during a typical SAC alloy
reflow process will result in an NWO soldering defect, solder bridging, and
non-contact open (NCO) on the joints between the bottom package and the
PoP memory package[25]. Figure 5.3 illustrates typical solder joint failures that
can happen between a PoP package and PCB. These failures can also occur
between the top memory and bottom PoP package.
Figure 5.3: Typical defect on PoP package [26].
40
Low-temperature solder alloys, such as Alpha’s HRL1, offer a unique solu-
tion to such problems. The low melting temperature and high mechanical
reliability property of the HRL1 alloy allows the alloy to be use as the inter-
connect between the top and bottom PoP. As shown in schematic Figure 5.4,
low-temperature spheres made from alloys with improved mechanical reli-
ability can be used to form the top solder interconnect for the bottom package
during the packaging process. The solder sphere on the top PoP package, such
as a memory package, can remain a typical SAC alloy. During the PoP prestack
process, a low-temperature reflow process can be used to connect the top and
bottom PoP. The low thermal load on the packages eliminates warpage issues
faced during the high-temperature SAC reflow.
Figure 5.4: Using HRL1 spheres as the top solder interconnect on the bottom package.
In instances where the bottom PoP package cannot be packaged with the
HRL1 sphere (e.g., a fan-out package, such as TSMC’s InFO), HRL1 solder paste
can be used to connect the top memory package using a low-temperature
process (Figure 5.5).
Figure 5.5: Using HRL1 solder paste to connect the top memory package to the
bottom POP package with copper post as interconnect.
41
Figure 5.6: HRL1 solder paste is a cost-effective solution for an advanced PoP package.
In the case of advanced MCeP packaging utilizing costly copper core solder
spheres to provide standoff, low-temperature solder paste can be used to
assemble the top interposer with a standard SAC solder sphere. Because the
SAC alloy solder ball does not melt during low-temperature solder paste reflow,
the standoff can be achieved for subsequent molding processes (Figure 5.6).
Low-temperature alloys, such as HRL1, offer high yield and solder reliability
similar to the SAC305 alloy, as well as unique and cost-effective solutions to
advanced PoP packaging that are not possible with standard high thermal
processes.
LTS Solutions to System in Package Challenges
The internet of things (IoT) is driving the increase of functionality in a smaller
package. The reduction in footprint and the heterogeneous integration of
different functions gives rise to the demand for SiP. SiPs provide the easiest
solution to integrate sensors, processors, and radio frequency (RF) devices
into a small form factor. The availability of components also means faster time
to market without the need to develop a single die (i.e., a system-on-chip solu-
tion).
The increase in integration in an ever-reducing package size for wearable appli-
cations means active silicon dies have to be stacked or gaps between compo-
nents will be reduced to a point that the traditional surface mount process
becomes challenging. The reduction in pitch and gaps between components
creates potential defects when the package is subjected to multiple reflows.
The use of a higher melting-point alloy, such as tin antimony or high lead
solder paste, is common in RF and power SiP. The purpose is to prevent the
remelting of solder joints on the components during downstream processes,
42
such as the ball attach
process on the SiP
chip scale package
(CSP)/BGA package. As
shown in Figure 5.7,
solder bridging due
to delamination of
molding compounds
can happen during
multiple high-temper-
ature reflows steps.
Low-temperature solder spheres offer a great solution to prevent the remelting
of SiP component solder joints that use the standard SAC alloy. HRL1 solder
sphere is a drop-in solution that can be implemented with current ball attach
processes.
Other Advanced Applications for Low-Temperature Solder

With all the cost, safety, and environmental benefits gained by adopting low
melt point (LMP) material sets and manufacturing processes, it is expected
that the use of LMP solder pastes will grow significantly in the coming decade
(Figure 5.8). While a considerable portion of this growth will be in the assembly
market that historically has used rigid PCBs, other markets and applica-
tions have recognized the benefits of low-temperature processing and have
expanded their technology roadmaps to include the use of solders/solder
pastes with decreased liquidus temperatures.
Figure 5.8: Forecasted growth of LMP solder paste for electronics assembly applications [27].
43
Formable Electronics and Flexible Circuits
Nearly all electronic products will, and many already do, contain flexible
circuits. Flexible substrates are used instead of rigid substrates because they
weigh less, take up less space, and allow for greater flexibility in the product
design (Figure 5.9). While flexible substrates deliver many significant benefits,
those benefits come with a price. Flex circuits are more sensitive to heat and
can deform, or even decompose, if process temperatures are too high. Gener-
ally, assemblers who are considering using flexible circuits must also consider
that unique equipment and processes may also be required.
Figure 5.9: Flexible circuit application in a wearable fitness tracker.
There are many different flexible circuit substrates used in today’s electronics,
with the most popular being variations of polyester, polyimide, polycarbonate,
or polyethylene. Assemblers decide which type to use based on their unique
properties. One of the most critical properties is temperature stability. Certain
types are able to withstand higher process or operating temperatures than
others. The chosen substrate impacts the decision of which solder paste to
use because certain pastes are formulated to perform under certain process
temperatures. The solder alloy used in the paste is a critical consideration
(refer to Chapter 2, Table 2.1 on melting temperatures of known solder alloys),
as well as the paste flux, because it must maintain its properties and perform
its required function in a specific reflow profile window.
44
Alternative solder pastes and inks must also be used for formable or molded
electronics (Figure 5.10). In these applications, solder pastes and inks with
unique properties are applied to certain types of flat, rigid, and semi-rigid
polymer sheets. They are then heated and formed under pressure into 3D
shapes designed to become part of the electronic product itself. Thus, the
body of the product is used as the substrate where a part of the electrical
system operates, much like a traditional circuit board. Solder pastes and inks
used in these applications must maintain electrical pathways even after being
reformed. As with flexible circuits, formable electronic substrates normally
require processing temperatures much lower than traditional printed circuit
assemblies, so the joining materials must have lower melting temperatures.
Figure 5.10: Example of a more conventional assembly (left)

and a formable electronics end product (right).
45
Membrane Touch Switches
Many electronic products today use membrane touch switch (MTS) tech-
nology at the user interface (Figures 5.11 and 5.12). MTS technology uses a
variety of polymer materials to allow the product to be stylish, functional,
and lightweight. Transitioning to MTS technology normally eliminates the use
of mechanical buttons and switches, rigid PCBs, and the process conditions
needed to assemble them. Because new MTS materials are temperature sensi-
tive, lower melt point solder pastes enable this transition while not sacrificing
the mechanical reliability expected of the device being produced. MTS tech-
nology is used, or will be used in the future, by nearly every major electronics
market, including automotive, white goods, computers, mobile devices, LEDs,
medical equipment, and even aerospace.
Figure 5.11: Membrane touch switch (MTS) technology.
Figure 5.12: MTS technology in a washing machine control panel.
46
Photovoltaics
The majority of solar modules produced in the world use cells made predomi-
nantly of crystalline silicon (cSi) to produce power (Figure 5.13). These cells are
assembled in strings, placed in an array, and then joined together to create a
circuit that generates power. The cells are connected using various methods—
most use some type of solder-coated copper ribbons or other connector parts
joined together using solder paste.
There are two major shifts occuring in the photovoltaic (PV) module industry
that will impact the materials used in assembly: cSi solar cells are getting
thinner and the industry will need to transition from using tin-lead to lead-free
solders in the coming years.
Figure 5.13: PV solar modules in an array.
Most solar modules use cSi cells in the range of 180 µm. As the push for lower
solar energy costs continues, cell thickness is getting smaller (Figure 5.14).
However, cSi cells are very delicate and can crack easily. Cracks can result from
improper handling, but can also occur during assembly as the ribbons and
other parts used to join the cells together can have a CTE that is 4–5 times
greater than the cSi itself. This puts stress on the delicate cells as the solder
solidifies after processing. As cells get thinner, they become even more sensi-
tive to cracking. This is where LMP solder alloys and solder pastes can help. By
lowering the temperatures required to assemble the cell strings and arrays,
the risk of cells cracking during the soldering step is reduced.
PV modules are not specifically covered by the European Union’s RoHS
Directive that banned the use of lead in soldering materials in 2006. Future
ammendments of RoHS are expected to include PV modules. While not specifi-
cally covered by RoHS, the disposal of solar modules containing lead is covered
47
Figure 5.14: Forecasted reduction in cSi cell thickness [28].
by a variety of state- and/or country-specific recycling and “take-back” regula-
tions. Many companies have already eliminated the use of lead, and many
more are in the process. The majority of the low melt point alloys and solder
pastes developed in recent years are lead-free, thus enabling this important
environmental transition.
With the demonstrated mechanical reliability and process-
ability of solders and solder pastes using low melt point
alloys, the rapid transition and adoption of these materials
by a wide variety of industries and applications is inevitable.
With ranges in melt point from mid-range (160–210°C) to
very low temperatures (<140°C), these solder alloys allow
electronics manufacturers the flexibility to choose the
substrates they use and consider new designs like they never have before.
Summary
Low-temperature alloys offer a unique processing approach to solve advanced
semiconductor packaging challenges. The use of low-temperature processes
not only addresses the issue of thermal induced warpages, but also offers cost
efficiency. The benefits of implementing a low-temperature process may even
extend beyond what was addressed in this chapter. The use of low cost mate-
rials, such as low-Tg substrates and molding compounds, can be explored
since high thermal processes are reduced. Low-temperature alloys such as
HRL1 can revolutionize advanced semiconductor packaging processes with
combined low melting temperature and high mechanical reliability. Moreover,
LTSs offer a variety of opportunities in various electronics markets through
use of formable electronics, flexible circuits, membrane touch switches, and
photovoltaics.
48
Conclusion
Electronics assembly fundamentally requires the use of solder to

establish the electrical and mechanical connection between the
components and PCB. A variety of factors—including legislative
changes, design challenges, and cost considerations—have created
opportunities for the alloys used to create these connections to evolve
over time. Through a series of systematic advances in alloy proper-
ties and chemistry platforms, we now find the electronics industry
poised to implement assembly solutions that take advantage of lower
temperature materials and processes. Low melting point solders have
the potential to be a cost-efficient way to establish strong and reliable
solder joints and enable design engineers to overcome limitations
that are created by traditional SAC alloys. Low-temperature soldering
in SMT applications can also reduce operational costs because they
reduce the need for additional materials, labor, and energy. Low-
temperature soldering will continue to evolve and be an important
part of PCB manufacturing for years to come.
49
Glossary
Ball Grid Array (BGA): A type of surface-mount packaging (chip carrier) used
for integrated circuits. BGA packages are used to permanently mount devices,
such as microprocessors. A BGA can provide more interconnection pins than
can be put on a dual inline or flat package.
Coefficient of Thermal Expansion (CTE): How the size of an object changes
with a change in temperature. Specifically, it measures the fractional change in
size per degree change in temperature at a constant pressure.
Creep: The tendency of a solid material to move slowly or deform perma-
nently under the influence of mechanical stresses. It can occur as a result
of long-term exposure to high levels of stress that are still below the yield
strength of the material.
Crystalline Silicon (cSi): The dominant semiconducting material used in
photovoltaic technology for the production of solar cells. These cells are
assembled into solar panels as part of a photovoltaic system to generate solar
power from sunlight.
CTE Mismatch: Differences in the CTE between two joined materials. As
temperature varies (e.g., during thermal cycling test), soldered materials
with different CTE will expand at different rates, which causes strain in the
assembly. The thermal expansion of one layer causes traction stresses in adja-
cent layers and compression stresses within itself (or vice versa). This resulting
mechanical strain is often called CTE mismatch.
Drop Shock Performance: The ability of a solder material to absorb and
recover from a certain stress/strain condition exerted during a standardized
drop test.
Elastic Deformation: A change in shape of a material at low stress that is
recoverable after the stress is removed.
Elastic Modulus: The ratio of the force exerted upon a substance or body to
the resultant deformation.
Eutectic: Relating to or denoting a mixture of substances in fixed proportions
that melts and solidifies at a single temperature that is lower than the melting
points of the separate constituents or of any other mixture of them.
Fan-Out Wafer-Level Packaging (FOWLP): FOWLP technology is an enhance-
ment of standard wafer-level packages (WLPs), developed to provide a solution
for semiconductor devices requiring a higher integration level and a greater
number of external contacts.
50
Flexural Strength: Also known as a modulus of rupture or bend strength.
The stress in a material just before it yields in a flexure test. Flexural strength
represents the highest stress experienced within the material at its moment
of yield.
Fracture Strength: The stress at which a specimen fails via fracture. This is
usually determined for a given specimen by a tensile test, which charts the
stress–strain curve. The final recorded point is the fracture strength.
Head-In-Pillow (HIP) Defect: In the assembly of integrated circuit packages
to PCBs, a HIP defect is a failure of the soldering process. The defect can be
caused by surface oxidation, poor wetting of the solder, or distortion of the
integrated circuit package or circuit board by the heat of the soldering process
in which solidifying the solder ball and solder paste do not coalesce in one
single joint. The defect gets its name from the failure analysis where a “head”
(i.e., a BGA sphere) appears to be resting on a “pillow” (i.e., the reflowed solder
paste deposit that remains on the PCB).
Heterogeneous: Denotes a process involving substances in different phases
(solid, liquid, or gaseous).
Homologous Temperature: Homologous temperature expresses the temp-
erature of a material as a fraction of its melting point temperature using the
Kelvin scale.
In-Circuit Test (ICT): An example of white box testing where an electrical
probe tests a populated PCB to check for shorts, opens, resistance, capaci-
tance, and other basic quantities that will show whether the assembly was
correctly fabricated or not.
Liquidus Temperature: The temperature at which a solid changes into a
liquid. For pure substances, the melting or fusion process occurs at a single
temperature. For mixtures of two or more components, the melting process
normally occurs over a range of temperatures.
Mechanical Reliability: The probability that an item or unit operate properly
within specified limits in a given time when operated correctly in a specific
environment.
Membrane Touch Switch (MTS): A momentary electrical on/off switch for
activating and deactivating a circuit.
51
Non-Wet Open (NWO): The NWO defect occurs when the solder sphere and
solder paste on the BGA have no physical contact with the pad after reflow, yet
there was paste on the pad prior to the board entering the oven. The defect is
identified by the presence of the non-wetted pad after reflow.
Package on Package (PoP): An integrated circuit packaging method that verti-
cally combines discrete logic and memory BGA packages. Two or more pack-
ages are installed atop each other (i.e. stacked) with a standard interface to
route signals between them.
Reflow: A process in which the solder paste is heated to the point where it
melts, and wetting, wicking, and surface tension allow the solder to flow—
thereby forming a soldered connection between the component lead and the
printed wiring board’s pad (land).
SAC Alloy: Tin-silver-copper (SnAgCu, also known as SAC) is a lead-free alloy
commonly used for electronic solder. The SAC alloy has been the prevailing
alloy system used to replace tin-lead because it is near eutectic and has
adequate thermal fatigue properties, strength, and wettability.
Semiconductor Package: A metal, plastic, glass, or ceramic casing containing
one or more semiconductor electronic components. Individual discrete
components are typically etched in silicon wafer before being cut and assem-
bled in a package.
Shear Strength: The strength of a material or component against the type of
yield or structural failure where the material or component fails in shear. A
shear load is a force that tends to produce a sliding failure on a material along
a plane that is parallel to the direction of the force.
Solidus Temperature: The locus of temperatures (a curve on a phase diagram)
below which a given substance is completely solid (crystallized).
Tensile Strength: The resistance of a material to breaking under tension.
Thermal Cycling: The alternate heating and cooling of a material. A low
frequency thermal cycle is where the time taken for completion of the cycle is
large enough to cool the component.
Thermal Fatigue Resistance: The ability of a material to resist cracking or
other damaging deformations during sudden or repeated gradual tempera-
ture change. Thermal fatigue occurs when a thermal gradient causes different
parts of an object to expand by different amounts. This differential expansion
can be understood in terms of stress or strain. At some point, this stress over-
comes the strength of the material, which causes a crack to form. If nothing
stops this crack from propagating through the material, it will cause the
object's structure to fail.
52
Transistors: A semiconductor device with three connections capable of ampli-
fication and rectification.
Volatile Organic Compounds (VOC): Any compound of carbon—excluding
carbon monoxide, carbon dioxide, carbonic acid, metallic carbides or carbon-
ates, and ammonium carbonate—that participates in atmospheric photo-
chemical reactions.
Wafer-Level Packaging (WLP): The technology of packaging an integrated
circuit while still part of the wafer, in contrast to the more conventional method
of slicing the wafer into individual circuits (die) and then packaging them.
Warpage: Dimensional distortion of components or PCBs after the reflow
process.
Yield Point: The stress beyond which a material becomes plastic.
Yield Strength: In materials that do not exhibit a well-defined yield point, the
stress at which a specific amount of plastic deformation is produced—usually
taken as 0.2% of the unstressed length.
53
References
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31 (2), p. 205. Image reprinted with permission.
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1994, pp. 30–34.
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Pb-Free Electronic Solder Applications.” Journal of Materials Science: Materials Elec-
tronics, 18, pp. 55–76.
4. National Center for Manufacturing Sciences. “Lead-Free Solder Project Final

Report.” Report 0401RE96, May 1997.
5. Mei, Zequn, Holder, Helen A., and Vander Plas, Hubert A. “Low-Temperature
Solders.” Hewlett-Packard Journal, Article 10, August 1996, pp. 1–10.
6. Braga, M. H., Vizdal, J., Kroupa, A., Ferreira, J., Soares, D., and Malheiros, L.F.,
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Coupling of Phase Diagrams and Thermochemistry, 31, pp. 468–478.
7. Ribas, M., Chegudi, S., Kumar, A., Pandher, R., Raut, R., Mukherjee, S., Sarkar,
S., and Singh, B. “Development of Low-Temperature Drop Shock Resistant Solder
Alloys for Handheld Devices.” IEEE 15th Electronics Packaging Technology Confer-
ence. Singapore. December 2013, pp. 53–57.
8. Glazer, J., 1994. “Microstructure and Mechanical Properties of Pb-Free Solder

Alloys for Low-Cost Electronic Assembly: A Review.” Journal of Electronic Materials, 23
(8), pp. 693–700.
9. Goldstein, F. J. L., and Morris, J.W., Jr., 1994. “Microstructural Development of

Eutectic Bi-Sn and Eutectic In-Sn During High Temperature Deformation.” Journal of
Electronic Materials, 23 (5), pp. 477–486.
10. McCormack, M., Chen, H. S., Kammlott, G. W., and Jin, S., 1997. “Significantly
Improved Mechanical Properties of Bi-Sn Solder Alloys by Ag-Doping.” Journal of
Electronic Materials, 26 (8), pp. 954–958.
11. Ribas, M., Chegudi, S., Kumar, A., Pandher, R., Raut, R., Mukherjee, S., Sarkar, S.,
and Singh, B. “Low-temperature Alloy Development for Electronics Assembly.” IPC
APEX EXPO, San Diego, California. February 2013.
12. Ribas, Chegudi, S., Kumar, A., Pandher, R., Raut, R., Mukherjee, S., Sarkar, S., and
Singh, B. “Comprehensive Report on Low-temperature Solder Alloys for Portable
Electronics.” SMTA International Conference and Exhibition. Rosemont, Illinois.
September 2015, pp. 176–183.
13. Board Assembly Chapter, 2017. "iNEMI Roadmap."
14. Fu, H., Aspandiar, R., Chen, J., Cheng, S., Chen, Q., Coyle, R., Feng, S., Krmpotich,
M., Lasky, R., Mokler, S., Radhakrishnan, J., Ribas, M., Sandy-Smith, B., Tang, K. K.,
Wu, G., Zhang, A., and Zhen, W. “iNEMI Project on Process Development of BiSn-
Based Low Temperature Solder Pastes.” SMTA International Conference and Exhibi-
tion. Rosemont, Illinois. September 2017
54
15. Aspandiar, R., Byrd, K., Tang, K. K., Campbell, L., and Mokler, S. “Investigation of
Low-temperature Solders to Reduce Reflow Temperature, Improve SMT Yields and
Realize Energy Savings.” IPC APEX EXPO, San Diego, California. February 2015.
16. Chen, O. H., Byrd, K., Mokler, S., Tang, K. K., and Aspandiar, R. “Comparison of the
Mechanical Shock/Drop Reliability of Flip Chip BGA (FCBGA) Solder Joints Formed by
Soldering with Low-temperature BiSn-Based Resin Reinforced Solder Pastes.” Inter-
national Conference on Soldering and Reliability. Markham, Ontario. May 2015.
17. Chen, O. H., Molina, A., Aspandiar, R., Byrd, K., Mokler, S., and Tang, K. K.
“Mechanical Shock and Drop Reliability Evaluation of the BGA Solder Joint Stack-Ups
Formed by Reflow Soldering SAC Solder Balls BGAs with BiSnAg and Resin Rein-
forced BiSn-Based Solder Pastes.” SMTA International Conference and Exhibition.
Rosemont, Illinois. September 2015.
18. Holtzer, M., and Mok, T. W. “Eliminating Wave Soldering with Low Melting Point
Solder Paste.” SMTA International Conference and Exhibition, Fort Worth, Texas.
October 2013.
19. Mokler, S., Aspandiar, R., Byrd, K., Chen, O., Walwadkar, S., Tang, K. K., Renavikar,
M., and Sane, S. “The Application of Bi-Based Solders for Low-temperature Reflow
to Reduce Cost While Improving SMT Yields in Client Computing Systems.” SMTA
International Conference and Exhibition, Rosemont, Illinois. September 2016.
20. Lenovo Newsroom, (2017). "Lenovo™ Announces Breakthrough, Innovative PC

Manufacturing Process".
21. Ribas, M., Kumar, A., Kosuri, D., Rangaraju, R. R., Choudhury, P., Telu, S., and
Sarkar, S. “Low-temperature Soldering Using Sn-Bi Alloys.” SMTA International
Conference and Exhibition. Rosemont, Illinois. September 2017.
22. Ribas, M. “Advancements in Low-temperature Soldering.” SMT Today, September

2017, pp. 36–38.
23. Sidhu, R. S., Renavikar, M. P., Dani, A. A., and Dudek, M. A., 2014. “Solder Paste
material technology for elimination of high warpage surface mount assembly
defects.” U.S. Patent, 0175160 A1.
24. Tseng, C. F., Liu, C. S., Wu, C. H., and Yu, D. “InFO (Wafer Level Integrated Fan-Out)
Technology.” 66th Electronic Components and Technology Conference (ECTC). Las
Vegas, Nevada. IEEE Press, June 2016, pp. 1–6.
25. Lau, J. H. “Patent Issues of Fan-Out Wafer/Panel-Level Packaging.” Chip Scale

Review, 19, November/December 2015, pp. 42–46.
26. Loh, W. H., Fu, H. “Package-on-Package Warpage Characteristics and Require-

ments.” SMT Magazine, July 2016, pp. 68–76.
27. Fu, H. “iNEMI Collaborative Effort on Low-temperature Soldering.” 2nd Genera-

tion Lead Free Alloys Technology Seminar, September 2017.
28. International Technology Roadmap for Photovoltaic (ITRPV), 8th Edition, September
2017.
55
About Alpha Assembly Solutions
Alpha Assembly Solutions, part of the MacDermid Performance
Solutions group of businesses, is the world leader in the develop-
ment, manufacturing, and sales of innovative specialty materials
used for electronics assembly, die attach, and semiconductor
packaging in a wide range of industry segments, including auto-
motive, communications, computers, consumer, power elec-
tronics, LED lighting, photovoltaics, and others.
For over a century, electronics manufacturers have relied on
Alpha for tailor-made materials and solutions that meet and
exceed specifications for quality, efficiency, effectiveness, and
cost. Our mission as a company is to always uphold a standard
of excellence.
As the electronics industry continues to evolve, Alpha is focused
on developing novel and unique processes for solving assembly
challenges. Whether traditional electronics assembly, die attach,
or emerging applications, such as flexible circuits and formable
electronics, Alpha designs manufacturing solutions that look at
how multiple products can interact in the same environment to
provide customers with the most effective assembly solution for
their application.
Research and Development

Alpha’s international state-of-the-art R&D facilities are home to
some of the most talented engineers, metallurgists, and chemists
in the industry. Their collective depth and breadth in problem-
solving is unmatched by any other assembly materials manu-
facturer. This team of scientists takes a pioneering approach to
process technology and assembly materials. As a leading solu-
tions provider in the industry, Alpha’s expert engineering team
continually looks forward to anticipating and addressing elec-
tronics manufacturing challenges and concerns.
56
Service and Support
A unique advantage to partnering with Alpha is the exceptional
customer technical support (CTS) team that you gain access
to. Our seasoned CTS engineers work as an extension of our
customers’ existing staff to ensure assembly operations are opti-
mized to produce high-performing, reliable products while mini-
mizing time-to-market. Many of Alpha’s CTS engineers utilize Six
Sigma techniques and principles to achieve this and are black-
belt certified through Alpha’s Six Sigma program.
Alpha Advanced Materials

Alpha Advanced Materials (AAM) is a business unit within Alpha
Assembly Solutions that is completely focused on the needs of
the semiconductor packaging industry. AAM is a leading supplier
of innovative, high-performance materials tailored to the needs
of the leading semiconductor packaging manufacturers and
delivered with knowledgeable applications expertise.
MacDermid Enthone Electronics Solutions

Both Alpha and MacDermid Enthone are leaders in the develop-
ment, characterization, and commercialization of materials for
electronics assembly and plating. Each business has its unique
areas of expertise and resources that focus on creating new
chemistries and applications knowledge to help enable new
assembly processes at their customers.
Connected by Design
Together, both Alpha and MacDermid Enthone continue to
provide the electronics industry best-in-class materials and
services to provide solutions for the next generation of elec-
tronics assembly. Their combined know-how and years of expe-
rience can be leveraged to help many customers throughout the
electronics assembly supply chain.
For more information, visit AlphaAssembly.com.
57

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Low-Temperature Soldering

Morgana Ribas, et al.

ALPHA ASSEMBLY SOLUTIONS

© 2018 BR Publishing, Inc.

Traian Cucu, Ph.D.

56 About Alpha Assembly Solutions

Table 1.1 provides examples of solidus/liquidus temperatures for common

Figure 1.5: BiSn phase diagram [1].

History and Overview of

Table 2.1: Melting temperatures of known solder alloys.

(a) (b) (c)

Figure 2.5: Drop shock performance of eutectic SnBi solders.

Table 2.2: Creep behavior at 85°C and 150 N load.

by measuring discontinuities in electrical resistance or passively monitored by

Figure 2.9: Effect of thermal cycling on shear strength.

Table 3.1: Melting temperatures and liquid fraction of various alloys.

As shown in the previous chapter, the use of alloying additions improves

An additional 1 wt% indium has no effect on the mechanical properties, but

Figure 3.2: DSC curve showing HRL1 melting behavior.

Figure 3.6: Cross-section of mixed HRL1/SAC305 solder joint reflowed at 190°C.

Using the Right Chemistry

In SAC reflow process, certain components tend to warp (frowning to smiley

These changes in electronics assembly materials, such as solder paste, to meet

Addressing Warpage Defects Through “Right Chemistry”

A solder flux formulation may contain as many as 15 or more ingredients from

• Activators: Functional molecules—often organic acids—that reduce

• Solvents: Used to adjust viscosity, wetting, and compatibility of the

• Other additives: A range of additives (often proprietary) are utilized to

Figure 4.1: Mechanism of formation of NWO defect with

Minimizing or eliminating NWO defects by using the right flux chemistry

Figure 4.3: Solder paste behavior at peak reflow temperature.

ICT-Compatible LTSs Through “Right Chemistry”

Figure 4.4: Impact of hard and brittle residue on pin testability.

Figure 4.5: Impact of soft and tacky residue on the ICT.

Thermal-Mechanical Properties Enhanced by Crosslinkable Chemistry

Figure 4.9: Schematic representation of a crosslinkable

LTS Transfer Efficiency and Bottom Terminal Component Void Performance

Advanced Applications for

Figure 5.2: MCeP demonstration.

Figure 5.3: Typical defect on PoP package [26].

Other Advanced Applications for Low-Temperature Solder

Figure 5.9: Flexible circuit application in a wearable fitness tracker.

Figure 5.10: Example of a more conventional assembly (left)

Figure 5.11: Membrane touch switch (MTS) technology.

Figure 5.12: MTS technology in a washing machine control panel.

Figure 5.13: PV solar modules in an array.

Electronics assembly fundamentally requires the use of solder to

3. Anderson, I. E., 2007. “Development of Sn-Ag-Cu and Sn-Ag-Cu-X Alloys for

4. National Center for Manufacturing Sciences. “Lead-Free Solder Project Final

8. Glazer, J., 1994. “Microstructure and Mechanical Properties of Pb-Free Solder

9. Goldstein, F. J. L., and Morris, J.W., Jr., 1994. “Microstructural Development of

13. Board Assembly Chapter, 2017. "iNEMI Roadmap."

20. Lenovo Newsroom, (2017). "Lenovo™ Announces Breakthrough, Innovative PC

22. Ribas, M. “Advancements in Low-temperature Soldering.” SMT Today, September

25. Lau, J. H. “Patent Issues of Fan-Out Wafer/Panel-Level Packaging.” Chip Scale

26. Loh, W. H., Fu, H. “Package-on-Package Warpage Characteristics and Require-

27. Fu, H. “iNEMI Collaborative Effort on Low-temperature Soldering.” 2nd Genera-

Research and Development

Alpha Advanced Materials

MacDermid Enthone Electronics Solutions

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