Cortex-M Processors Overview

© 2022 Arm Course 1 Cortex-M Processors Overview

Agenda
Introduction
Armv6-M Cortex processors
Armv7-M Cortex processors
Armv8-M Cortex processors
Processor selection

2 2088 rev 00000 Cortex-M Processors Overview

Learning objectives - Introduction
After completing this overview, you will be able to:
• Describe the main features of Cortex-M processors

• Discuss criteria for selecting the Cortex-M processor best suited to your need

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Arm Architecture Profiles

Cortex-A Cortex-R Cortex-M SecurCore

Highest performance Faster responsiveness Smallest/lowest power Tamper resistant
Designed for high-level Designed for high Designed for discrete Designed for physical
operating systems performance, hard real- processing and security
time applications microcontrollers

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Arm Cortex-M processor portfolio
Cortex-M7
Maximum High
performance, performance
control and
DSP TrustZone
Cortex-M3 Cortex-M4 Cortex-M33 Cortex-M35P Cortex-M55
Flexibility, Tamper Performance
Mainstream Balanced
Performance resistance,
control and control and
flexibility, control
performance and efficiency
efficiency DSP efficiency for ML
DSP and DSP

Cortex-M0 Cortex-M0+ Cortex-M23

Lowest
Lowest cost, Highest energy Smallest area, power & area
low power efficiency lowest power

Armv6-M Armv7-M Armv8-M

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Agenda
Introduction
Armv6-M Cortex processors
Armv7-M Cortex processors
Armv8-M Cortex processors
Processor selection

6 2088 rev 00000 Cortex-M Processors Overview

Arm Cortex-M0 processor

Armv6-M architecture
Debug
Thumb® technology
Nested Vector Interrupt Controller (NVIC)
WIC Interface
Interrupts &

Breakpoint
and
Watchpoint Optional CoreSight™-compliant debug

Debug
Cortex-M0 Unit
NVIC
Core Von-Neumann architecture
Debugger
Interface 3-stage core pipeline
Clock/Reset

AMBA®AHB-Lite Master Interface

Configuration
Ultra-low power support

/Status
Bus
Matrix
Synthesizable - configurable RTL
Gate count 12 ~ 25K
AHB-Lite
Master
Interface

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Arm Cortex-M0+ processor
Armv6-M architecture
Thumb technology
Execution Trace
Interface Nested Vector Interrupt Controller (NVIC)
Debug
Optional CoreSight™-compliant debug
WIC Interface

Optional user/privileged support

Interrupts &

Breakpoint
Cortex-M0+ and
Core Watchpoint
Optional MPU

Debug
Unit
NVIC
Von-Neumann architecture
Debugger
MPU Interface 2-stage core pipeline
Clock/Reset

AMBA AHB-Lite master interface

Configuration
Optional Micro Trace Buffer (MTB)

/Status
Bus
Matrix
Optional single cycle IO Port
Optional halfword instruction fetch
AHB-Lite Low Latency
Master
Interface
IO Port Ultra-low power support
Synthesizable - configurable RTL
8 2088 rev 00000 Cortex-M Processors Overview
Agenda
Introduction
Armv6-M Cortex processors
Armv7-M Cortex processors
Armv8-M Cortex processors
Processor selection

9 2088 rev 00000 Cortex-M Processors Overview

Arm Cortex-M3/M4 processor
(Up to 5 pins)
Trace Port
Armv7-M Architecture External DAP ETM TPIU
Harvard Architecture Debugger JTAG/SWD Instruction Trace Trace Port
Serial-Wire
Configurable Blocks Viewer
External ITM (1-pin)
• Cortex-M3/M4 Core N Cortex-M3/
Interrupts V Instrumentation
Cortex-M4(+FPU) Trace
– Optional FPU on M4 W I Core
• NVIC I C
I D
C
– Interrupts : 1 - 240 DWT
MPU Watchpoints
– Priority bits : 3 – 8 and Trace

Optional Blocks FPB

Debug and Trace
Subsystem
• Debug and Trace Subsystem
• Wakeup Interrupt Controller
Bus Matrix
• Memory Protection Unit
Code Buses System Bus
Configurable Features Flash/Code SRAM Stack SRAM Peripherals

• Sleep modes, Endianness,

Bit-Banding, and more ...
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Differences between Cortex-M3 and Cortex-M4
Cortex-M3 and Cortex-M4 processors are derived from same database

Improvements and new features that make them different

Feature Cortex-M3 Cortex-M4

Armv7-M architecture variant Base Extended

(Armv7-M) (Armv7E-M)
SIMD & DSP instructions supported NO YES
Supports optional FPv4-SP extension NO YES
No of cycles for multiplication operation 1-7 1
Support for fault-robust interface Present Absent
Bundle Example System Integration Kit

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 Arm Cortex-M7 processor
ITCM D0TCM D1TCM

Synthesizable - configurable RTL

TCU SQ
64-bit AXI bus interface
L1 Tightly Coupled Memory (TCM)
MPU AHBS DMA
L1 Caches
Interrupts NVIC DBG AHBD Dedicated peripheral and DMA ports
Support for safety/reliability-critical
DPU applications (including ASIL-D)
PFU LSU AHBP
FPU
Double precision support
ETM data trace
STB

I$ & D$ & ATB trace

Controller BIU Controller ETM Interface

Cortex-M7 EPPB

L2 AXI
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Agenda
Introduction
Armv6-M Cortex processors
Armv7-M Cortex processors
Armv8-M Cortex processors
Processor selection

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 Arm Cortex-M23 Processor
MTB
AHB Baseline profile of Armv8-M
Cortex-M23
- MCU level Synthesizable - configurable RTL
Cortex-M23
- Processor level
MTB SRAM
In-order 2 stage pipeline
interface
MTB Optional Security Extension
Nested
CTI
PMSAv8 memory system architecture
IRQ and Vectored
power control
interface
Interrupt
Controller
Core

ETM ETM ATB

MPU supporting up to 16 regions
(NVIC)
Intf Trace
Secure
Attribution
TPIU
Port SAU supporting up to 8 regions
interface Memory

Breakpoint
Protection Data
Watchpoint
NVIC supporting up to 240 interrupts
SAU
(BPU ) and Trace
MPU MPU
(DWT) Hardware Multiplier (Fast/Small)
Hardware Divider (Fast/Small)
WIC

JTAG or
DAP Matrix
AMBA5 AHB Master Interface
SW Slave -AHB
interface
Optional single cycle IO Port
Optional halfword instruction fetch
Processor MCU
ROM table ROM table CoreSight-compliant Debug & Trace
Ultra-low Power Support
IO Port AHB - APB with separate power domains
Master

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Arm Cortex-M33 Processor
MTB
M -AHB Mainline profile of Armv8-M
Cortex-M33 MCU level
Cortex-M33 processor level Synthesizable - configurable RTL
Floating Point
MTB MTB SRAM
Coprocessor
Unit (FPU)
interface In-order 2/3 stage pipeline
interface

IRQ and
Nested
Vectored
CTI
Optional Security Extension
power control Interrupt Core
interface Controller
(NVIC) ETM Optional Floating-point Extension (FPv5)
External secure
attribution
interface Memory
ETM ATB
Optional DSP Extension
Data Interface
Protection
Breakpoint
( BPU )
SAU
Watchpoint
and Trace
PMSAv8 memory system architecture
(DWT)
MPU MPU TPIU Trace
MPU supporting up to 16 regions
WIC SAU supporting up to 8 regions
Instrumentation
JTAG or
SW
DAP
D -AHB
interface
Bus Matrix Trace Macrocell
(ITM) ITM ATB NVIC supporting up to 480 interrupts
interface

PPB bus
AMBA5 AHB Master Interface
Processor CoreSight-compliant Debug & Trace
ROM table

Ultra-low Power Support with separate power

domains
MCU
ROM table
External coprocessor support
C -AHB S -AHB E PPB APB
interface interface interface

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 Arm Cortex-M55 Processor
EWIC IWIC IDAU TCM
interface interface interface interface
Synthesizable - configurable RTL
From ITCM D0 D1 D2 D3 TCM
MCU level Mainline profile of Armv8.1-M with DSP Extension
EPPB
In-order 3/4 stage pipeline
Processor level
EWIC IWIC AHB5 S-AHB
Optional Security Extension
TCU slave interface
Optional Floating-point Extension (FPv5)
AHB5 P-AHB
IRQ
interface NVIC MAU Internal
peripheral From
master interface
Optional M-profile Vector Extension (MVE)
registers ITM
Core PMSAv8 memory system architecture
IFU

JTAG or D-AHB
DAP ROM
SW interface PPB
table
DPU LSU
BPU
MPU supporting up to 16 regions
ITM

Trace
DWT CTI TPIU interface

Coprocessor
Coprocessor
SAU supporting up to 8 regions
interface EPU ETM RAM
ETB interface NVIC supporting up to 480 interrupts
Clock and
Reset ICU DCU STB
ROM
Tightly Coupled Memory (TCM)
EPPB
table
To TCU EPPB
64-bit AMBA AXI5 bus interface
& I/DCU interface
I-Cache D-Cache
Power
control RAM RAM Separate instruction and data L1 caches
BIU MIU
MBIST
interface 32-bit AMBA5 AHB Master Interface
CoreSight-compliant Debug & Trace
AXI5
master
Performance Monitoring Unit (PMU)
Ultra-low Power Support with separate power domains
M-AXI
interface External coprocessor support
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Agenda
Introduction
Armv6-M Cortex processors
Armv7-M Cortex processors
Armv8-M Cortex processors
Processor selection

17 2088 rev 00000 Cortex-M Processors Overview

Security grouping
Cortex-M0
Cortex-M0+
Cortex-M3
Cortex-M4
Cortex-M7

Tamper resistant TrustZone

for Armv8-M
SecurCore
SC000 Cortex-M23
Cortex-M35P
SecurCore Cortex-M33
SC300
Cortex-M55

18 2088 rev 00000 Cortex-M Processors Overview

Cortex-M selection considerations Cortex-M55
• 4.2 CoreMark
• TCM, AXI, Cache
• CoreMark and Dhrystone (per MHz) • Optimized for ML &
• Results depends on C compiler used Cortex-M7
• 5.01 CoreMark signal processing
• Might not be a good indication of the performance for your
• TCM
real world applications
• AXI
Cortex-M33 • Cache Cortex-M35P
• Tamper resistance
• TrustZone • TrustZone
Actual performance depends on
• HW stack protection • HW stack protection
• System-level design
Cortex-M23 • Co-processor • Co-processor
• Memory wait states
• TrustZone
• Clock configurations, etc
• HW stack protection

Cortex-M0+ can be faster for simple Cortex-M3/Cortex-M4 is high performance

I/O control tasks because of • Richer instruction set
• Shorter pipeline • Harvard bus architecture
• Single cycle I/O interface • Write buffer
• Speculative fetch of branch targets

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