Silica MCU Summit Italy Freescale Kinetis L Series

TM
June 2012
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, t
he Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony
are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack,
ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a Package, Processor Expert, QorIQ
Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore
of Freescale Semiconductor, Inc. All other product or service names are the property and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a
of their respective owners. © 2011 Freescale Semiconductor, Inc. TM 1 Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc.
All other product or service names are the property of their respective owners. © 2011 Freescale Semiconductor, Inc.
Kinetis X Series
32-bit ARM Cortex-M4 ARM Cortex-M4
200MHz, 0-4MB, advanced
performance, memory and
feature integration
Kinetis K Series
Performance
ARM Cortex-M4
50-150MHz, 32kB-1MB,
32-256pin, low power,
mixed-signal, EEPROM,
connectivity, HMI & security
Kinetis L Series
ARM Cortex-M0+
32-bit ARM Cortex-M0+
48MHz, 8-256kB, 24-100pin,
ultra-low power, mixed-
signal, connectivity & HMI,
compatible with K Series
Feature Integration
Leading Performance - Low Power - Scalability - Industrial-grade Reliability, Temperature & Product Longevity
Freescale Bundled IDE, RTOS & Firmware - Tower rapid prototyping Platform - ARM Ecosystem Support
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore
and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a
TM 2 Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc.
Feature rich
Easy-to-use
Connectivity
Extended battery life
Sleek design
User expectations
8/16-bit MCU 32-bit MCU
Connectivity
User Interface
Ultra low sleep/ Maximum

Power
power-down energy-efficiency
Consumption
currents (CoreMark/mW)
+ ×
√ ∫
n
Computation sin log
- ÷ x
n
Software/Cost Unique platforms, Scalable, reusable platforms with

of Ownership MCU dependent/$$$ modern software techniques/$
Scalability
Limited choice, Broad MCU portfolios,
single-source multi-source
Building Control Instrumentation &
Banking
Medical
Smoke Detector Thermostat
Cash Registers
OTP
Mass-Market Mass-Market
Joy Sticks Remote Controller Aero Model

ETC
Electronic Label Fiber Module
Scale Mouse
RFID Shaver GPS Watch
Cortex-M Compatibility
•Cortex-M compatibility – 100% compatible with

Cortex-M0 instruction set and a subset the Cortex-
M3/M4 instruction set, allows reuse of existing
compilers and debug tools minimising migration effort
•Simplified architecture with 8-bit look & feel –
only 56 instructions and 17 registers, enables easy
programming and efficient packaging of 8/16/32-bit
data in memory
•Linear4 GB address space - removes the need for
paging/banking, reducing software complexity L Series K Series
•Nested Vectored Interrupt Controller (NVIC) – CoreSight™ Micro Trace Buffer (MTB)
manages interrupt prioritisation, masking and nested
interrupt handling Read trace Store trace
information information
•Micro trace buffer – provides a light weight trace ARM
Cortex-M0+
solution that allows faster bug identification and
correction without the need for additional I/O
AHB
resources
MTB Controller
•Supported by the extensive ARM 3rd party •Trace stored in
RAM (non intrusive) RAM Appl. Data
ecosystem – large range of off-the-shelf software •Read over Serial I/F +
and tools help minimise development time/cost Wire /JTAG (CPU SRAM Trace Data
stopped)
TM
•Cortex-M0+ processor
•Energy-saving MCU architecture
•Breakthrough low-power performance
•Energy-saving peripherals Most Innovative

Process Technology
Processor Energy Efficiency
in CoreMark/mA
45 42.14
•More than 2x CoreMark/mA performance than the 40
closest 8/16-bit competitor and 30% less power 35
consumption than Cortex-M0 30 X2.25
25
•2x
to 40x more performance than 8- and 16-bit and 9% 18.6
20
more performance than Cortex-M0 15
10.09
•Fast I/O port – single-cycle access to I/O and critical 10
6.04
5.29
peripherals (up to 50% faster than normal I/O), 5
improves reaction time to external events allowing bit- 0
Corex-M0+ A (16-bit) B (16-bit) C (8-bit) D (8/16-bit)
banding and software protocol emulation All values shown in chart are core consumption estimates with optimal operation from flash
@ ~1.8-2.2V. Values extracted from public data sheets
•2-stage pipeline – reduced number of cycles per

CoreMark Code in kB
instruction (CPI) enables faster branch instruction and 12,000
ISR entry, reduced power consumption and increased 10,206 10,066
10,000
performance
•Optimized access to program memory – accesses on 8,000
6,446
alternate cycles reduces power consumption 6,000 5,418
4,896
•Excellent code density vs. 8-bit and 16-bit 4,000
architectures – reduced flash size, system cost and
2,000
power consumption for a given application while
delivering significantly higher performance 0
Corex-M0+ A (16-bit) B (16-bit) C (8-bit) D (8/16-bit)
CoreMark code compiled optimized for size. A, B, C & D: same low power MCUs as in
previous slide
Source: http://arm.com/products/processors/cortex-m/index.php
Instruction Efficiency – New for ARM
Cortex-M0+ is
single cycle
multiply
Very Low Active and Standby
Energy Saving Peripherals Reduced Processing Time
Power Consumption
Initialization Collect Data Compute
Ultra-low
Active
Current
ENERGY SAVINGS
Power
Ultra-low
Standby
Current
Deep Sleep Mode
Time
RUN @3V, 48 MHz 84 uA/MHz VLLS0 Deep Sleep @3V 150 nA CoreMark/MHz 1.77
VLPR @3V, 4 MHz 50 uA/MHz LLS Deep Sleep @3V 1.4 uA LLS Wake-up Time 4.6 us
Kinetis Power Recovery L-Series Estimation
Modes Time “Typical” Idd Range
Leading Dynamic Power RUN - 84uA/MHz*

Innovative low power process technology (C90TFS) VLPR - 50uA/MHz**
Low power focused platform design WAIT - TBD
Next Generation Cortex M0+ core VLPW 4us TBD
Asynchronous DMA Wake-up (ADMA) STOP 4.3us From 220uA

Energy-saving peripherals are operational with ADMA
feature that can wake-up DMA to perform data transfer and VLPS 4.3us From 2.7uA
return to current mode when complete
Low Leakage Wake-up Unit LLS 4.6us From 1.4uA

Enables complete shut-down of core logic, including AWIC,
VLLS3 53us From 1uA
further reducing leakage currents in all low power modes
Supports 8 external input pins and 8 internal modules as
wakeup sources; extends the low power wake-up capability VLLS1 115us From 640nA
of some internal peripherals to all power modes.
Wake-up inputs are activated in LLS or VLLS modes VLLS0 115us From 150nA
* All Modules Off enabled: 4.0mA @ 48MHz core / 24MHz bus)
** All Modules Off enabled: 200uA @ 4MHz core / 1MHz bus)
and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, Airfast, BeeKit,
BeeStack,
BeeStack,
ColdFire+,
ColdFire+,
CoreNet,CoreNet,
Flexis, Kinetis,
Flexis, Kinetis,
MXC, Platform
MagniV,in a
TM 12 Package,
MXC, Platform
Processor
in a Package,
Expert, QorIQ
Processor
Qonverge,
Expert,Qorivva,
QorIQ Qonverge,
QUICC Engine,
Qorivva,
SMARTMOS,
QUICC Engine,
TurboLink,
ReadyVortiQa
Play, SafeAssure,
and XtrinsicSMARTMOS,
are trademarks
TurboLink,
of Freescale
VortiQa
Semiconductor,
and Xtrinsic Inc.
are
All other product
trademarks of Freescale
or service
Semiconductor,
names are theInc.
property
All other
of their
product
respective
or service
owners.
names© are
2011theFreescale
property Semiconductor,
of their respective
Inc.
owners. © 2012 Freescale Semiconductor, Inc.
Intelligent peripherals increasing time in deep sleep modes with no CPU
intervention for increased battery life
Peripheral Low Power Functionality
Allows energy-saving peripherals (ex. ADC, UART and Timer/PWM) to trigger asynchronous DMA request in
DMA
STOP/VLPS modes to perform DMA transfer and return to current power mode with no CPU intervention
Supports asynchronous transmit and receive operations to the bus clock supporting communication down to
UART STOP/VLPS modes. Configurable receiver baud rate oversampling ratio from 4x to 32x allowing higher baud rates
with lower clock sources
SPI Supports slave mode address match wake-up function down to STOP/VLPS modes
I2C Supports multiple address match wake-up function down to STOP/VLPS modes
USB Supports asynchronous wakeup on resume signaling down to STOP/VLPS
LPTPM
Supports 16-bit timer input capture, output compare and PWM functions down to STOP/VLPS modes
(Timer/PWM)
LPTMR
(Timer/Pulse Supports 16-bit timer and pulse counter functions in all power modes
Counter)
Supports 32-bit seconds counter with seconds interrupt and programmable alarm in all power modes with include
RTC
temperature and voltage compensation
Intelligent peripherals increasing time in deep sleep modes with no CPU
intervention for increased battery life
Peripheral Low Power Functionality
Supports single conversions in multiple result registers down to STOP/VLPS modes with hardware averaging and
ADC
automatic compare modes
CMP
Supports threshold crossing detection in all power modes along with a triggered compare mode for lower
(Analog
Comparator) average power compares
DAC Supports static reference in all power modes
Segment LCD Supports alternate displays and blink capability in all power modes
TSI
(Capacitive
Touch Sense
Supports wake-on capacitive touch on single channel in all power modes
Interface)
LLWU
Supports 8 wake-up pins, RESET and NMI wakeup pins, and some energy-saving peripherals in LLS and
(Low-Leakage
Wake-up Unit) VLLSx modes
BME Decorated load and store capability for improved peripheral processing efficiency for AND/OR/XOR/CLEAR
(Bit Manipulation FLAG/SET FLAG/BIT EXTRACTION functions to individual bits (ideal for 8/16-bit applications where manipulating
Engine) individual bits is very common)
TM
Select right part with simple clinks
Features:
• Web-based application that features
an interactive MCU product
selector.
• Identify the best MCU by applying
dynamic filters based on:
− Operating characteristics
− Packaging options
− Memory configuration
− Peripheral hardware library
• Verify pin muxing compatibility
• Identify compatible and relevant
Tower System modules
• Save, restore an share sessions for
reviewing and critiquing design
possibilities
• View, download and print summary
reports and pin muxing configurations
• Standards based HTML application
Tower
TWR-KL25Z48 FREEDOM-KL25Z
• Richer feature set • Reduced feature

• Standard Tower evaluation and
Controller Module development boards
• Compatible with • $12.95 SRP
existing Tower
System peripherals
• <$99 SRP
GNU Tools
7 Steps
www.freescale.com.processorexpert
Create Project Configure Components Generate Code Build & Debug
1 3 • Use Inspector to set all 5 • Processor 7 • Build the
component settings Expert application
generates • Debug the
components application
Software Development Timeline
Add Components Verify Settings Write Application Code

2 • Add components to the
4 • Verify no design-time
6 • Write application code
project from Components errors in the project using code generated for
Library components
MQX Lite Kernel (PSP)
• A light weight MQX kernel targeted for resource limited
Kinetis L/E Series, other MCUs and DSCs
− Target code size less than 6KB
• Compatible programming model with standard MQX to
enable an upgrade path
• Processor Expert (PEx) Integration
Additional Components and Stacks:

• Basic USB device support only • Integration available from PEx
− HID, CDC, Audio • USB device stack
• TSS library
• No TCP/IP stack (RTCS)
• No file system support (MFS)
• The embedded market needs long-term product
support
• Freescale has a longstanding track record of
providing long-term production support for our
products
• Freescale is pleased to introduce a formal product
longevity program for the market segments we serve
− For the automotive and medical segments, Freescale
will make a broad range of program devices available
for a minimum of 15 years
− For all other market segments in which Freescale
participates, Freescale will make a broad range of
devices available for a minimum of 10 years
− Life cycles begin at the time of launch
• For terms and conditions and to see a list of
participating Freescale products available under this
program: www.freescale.com/productlongevity
TM
Kinetis X Series
ARM Cortex M4 200MHz Kinetis X Series
Kinetis K Series
ARM Cortex M4 50-150MHz
K70 Family 120/150MHz,
512KB-1MB, Graphics LCD, Ethernet,
Kinetis L Series USB (FS/HS) Encryption, Tamper, DRAM
ARM Cortex M0+ 48MHz
K60 Family 100-150MHz, 256KB-1MB,
Ethernet, USB OTG (FS/HS), Encryption, Tamper Detect, DRAM
K50 Family 72-100MHz, 28-512KB,

Analogue, USB OTG (FS), E’net, SLCD, Encryption
K40 Family
72-100MHz, 64-512KB, USB OTG (FS), SLCD
Feature Integration
KL4 Family
USB OTG (FS), SLCD
K30 Family
72-100MHz , 64-512KB, Segment LCD
KL3 Family
SLCD
K20 Family
50-120MHz, 32KB-1MB, USB OTG (FS/HS)
KL2 Family
USB OTG (FS)
K10 Family
50-120MHz, 32KB-1MB, Low Power, Mixed Signal
KL1 Family
General Purpose
KL0 Family
8-bit S08P compatible
<=24pin 32pin 48pin 64pin 80pin 100pin 121pin 144pin 256pin

Pin Count Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore
GPIO etc
GPIO etc
LLWU
LLWU
GPIO
GPIO
ADC
ADC
Fully Hardware Compatible
48 37 48 37
1
1
Digital
Follow Same Digital
36
36
Power Power
ADC/TSI Pin Assignment Rule ADC/TSI
GPIO etc. GPIO
etc.
USB USB
KL25 Reset
K20 Reset
GPIO GPIO
ADC DP
Ch
GPIO etc.
48-pin ADC DP
Ch 48-pin
Clock Clock
GPIO etc (3~32M)
Analog Analog GPIO etc
25
25
12
12
Power Same Peripheral Register Power
13 24 Setting for common features 13 24
Clock (32K)
VREFOUT
DAC/ADC
GPIO etc.
GPIO etc
GPIO etc
HSCMP
HSCMP
HSCMP
Digital
Power
Digital
Power
JTAG
Software Compatible,
SWD
SWD
ADC
ADC
Vbat
TSI
TSI
C-Code Reusable
Take 3 Steps for easy Migration:

Step 1 Step 2 Step 3
Check Hardware difference Check Software difference Optimize the Design
 Power Pin (Vbat)  DMA configuration  Adopt new head file and
 External Clock Input  Watchdog Service Routine reuse the C code by modifying
(32KHz/3~32MHz)  Low Power usecase (New the difference
 Analog interface (DAC, features added on L-Series)  Add new features support
Vref_Out)  BME (new on L-Series) in design that specific to L-
 Debug Interface (JTAG)  MTB (new on L-Series) Series or K-Series
 GPIO pinmux  GPIO Map (More on L-Series)
 Flexmemory (K-Series only)
* Detail technical migration guide will be available on Freescale website @ Launch Date
TM
Available 2012, up to 128KB
Available 2013, up to 256KB
Common Features Optional Features

System Key Features
ARM Cortex-M0+ Core, 48MHz Family Flash SRAM USB Seg.
DMA
Cross- ADC DAC I2S TSI
OTG LCD
Multiple low-power modes, Clock Gating, 1.71V - 3.6V Bar
Operating Temp: -40 to 105°C [1] KL46 128-256KB 16-32KB √ √ √ 16-bit 12-bit √ √
Memory
90nm TFS Flash, SRAM KL36 64-256KB 8-32KB √ √ 16-bit 12-bit √ √
Internal Memory Security/Protection KL34 64KB 8KB √ √ 12-bit
Analog Peripherals
12/16-Bit ADC KL26 128-256KB 16-32KB √ √ 16-bit 12-bit √ √
High-Speed Comparators KL25 32-128KB 4-16KB √ √ 16-bit 12-bit √
Serial Interfaces KL24 32-64KB 4-8KB √ √ 12-bit
SCI (Including 1 LPSCI)
SPI, IIC KL16 256KB 16-32KB √ 16-bit 12-bit √ √
Timers KL15 32-128KB 4-16KB √ 16-bit 12-bit √
Real Time Clock [2] KL14 32-64KB 4-8KB √ 12-bit
16bit Low Power TPMs (GP Timer/PWM)
Low Power Timers KL05 8-32KB 1-4KB √ 12-bit 12-bit √
32bit Periodic Interrupt Timer KL04 8-32KB 1-4KB √ 12-bit
KL02 8-32KB 1-4KB 12-bit
[1] Feature not available on CSP packages

[2] For KL02, use software to support
USB + Seg. LCD KL4x KL4x
Segment LCD
KL3x KL3x
USB
256KB General Purpose KL2x KL2x KL2x
Entry Level
KL1x KL1x
KL4x KL4x
KL3x KL3x
128KB
KL2x KL2x KL2x KL2x KL2x KL2x
Flash Memory
KL1x KL1x KL1x KL1x KL1x

Flash Memory
KL3x KL3x
64KB KL2x KL2x KL2x KL2x KL2x

32KB
16KB KL0x KL0x KL0x KL0x KL0x
8KB KL0x KL0x KL0x KL0x
<24 pin* 24 25 32 35 48 64 80 100 LQFP/

QFN WLCSP* LQFP/ QFN WLCSP* LQFP/QFN LQFP / MBGA LQFP 121 MBGA
* Under Proposal TM 26 and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a
Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc.
Package All other product or service names are the property of their respective owners. © 2011 Freescale Semiconductor, Inc.
Kinetis K Series Package *Proposed
Kinetis L Series Package *Proposed
Common Packages
32QFN 48QFN 32LQFP 48LQFP 64LQFP 80LQFP 100LQFP

5 x 5 mm 7 x 7 mm 7 x 7 mm 7 x 7 mm 10 x 10 mm 12 x 12 mm 14 x 14 mm
0.5mm pitch 0.5mm pitch 0.8mm pitch 0.55mm pitch 0.5mm pitch 0.5mm pitch 0.5mm pitch
(K10/20) (K10/20) (K10/20) (K10/20) (K10/20/30/40/50) (K10/20/30/40/50) (K10/20/30/40/50/60)
(KL0/1/2) (KL1/2) (KL0x) (KL0) (KL1/2/3/4) (KL1/2) (KL2/3/4)
Kinetis K Series only

64MAPBGA 121MAPBGA
5 x 5 mm
New New New New
8 x 8 mm
0.5mm pitch 0.65mm pitch
(K10/20) (K1/2/30/40/50/60)
(KL1*/2*/3*/4*) (KL2/3/4)
56CSP 90CSP 121CSP 143CSP
3 x 3 mm 4 x 4 mm 5 x 5 mm 6 x 6 mm
0.4mm pitch 0.4mm pitch 0.4mm pitch 0.4mm pitch
Kinetis L Series only (K10*/20*) (K10*/20*) (K10/20/60) (K61)
New
New New
25CSP 35CSP 24QFN

2.35 x 2.88 mm <3 x 3 mm 4 x 4 mm
0.4mm pitch 0.4mm pitch 0.5mm pitch 144LQFP 144MAPBGA 256MAPBGA
20 x 20 mm 13 x 13 mm 17 x 17 mm
(KL0*) (KL1*/2*) (KL0)
0.5mm pitch 1.0mm pitch 1.0mm pitch
(K10/20/30/40/50/60) (K10/20/30/40/50/60) (K60/70)
System Unique ID Clock Management Energy Management
Crystal
CM0+Core Debug
COP
LPO Oscillator LS Osc
Ultra-low power (1KHz) (low&high (32KHz) Voltage Regulator
(SWD) RST
48MHz bus freq. range)
Flash RAM ULP Osc Power On Low Voltage

1-32K
DMA 4-ch FLL PLL
(4MHz) Reset Detector
8-256K
Peripheral Bus
Analog Interfaces Timers Connectivity USB OTG I/O Ports

4chDP+ 8chSE 16-bit 2ch SCI LPSCI I2S FS/LS Up to 80 GPIO
16b LPTPM
/ 16chSE 12bit 32bit x2 x1 x1 Transceiver [5] (4 High Dive)
6ch x1, 2ch x 2
SAR ADC /w DMA PIT w/ 25 interrupt
SRTC w/ SPI x 2 USB Controller
12-bit temperature LPTMR
TSI x RST/
HSCMP
DAC compensation I2C x 2 V Regulator 16ch Input
Stop/ VLLS VLLS VLLS Display

Operation in: Run Wait VLPS 3 1 0
47x8/51x4
TM
•Kinetis L-Series Platform is the system level interconnectivity between the
ARM Cortex-M0+ core and the rest of the system on chip
•The platform is comprised of system clocking and control, hardware

acceleration blocks for code execution and memory interfaces, debug buffers,
etc.
• ARM Cortex-M0+ Core
− NVIC with 4 priority levels and hardware preemption
− Efficient instruction set for low power and small code size
− Micro-Trace Buffer (MTB) for on-chip trace capabilities
− I/O port for single cycle GPIO loads and stores
• Bit Manipulation Engine (BME)
− Decoratedload and store capability for peripherals improving
processing efficiency and small code size
• Peripheral Bridge Crossbar (AXBS-Lite)
− Supportfor concurrent accesses from DMA/CORE to memory and
peripherals
• Flash Memory Controller (FMC)
− 4-way, 4-set 32-bit Flash cache for improving flash access times
• Kinetis L-Series devices support DMA operation in low power modes
− Stop modes can be entered with the System Clock enabled
 This allows peripherals with STOP mode functionality to trigger asynchronous
DMA request
 The MCU will wake from STOP mode, process the DMA request and then re-
enter the STOP mode with no CPU intervention
− The MCU can be placed in a Compute mode with peripherals
configured for STOP
 In this mode, the CPU can continue to process data at very low dynamic
power
 Peripherals with STOP mode functionality can continue to operate and trigger
DMA transfers
• Use Case
− ADCperforming conversions, DMA transferring conversion results into
RAM buffer and CPU processing/filtering the data all done with minimal
power ~ 300uA at 4MHz Core speed
• New to the ARM Cortex M0+, the Micro-Trace buffer is an
efficient way of expanding debug capabilities
• When enabled, the MTB records changes in program flow
(branches and interrupts) reported by the processor into a
configurable region of the SRAM
• Subsequently either an on-chip or off-chip debugger may
extract the trace information which would allow reconstruction
of an instruction flow
ARM Cortex- MTB Port System

M0+ Core
RAM
• Embedded Serial Debug Adapter
• New standard for embedded debug OpenSDA
circuit supporting SWD and JTAG
• Open hardware platform with OpenSDA MCU
K20DX128Vxx5
proprietary and open-source software
• Built on K20DX128 50MHz CM4
• Provides serial channel and debug MSD Bootloader
interface to the target MCU to Target MCU
UART TX/RX
• Mass-storage bootloader used to load UART RX/TX
new applications into the OpenSDA GPIO / Interrupt
OpenSDA
• A mix of proprietary and open-source Application
RESET
OpenSDA Applications will be available SPI, GPIO

SWD / JTAG
free-of-charge from Freescale
• Customers and partners can develop
their own Applications as well.
• New to the ARM Cortex M0+, the I/O port improves execution time for loads
and stores to GPIO on L-Series devices
− Previous loads and stores took a minimum 2 System clock cycles
− New I/O port accesses will support 1 system clock cycle loads and stores
• Reduce latency involved with I/O control
− Respond to fault events quickly
• Improved code execution efficiency
− Shorter execution times can lead to lower dynamic power
I/O PORT
ARM Cortex-
M0+ Core RGPIO
• The BME is a hardware block that resides between the
platform and L-Series Core that allows read-modify-write
operations to be performed on peripheral registers using data
stored in the target address
− Decorated Stores
 AND, OR, XOR and Bit field insert (BFI)
− Decorated Loads
 Load and clear one bit (LAC1), Load and Set one bit (LAS1), Unsigned bit
field extract (UBFX)
Peripherals
Core Accesses BME
• Decorated store: OR operation Peripherals
New for ARM
contain normal
Cortex-M0+ is
access space
single cycle
and decorated
multiply
access space
Data within the

decorated
address space
defines the
operation
• The crossbar switch (AXBS-Lite) allows concurrent accesses from
different masters to different slaves
• If two or more masters try to access the same slave
− Two priority schemes can be set
 Fixed priority: Higher numbered masters always gain control at the end of a transfer
 Round Robin where the priority is set based on the relative position to the last
master to control the slave
AXBS Flash
FMC 32
32
4-Way by 4-set x 32-bit

for a total of 64bytes
The FMC sits between the platform masters (Core, DMA, etc) and the Flash and
accelerates access time with buffers which will provide 0 wait state access times
when hit.
Each access of the Flash pulls 32bits into the FMC cache buffer
ADC
• Typical performance of >12 ENOB for increased measurement accuracy without external
components available on some devices
• Hardware averaging by 1, 4, 8, 16, or 32 to automatically filter ADC conversions without software
intervention
• Automatic Compare Function and operation in Very Low Power Stop mode for low power poling with
average power in the 100uA range
• Configurable resolution, sample time, speed and power (8/10/12/16-bit resolution, available on
some devices)
• Input multiplexor with to support many input channels eliminates the need for external multiplexors
DAC
• 12-bit Resolution guaranteed
monotonic
• Dual half-word buffer
• Hardware or software triggering
ACMP (Analog Comparator)

• Internal 6-bit DAC for variable
compare
• Functional in low power modes
• Configurable propagation delay and
hysteresis
• 2-Ch PIT (Programmable Interrupt Timer)
− 32bit timers for general purpose time keeping
− Interconnected to DMA channels 1&2 for easy DMA triggering
• 6-ch + 2ch FTM timer modules on all devices (additional 2ch

on some devices)
− 16bit timer configurable for OC/IC and PWM Generate PWMs while
− Center aligned PWM modes the MCU is in low
− Up count or up-down count capabilities power modes
− Functional in sleep modes (stop mode)
• LPTMR Low power Timer

− 16bit timer/pulse counter available in deep sleep modes
• RTC Real time Clock

− 32bit seconds counter with alarm
In addition to standard UART
• UART FEATURES
features the L-Series UART
• Full-duplex, standard non-return-to-zero (NRZ) format
includes the capability of
• Double-buffered transmitter and receiver with separate enables running from an separate
• Programmable baud rates (13-bit modulo divider) clock source. This enables
• Transmit and receive baud rate can operate asynchronous to the bus clock: operation in stop modes .
• Baud rate can be configured independently of the bus clock frequency
Also, the capability to
• Supports operation in Stop modes
configure the baud rate over
• Configurable receiver baud rate oversampling ratio from 4x to 32x sampling ratio allows higher
• Interrupt, DMA or polled operation: baud rates to be achieved
• Transmit data register empty and transmission complete with lower clock sources.
• Receive data register full For example 115200baud
• Receive overrun, parity error, framing error, and noise error
can be achieved with a
0.4608Mhz clock source with
• Idle receiver detect
4x oversampling ratio
• Active edge on receive pin
• Break detect supporting LIN
• Hardware parity generation and checking
• Programmable 8-bit, 9-bit or 10-bit character length
• Programmable 1-bit or 2-bit stop bits
• Receiver wakeup by idle-line, address-mark or address match
• Optional 13-bit break character generation / 11-bit break character detection
• Selectable transmitter output and receiver input polarity
• TSI: Touch Sense Interface
− Support for up to 16 Electrodes
 Support for Wheels/sliders
− Configurable for software or hardware triggering of scan
− Operation in deep sleep modes
 Low power consumption
− No external components needed
Avoid high cost/ high power alternatives
GPIO & Software method: External ASIC method:
•requires ext. components •Cost of external
•not low power (needs CPU) component
•poor noise immunity •Increased PCB space
• Segment fault detection capability
− Hardware support for segment LCD display errors
 Essential when displayed data is safety critical
 Automates factory test for end product
• Up to by 8 multiplexing
− Fewer pins required to drive LCD segments
 Kinetis: 48 pins needed to drive 320 segments
 Competition: 84 pins needed to drive 320 segments
• Front and back plane re-assignment

− Any LCD pin can be a frontplane or backplane pin or GPIO function
− Assist in vertical scrolling on dot-matrix displays
• Internal charge pump provides voltage required to power LCD glass

− Internally regulated voltage for constant contrast across MCU VDD
− Trim register for software contrast control
− Drive for 3V or 5V LCD glass
• Low power blinking mode
− LCD glass blink capability in low power modes
− Alternate display feature can be activated to display alternate data (i.e. blink temperature and
time)
TM
• Rich set of Freescale enablement:
• CodeWarrior with Ease-of-Use improvements
• Processor Expert: Stand-alone and integrated
with CodeWarrior
• MQX Lite: delivered via Processor Expert
• Embedded debug circuit (OpenSDA) enabling
quick and easy demonstrations and tools
compatibility:
• Mass storage device flash programming
interface (default) – no tool installation required
to evaluate suite of demo apps
• P&E Multilink interface provides run-control
debugging and compatibility with IDE tools.
• Open-source Data Logging application
provides an example for customer, partner and
enthusiast development on the OpenSDA
circuit
• Support from our Ecosystem Partners:
• IAR Embedded Workbench
• Keil MDK
• Code Red – Red Suite
• Atollic TrueSTUDIO GNU Tools
• Rowley Crossworks
• Free GNU command-line tools with GDB server
Enablement
TWR-
MCF51MM
TWR-
TWR-MPC5125
TWR-S08LL64 S08MM128
TWR-S08UNIV TWR-
TWR-PROTO MCF5225X
TWR-ELEV
TWR- TWR-
K60N512 TWR-
MCF51CN
S12G128
MED-
EKG ... to be
continue
TWR-SER
TWR-WIFI-AR4100 TWR-xxx-xxx
TWR-WIFI-RS2101 TWR-WIFI-G1011MI
TWR-LCD
TWR-SENSOR- Online
PAK community
TWR-MEM dedicated to
TWR-AUDIO-SGTL
our Tower
System
TWR-SER2 TWR-ADCDAC-LTC
Enablement
Run-Time Software: RTOS, Stacks, File System
IDE:
Tools Compliers, Debuggers
+ ProcessorExpert
GNU Tools HW BDM Debugger/Emulators
Enablement
GUI Graphical Audio/Video Codecs
Ind. Protocol Stacks
Security / Medical
MQX Support / Design Services
www.embedded-access.com
EVBs & System Design

Summary
Freescale is leading the development of
next generation ARM-based MCUs in
the embedded market
Kinetis L Series Cortex M0+ MCUs offer a

game-changing combination of energy-
efficiency, ease-of-use and value as well
as scalability into the existing Kinetis K
Series ARM Cortex-M4 MCU portfolio
Freescale is demonstrating the Kinetis L

Series at FTF June 2012 and has started
its global alpha customer program
Devices within the Kinetis L Series MCUs

will be launched to the mass market in
September and in full production by the
end of 2012
www.freescale.com/kinetis/Lseries
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
TM 50 Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
TM

Silica MCU Summit Italy Freescale Kinetis L Series

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TM

Extended battery life

Ultra low sleep/ Maximum

Software/Cost Unique platforms, Scalable, reusable platforms with

Joy Sticks Remote Controller Aero Model

Electronic Label Fiber Module

•Cortex-M compatibility – 100% compatible with

•Energy-saving MCU architecture

•Breakthrough low-power performance

•Energy-saving peripherals Most Innovative

•2-stage pipeline – reduced number of cycles per

Deep Sleep Mode

Leading Dynamic Power RUN - 84uA/MHz*

Asynchronous DMA Wake-up (ADMA) STOP 4.3us From 220uA

Low Leakage Wake-up Unit LLS 4.6us From 1.4uA

USB Supports asynchronous wakeup on resume signaling down to STOP/VLPS

DAC Supports static reference in all power modes

• Richer feature set • Reduced feature

Software Development Timeline

Add Components Verify Settings Write Application Code

Additional Components and Stacks:

K50 Family 72-100MHz, 28-512KB,

<=24pin 32pin 48pin 64pin 80pin 100pin 121pin 144pin 256pin

Power Same Peripheral Register Power

13 24 Setting for common features 13 24

Take 3 Steps for easy Migration:

Available 2013, up to 256KB

Common Features Optional Features

Internal Memory Security/Protection KL34 64KB 8KB √ √ 12-bit

High-Speed Comparators KL25 32-128KB 4-16KB √ √ 16-bit 12-bit √

Serial Interfaces KL24 32-64KB 4-8KB √ √ 12-bit

SCI (Including 1 LPSCI)

SPI, IIC KL16 256KB 16-32KB √ 16-bit 12-bit √ √

Timers KL15 32-128KB 4-16KB √ 16-bit 12-bit √

Real Time Clock [2] KL14 32-64KB 4-8KB √ 12-bit

16bit Low Power TPMs (GP Timer/PWM)

Low Power Timers KL05 8-32KB 1-4KB √ 12-bit 12-bit √

32bit Periodic Interrupt Timer KL04 8-32KB 1-4KB √ 12-bit

KL02 8-32KB 1-4KB 12-bit

[1] Feature not available on CSP packages

KL1x KL1x KL1x KL1x KL1x

64KB KL2x KL2x KL2x KL2x KL2x

KL1x KL1x KL1x KL1x KL1x

KL2x KL2x KL2x KL2x KL2x

KL0x KL0x KL0x KL0x KL0x

16KB KL0x KL0x KL0x KL0x KL0x

8KB KL0x KL0x KL0x KL0x

<24 pin* 24 25 32 35 48 64 80 100 LQFP/

Kinetis L Series Package *Proposed

32QFN 48QFN 32LQFP 48LQFP 64LQFP 80LQFP 100LQFP

Kinetis K Series only

25CSP 35CSP 24QFN

Flash RAM ULP Osc Power On Low Voltage

Analog Interfaces Timers Connectivity USB OTG I/O Ports

Stop/ VLLS VLLS VLLS Display

•The platform is comprised of system clocking and control, hardware

ARM Cortex- MTB Port System

OpenSDA Applications will be available SPI, GPIO

Data within the

4-Way by 4-set x 32-bit

ACMP (Analog Comparator)

• 6-ch + 2ch FTM timer modules on all devices (additional 2ch

• LPTMR Low power Timer