ELEC 5804

VLSI DESIGN

FALL Term 2023

 Big Picture View

Abstract Physical
 Think Like A Designer
The designer of an integrated circuit must weigh the
consequences of:
• wafer cost,

• level of integration,

• performance,

• economics,

• and time to market.

 Techno-Hodgepodge
The requirements of wafer cost, level of
integration, performance, economics, and time
to market often lead designers into using several
technologies within a system.
Commercial implementations of high performance
systems may use a mixture of technologies, including
CMOS, BiCMOS, BJTs, GaAs FETs, and HBTs.
 Multi-chip Modules

Seven dies mounted on a laminate substrate along with numerous discrete components (looks like decoupling/
by-pass capacitors, and some resistors). Source: Elektronik no.12 2004 p.24.
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Example #2: RF Receiver circa 1995
Discrete LO2@0

CMOS Si LPF
LO @0
Rx A/D
Bipolar Si
SAW LNA BPF BPF Mx Gx
GaAs
DSP
Mx Mx LPF
Gx
A/D
Antenna
Gx

LO2@90

Duplex

Note the number of technologies required, due to performance issues. Over the
past decade CMOS moved toward the antenna as technology improved.
 Our Focus:
Our focus in this course is on single-chip solutions. We will discuss the IC boundary as well (bringing signals on and off chip). So our discussions
will involve single technologies for our design. Be aware however that mixed technologies are commonly used.

Intel 80386 Microprocessor. A monolithic CPU. Pentium Pro multichip module with processor
(left) and 256-KB cache (right) in a pin grid
array (PGA) package.
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 Cost & Availability
Much of this course is concerned with the application of the Metal-Oxide-
Semiconductor Field-Effect Transistor (MOSFET), for reasons of:

• Cost – with CMOS technology we take advantage of economy of scale

and the price per device can be extremely small.

• Availability – it is possible to run a “fabless” design company these days

due to the accessibility of fabrication facilities. The most accessible
technology is currently Complementary Metal-Oxide-Semiconductor
(CMOS).
 MOSFET Advantages
Primary advantages of MOSFET technology over other types of integrated devices include:
• its mature fabrication technology,
• its high integration levels,
• its mixed analog/digital compatibility,
• its capability for low voltage operation,
• its successful scaling characteristics,
• and the combination of complementary MOSFETs yielding low power CMOS circuits.
 Industry Players
• Integrated device manufacturer (IDM) is the name for a company that not
only designs and markets microchips but that also does the wafer processing in-
house in their own semiconductor fabrica-tion plant or fab for short. Examples:
Intel, Samsung, Toshiba, ST-Microelectronics, Texas Instruments, Cypress Semicon-
ductor, AMS.
• Silicon foundry, albeit technically incorrect, designates a company that operates
a complete wafer processing line and that offers its manufacturing services to
others. Examples: TSMC, UMC, SMIC, etc.
• Fabless vendor. A company that develops and markets proprietary
semiconductor components but has their manufacturing commissioned to an
independent silicon foundry rather than operating any wafer processing facilities
of its own. Examples: Altera (FPL), Actel (FPL), Broadcom (networking components),
Cirrus Logic-Crystal (audio and video chips), Lattice Semiconductor (FPL), Nvidia
(graphics accelerators), PMC-Sierra (networking components), Qualcomm (chipsets
for wireless telecommunication), and Xilinx (FPL).
Hubert Kaeslin - Top-Down Digital VLSI Design_ From Architectures to Gate-Level Circuits and FPGAs-Morgan Kaufmann (2014)
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• Fab-lite vendor is the name for a company that outsources standard wafer
processing steps but retains the limited and highly specialized manufacturing
capabilities required to integrate sensors, actuators, microelectromechanical
systems, RF components (such as high-Q inductors and RF switches), photonic
devices, or the like, in a silicon substrate along with electronic circuitry. This
approach typically implies that fully or partially processed CMOS wafers undergo
a series of nal processing steps at the vendor’s own facilities. Examples: Luxtera,
Sensirion.
• Intellectual property (IP) vendor. A fabless company that makes it a business
to develop hardware subfunctions and to license them to others for incorporation
into their ICs. Intellectual property here refers to any kind of predeveloped
electronic subfunction such as standard cells, macrocells, megacells, or virtual
components. Examples: ARM, Faraday, Sci-worx, Synopsys.
Originally, all IC business had been con ned to vertically integrated semiconductor
companies that designed and manufactured standard parts for the markets they
perceived. Opening VLSI to other players was essential to instilling new and highly
successful fabless business models. Three factors came together in the 1980s to make this
possible.
• Generous integration densities at low costs.
• Proliferation of high-performance engineering workstations and EDA software.
• Availability of know-how in VLSI design outside IC manufacturing companies.
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Predicting Future Technology

• Why is it important to do so?

Process Introduction Ramp
SIA Roadmap
 Moore’s Law
Moore's law is an empirical observation stating that the complexity of
integrated circuits doubles every 18 months.
It is attributed to Gordon E. Moore (a co-founder of Intel). Moore outlined his
"law" in 1965. His original empirical observation was that the number of
components on semiconductor chips with lowest per-component cost doubles Gordon Moore's original graph from 1965

roughly every 12 months, and he conjectured that the trend will stay for at
least 10 years.
In 1975, Moore revised his estimate for the expected doubling time, arguing
that it was slowing down to about two years.

From: http://www.intel.com/technology/mooreslaw/index.htm
 Moore’s Law Applied to Transistor Size & Count
“# of Transistors on a chip will double every 18 months”

• size of chips increases slightly (1cmx2cm for Pentium)

• biggest impact is scaling of technology (/2 every 3 years)

• speed : 2X MIPS/yr

• hitting limits : lithography, physical, modelling, complexity, interconnect, testing

Incorrect Application of Moore’s Law: Clock Speed
Semiconductor Scaling Over Time

http://www.intechopen.com/source/html/9855/media/image1.jpeg
 Bene ts of Geometry Scaling
Smaller transistors mean:
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• faster devices (ft ∝ L2
for long channel
devices)

• more transistors per wafer → smaller dice→

cheaper devices

• lower power consumption

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 Limitations?

• What limits device scaling?

Charge Density Limit
Feature Size Trend

http://www.synopsys.com/products/ntimrg/inphase_ds.html
Diffraction - Airy Disk
How to Get Sub-Wavelength Features

• High contrast photo-resist

• OPC (Optical proximity correction)
• Phase shift masks.
.

Optical Proximity Correction

Desired shape

Projected shape
Optical Proximity Correction

OPC shape

Projected shape
Optical Proximity Correction
Desired shape OPC shape

Projected shape Projected shape

Optical Proximity Correction
Phase Shift Masks

from: Hubert Kaeslin, Digital Integrated Circuit Design

 IC Process Knowledge

• Some level of knowledge concerning IC

processing is important for IC designers at
all levels
• Circuit designs, layout designs, timing, etc. are
all impacted by manufacturing issues.
.

Silicon
 Silicon Basics
• Name: silicon
• Symbol: Si
• Atomic number: 14
• Atomic weight: 28.0855
• Standard state: solid at 298 K
• Melts at 1410 degrees Celsius
• Colour: dark grey with a bluish tinge
• Classi cation: Semi-metallic

• Availability: lumps
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How Do We “Manufacture” Silicon?
 Czochralski Method

• Most common method used in

industry.

• Can produce large diameter

wafers.

• Can grow silicon crystals quickly.

• Operates at 1425°C.
So Where Do We Get The
Seed Crystal?
 • Silicon is readily available through the treatment of
silica, SiO2, with pure graphite (as coke) in an
electric furnace

SiO2 + 2C → Si + 2CO
• Under these conditions, silicon carbide, SiC, can
form. However, provided the amount of SiO2 is
kept high, silicon carbide may be eliminated

2SiC + SiO2 → 3Si + 2CO

• Very pure silicon can be made by the reaction

of SiCl4 with hydrogen, followed by “zone
re ning” of the resultant silicon

SiCl4 + 2H2 → Si + 4HCl

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.

 Wafer Manufacturing
Silicon wafers are produced by heating a mixture of silica and carbon in a furnace, creating pure
silicon. A seed is then dipped into the molten silicon and is slowly pulled out. This process
creates a cylindrical boule several feet long, which is ground to an appropriate diameter
(200mm, 300mm, etc). The boule is then sliced into thin wafers for production.
 Boule Views

Typically, silicon boules are 1m long.

Boule being drawn.

Various sizes of boules.

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 Wafers from Boules

The base material for the manufacturing

process comes in the form of a single-
crystalline, lightly doped wafer. Wafers are
obtained by cutting a single crystal boule
into slices.

Silicon boule (sliced).

Polished wafers fromboule.
Silicon boule.
Wafer Polishing
Double-sided Polishing
Upper polishing pad

Wafer
Slurry
Lower polishing pad
 Wafer Size Economics
• Wafer size is the diameter of the wafer used in manufacturing.
• Larger wafers → more die per wafer → cheaper devices
“Etched” Wafer

Laser scribe

Note: Notch and scribe are

made before circuits.
Semiconductor Manufacturing Flow
 Testing and Packaging Steps

Processed wafer (a), probed wafer with defective

circuits inked (b), wafer after sawing (c), a good die
attached to package cavity (d), wires bonded to lead
frame (e), nal IC after sealing, testing, and
stamping (f). (g,h,i) correspond to (d,e,f) for a
plastic package.

from: Hubert Kaeslin, Digital Integrated Circuit Design

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 Wafer-Level Testing
To avoid the costs of packaging defective parts, the prospective
ICs are tested while still being part of the processed wafer. A set
of ultra ne needles, rmly held in place by a probe card, is
lowered onto a wafer until all needles establish electrical contact
to the bonding pads of what eventually is to become an IC.

Stimuli are applied to the inputs and the actual responses from
the outputs are checked against the expected ones.

The operation must not take more than a few seconds for
reasons of cost and is repeated for all circuits on a wafer. The
outcome is kept on record electronically. Traditionally, defective
circuits were marked by a droplet of ink.

from: Hubert Kaeslin, Digital Integrated Circuit Design

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 Wafer Maps

Wafer bin maps represent defect patterns on

wafers.
Experienced engineers can sometimes
determine the root cause of failures just by
eyeballing the defect distribution.
Otherwise, statistical analysis techniques are
used to determine likely causes of failure.

from: Clustering Ensemble for Identifying Defective Wafer Bin Map in Semiconductor Manufacturing, Mathematical Problems in Engineering 2015(3):1-11 · July 2015
Dicing
Back-End Assembly and Test
Example of Wirebonding
K&S Ball Bonder

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K&S Ball Bonder

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K&S Ball Bonder

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