IC Fabricating

Trends of Semiconductor Technology for Total System Solutions

• Recent progress in electronics technology has been remarkable.
•

Higher performance and smaller size

Progress in electronics overall has been supported by semiconductor
technology with the information equipment field, as typified by
multimedia, but one leading example.

• The semiconductor technology that makes implementation of a system

on chip possible has contributed both to higher levels of system
performance and also to the creation of new product concepts.

• To respond to user requirements for future higher-level performance

and faster development speed, finer-pattern processing
technology and advanced semiconductor device technology are of
course needed.

• Moreover proposals for total system solutions are needed including

higher-performance microprocessors and application technology such
as middleware; also system SSI, MSI, LSI, VLSI, ULSI technology
and package technology. Year
• For example, in the early 1970s personal computer performance was Fig. 1—Semiconductor Technology Supports Systems
only 0.1 million instructions per second (MIPS), but recently it has Solutions. LSI processing performance has improved
remarkably as higher integration and device performance
exceeded 100 MIPS, for an improvement of more than enabled by semiconductor technology paves the way to multiple
4 orders of magnitude. functional modules on a chip. This not only contributes to
improved performance of system products but also extends to
the creation of new concept products.
 AGC : automatic gain control
ADC : anlog-to-digital converter
PRML : partial response maximum

• High-speed performance and low power consumption have been realized

by implementing on a single chip analog circuits, analog-to-digital (A-D) HDD PRML read-channel LSI
conversion circuits, and a Viterbi decoder — which performs digital filter
processing. Hitachi, Ltd. Used 0.4-µm process complementary metal-
oxide semiconductor (CMOS) technology to fabricate a read-channel LSI
with a top world-level transfer rate of 240 Mbit/s and a power
consumption of only 1 W)

Fig. 2—HDD Read Channel Trend. High-speed

operation has been implemented by integrating analog
circuits, A-D converter circuits, and Viterbi decoder
circuits on a single chip.
 RISC: reduced instruction set computer
* 1 Strong Arm and Alpha are trademarks of
Digital Equipment Corp. of the U.S.
* 2 Power PC 603 is a trademark in the U.S. of International Business
Machines Corp. of the U.S.
* 3 Pentium and Pentium Pro are trademarks of Intel Corp. of the U.S

Fig. New-Generation Microprocessors Featuring

Improved Processing Performance at Low Power
Consumption. New-generation processors have
emerged featuring excellent processing
performance at low power consumption and
small size in response to system-on-chip
requirements
Fig. —Improvement in the
Saturation Current of CMOS
Devices (nMOS Transistors).
Even at low current and voltage,
improvement in the MOS transistor
saturation current that determines
the speed of CMOS logic circuits
increases current drawn.
VLSI Design Flow
The VLSI IC circuits design flow is shown in the figure below. The various levels of design are numbered and the blocks show
processes in the design flow.
Specifications comes first, they describe abstractly, the functionality, interface, and the architecture of the digital IC circuit to be
designed.
Y Chart
• The Gajski-Kuhn Y-chart is a model, which captures the considerations in designing semiconductor devices.
• The three domains of the Gajski-Kuhn Y-chart are on radial axes. Each of the domains can be divided into levels of abstraction, using
concentric rings.
• At the top level (outer ring), we consider the architecture of the chip; at the lower levels (inner rings), we successively refine the design
into finer detailed implementation −
• Creating a structural description from a behavioral one is achieved through the processes of high-level synthesis or logical synthesis.
• Creating a physical description from a structural one is achieved through layout synthesis.
Frontend flow Backend flow
Early Intel microprocessors had the following power rating:
Depending on the right polarities, the blue PMOS transistor will be closed if there is a gate
voltage - the output then is zero. For gate voltage zero, the green NMOS transistor will be
closed, the PMOS transistor is open - the output will be VDD (the universal abbreviation for
the supply voltage).

If we have a p-type substrate, we will have to make a n-well.

The n-well then will contain the PMOS transistors, the original
substrate the NMOS transistors. The whole thing looks
something like this:
The 64 Mbit DRAM, in contrast, is very flat. A big break-through in wafer
processing around 1990 called "Chemical mechanical Polishing" or CMP allowed
to planarize wavy surfaces.

Lets get some idea about the state of the art in (CMOS) chip making in
the beginning of the year 2000. Above you can look at cross-sectional
pictures of a 16 Mbit and a 64 Mbit memory; the cheap chip and the
present work horse in memory chips. The following data which come
from my own experience are not extremely precise but give a good
impression of what you can buy for a few Dollars.
That's it. Those are holy numbers which must not be doubted. Since they are from 1993, the predictive power can be checked.
 Semiconductor Manufacturing Processes

• Design
• Wafer preparation
• Front-end processes
• Photolithography
• Etching
• Cleaning
• Thin Films
• Ion Implantation
• Planarization
• Test and Assembly
FABRICATION PROCESS
Oxidation
The process of oxidation consists of growing a thin film of silicon dioxide on the surface of the silicon wafer.

Diffusion
This process consists of the introduction of a few tenths to several micrometers of impurities by the solid-state diffusion of
dopants into selected regions of a wafer to form junctions.

Ion Implantation
This is a process of introducing dopants into selected areas of the surface of the wafer by bombarding the surface with high-
energy ions of the particular dopant.

Photolithography
In this process, the image on the reticle is transferred to the surface of the wafer.

Epitaxy
Epitaxy is the process of the controlled growth of a crystalline doped layer of silicon on a single crystal substrate.

Metallization and interconnections

After all semiconductor fabrication steps of a device or of an integrated circuit are completed, it becomes necessary to
provide metallic interconnections for the integrated circuit and for external connections to both the device and to the IC.
Semiconductor Cleanroom Design: Meet Air Quality Standards

Semiconductor cleanrooms are enclosed environments located within semiconductor foundries or fabs, that have tight control over
the following:
o Temperature
o Humidity
o Airflow
o Temperature change over time
o Noise
o Vibration
o Lighting
o Airborne particles
Knowing this, facilities lean towards a higher classification to reduce risk of production issues and product failure. One of the main
sources of contamination is human workers inside the semiconductor fab. Workers can create unwanted ESD (electrostatic discharge)
that can destroy delicate electronic circuits. Other potential contamination occurrences are:
•    Glitch in power
•    Fan motor breaking
•    Pressure malfunction
•   Dropping equipment, tools, and parts
•   Wafer handling equipment can malfunction

A proper cleanroom design must have a well designed HVAC system that focuses on temperature, humidity, filtration, and the attributes
noted above to treat and circulate air within acceptable limits. Each machine may have individual exhaust systems for removing
contaminated air and particulates. Every cleanroom must be able to control particulate matter, static, outgassing, and equipment failure,
which can lead to contamination events. These failures can include power glitches, pressure malfunctions, fan motor failure, and wafer
handling machine breakdowns.
 Controlling Temperature, Humidity, And Airflow
Semiconductors have an inverse relationship between temperature coefficient and resistance. When heated, semiconductor conductance increases and
resistance decreases. The outermost electrons separate from the material compound’s atomic nucleus. As free electrons multiply, resistance drops
accordingly. When manufacturing semiconductors, it is vital to keep temperatures within a certain range so the finished chips perform properly in their
application.

Custom Environmental Control Solutions For Semiconductors

Air Innovations’ custom environmental control units (ECUs) provide precise temperature and humidity tolerances to meet even the most
exacting requirements. Minor temperature differences in the environment during semiconductor scanning can result in false readings. Our
semiconductor ECUs control for temperature variations within 0.02 °C, resulting in more accurate readings. Other tolerances include the
following:
 Airflow: up to 4000 CFM
 Humidity: ± 0.5% relative humidity
 Setpoint temperature: 19 °C – 23 °C
 Temperature change: max of 1°C/5 minutes
 Humidity change: max of 1% relative humidity/3 minutes
IC Manufacturing
Schematic Diagram of IC process
 Czochralski Crystal Growth Process
We start growing a "Czochralski crystal" by filling a suitable crucible with
the material - here hyperpure correctly doped Si pieces obtained by crushing
the poly-Si from the Siemens process. Take care to keep impurities out - do
it in a clean room - and use hyperpure silica for your crucible.
 Make sure that the inside of the machine is very clean too and that the
gas flow - the gas you introduce but also the SiO coming from the molten
Si because parts of the crucible dissolve - does not interfere with the
growing crystal.
 Dissolve the Si in the crucible and keep its temperature close to the
melting point. Since you cannot avoid temperature gradients in the
crucible, there will be some convection in the liquid Si. You may want to
suppress this by big magnetic fields.
 Insert your seed crystal, adjust the temperature to "just right", and start
withdrawing the seed crystal. For homogeneity, rotate the seed crystal
and the crucible. Rotation directions and speeds and their development
during growth, are closely guarded secrets!
 First pull rather fast - the diameter of the growing crystal will decrease to
a few mm. This is the "Dash process" ensuring that the crystal will be
dislocation free even though the seed crystal may contain dislocations.
 Now decrease the growth rate - the crystal diameter will increase - until
you have the desired diameter and commence to grow the commercial
part of your crystal at a few mm/second.
As per crystal grows, the impurity concentration (including the dopants
if you do not watch out) will increase in the melt (due to segregation)
and therefore also the percentage incorporated into the crystal. The
temperature profile of the whole system will also change - you are now
deeper down in the crucible and the crystal cools off a little more
slowly. All these factor influence the homogeneity of the crystal.
• The radial and lateral doping level is influenced - it will not stay
constant without some special measures
• The concentration of impurities, especially interstitial oxygen, may
change. In general, the concentration increases from "head" to "tail".
• Crystal lattice defects still present (essentially agglomerates of the
point defects present in thermal equilibrium at high temperatures)
may change in size and distribution.
• You do not want this - you want a crystal where all this factors are
constant - everywhere!
• So you must do something - change the rotation speeds, the
temperature, the growth speed - whatever. This is where crystal
growing becomes an art - and you will not find much literature about
this.
• This is the tricky and secret part: Changing all important parameters
continuously so that the crystal is homogeneous!
Now the crystal is nearly finished. You do not want to use up all the
Si, because the "last drop" contains all the impurities not yet
incorporated because of their small segregation coefficients.
• But you cannot simply pull out the crystal after the desired
length has been reached. The thermal shock of the rapidly
cooling end would introduce large temperature gradients in the
crystal which in turn produce stress gradient - plastic
deformation (easy in Si at high temperatures) will take place and
this means dislocation are nucleated and driven into the crystal.
• The dislocation will even run up into the formerly dislocation
free part of the crystal, destroying your precious Silicon.
• So you withdraw gradually by just increasing the pulling rate a
little bit which will lead to a reduced diameter. The crystal then
ends in an "end cone" similar to the "seed cone"
 The most important technical application of the Cz method is the growth of
dislocation – free silicon crystals with diameters up to 300 mm and a
weight up to 300 kg in industrial production (see Figure 3). Silicon crystals
with diameters of 450 mm and a weight exceeding 300 kg were already
demonstrated. Also several technically important oxide and fluoride
crystals like garnets, niobates, tantalates, silicates, vanadates, aluminates, 
germanates are grown by the Cz method.

1. The pure material which is to be grown in the form of single crystal is

taken in the crucible.
2. The material is heated above the melting point using induction heater.
3. Thus melt is obtained in the crucible. A small defect free single crystal,
called seed crystal is introduced into the melt.
4. The seed crystal is attached to a rod, which is rotated slowly. 5. The seed
crystal is rotated and gradually pulled out of the melt.

Fig. Silicon crystal with a diameter of 300 mm and a weight

exceeding 250 kg, grown by the Cz method
Advantages
• It produces defect free crystal.
• It produces large single crystal.  It allows convenient chemical composition of crystal.
• The dopant distribution in the crystal will be uniform.

Limitations
• High vapour pressure of the materials can be used.
• Possibility of liquid phase encapsulation occurs during solidification.
• It may produce contamination of melt by the crucible.
Bridgman Techniques
Principle
The selective cooling of the molten material is used to form single crystal by
solidification along a particular direction. It is classified into two types. They are,
 Vertical Bridgman Technique
 Horizontal Bridgman Technique
In both techniques, the melt in a sealed crucible is progressively frozen from one end to other
end.
Description
1. The material to be grown in the form of a single crystal which is taken in a cylindrical
crucible.
2. Crucible is made of platinum and tapered conically with pointed tip at the bottom.
3. The crucible is suspended in the upper furnace until the material in the crucible in
completely melted into molten liquid.
4. Crucible is then slowly lowered from upper furnace into lower furnace with the help
of an electric motor.
5. Temperature of the lower furnace is maintained below the melting point of the
material inside the crucible.
6. Thus, a bulk single pure crystal can be grown in the crucible by lowering the crucible
at steady rate (1 – 30 mm/hr.)
Bridgman growth
The Bridgman technique requires a two-zone furnace, of the type shown in Figure. The left hand zone is maintained at
a temperature of ca. 610 °C, allowing sufficient overpressure of arsenic within the sealed system to prevent arsenic loss
from the gallium arsenide. The right hand side of the furnace contains the polycrystalline GaAs raw material held at a
temperature just above its melting point (ca. 1240 °C). As the furnace moves from left to right, the melt cools and
solidifies. If a seed crystal is placed at the left hand side of the melt (at a point where the temperature gradient is such
that only the end melts), a specific orientation of single crystal may be propagated at the liquid-solid interface
eventually to produce a single crystal.

Fig. A schematic diagram of a Bridgman two-zone furnace used for melt growths of single crystal GaAs
Advantages
 It is relatively cheaper than other pulling techniques.
 Simpler technology
 Melt composition can be controlled during the growth.
 It enables easy stabilization of temperature gradient
Disadvantages
 Growth rate is very low.
 Sometimes instead of single crystals, polycrystals may grow.
 Since the material is in contact with the walls of the container for long period, it leads to dislocations of the nucleus.
 This technique can't be used for materials which decompose before melting.
SILICON WAFER PRODUCTION AND SPECIFICATIONS
Silicon Wafer Production From Ingot to Cylinder. The monocrystals grown with the Czochralski or Float-zone
technique are ground to the desired diameter and cut into shorter workable cylinders with e.g. a band saw and ground
to a certain diameter

Fig. Grinding, sawing, etching and polished (from left to right)

Flats are the work steps from an ingot to a finished wafer
An orientation flat is added to indicate the crystal orientation (Fig.), while wafers with an 8 inch diameter and above use a
single notch to convey wafer orientation, independent from the doping type. Two common techniques are applied for wafer
dicing: Inside hole saw and wire saw, both explained in the following sections.

Diameter: The normal width across the wafer or diameter of the

Fig. : The usual ("SEMI-standard") arrangement of the
flats with wafers in dependency on crystal orientation
and doping
silicon wafer not in the region of the flats or other marks. Typical and
standard silicon wafer diameters are: 25.4mm (1”), 50.4mm (2”),
76.2mm (3”), 100mm, 125mm, 150mm, 200mm, 300mm.
Thickness: The normal distance through a slice or wafer in a direction
normal to the surface at a given point.
Crystal Planes
Planes are the second level or organization in crystal structure. They describe the orientation of the crystal, which is
dependent on the orientation of the individual unit cells within the crystal. Each type of plane is unique, differing in atom
count and binding energies and therefore in chemical, electrical and physical properties. The Miller Index helps us to
identify crystal planes.
The Miller Index
The Miller index is a roadmap or compass for identifying the crystal planes of crystals.
Miller indices are three digit notations that indicate planes and direction within a
crystal. These notations are based on the Cartesian coordinate system of x, y, and z. The
Cartesian coordinate system is illustrated using the three vectors (axes) x, y, and z.

Referring to the graphic “Cartesian Coordinates”, the • x-axis vector is denoted [1,0,0]
• y-axis vector is denoted [0,1,0] • z-axis vector is denoted [0,0,1] (Think of the "1" as
being "1 unit" out from the origin or 0,0,0.)
Alternate vectors are indicated with <>, such as , <100 >, <010 >, , or .

Each plane in a crystal structure has a unique notation and the notation depends on the
plane’s orientation. • (1,0,0) or (100) is perpendicular to the x-axis • (0,1,0) or (010) is
perpendicular to the y-axis • (0,0,1) or (001) is perpendicular to the z-axis The above
graphic illustrates a unit cell relative to the x-y-z axes and the yellow plane denoted (100).
Alternate planes are denoted using {}, such as {100}, {010} and {111}.
Orientation:
The growth plane of the crystalline silicon. Orientations are described using Miller Indices such as (100), (111), (110),
(211), etc. Different growth planes and orientations have different arrangements of the atoms or lattice as viewed from a
particular angle.
Slice Orientation:
The crystallographic orientation of the surface of a wafer. The primary and most common slice orientations are (100), (111)
and (110).
Primary Flat: The flat of longest length appearing in the circumference of the wafer. The primary flat has a specific
crystallographic orientation relative to the wafer surface.
Secondary Flat: The flat of shortest length appearing in the circumference of the wafer. The primary flat has a specific
crystallographic orientation relative to the wafer surface and the primary flat.
Bow: Concavity, curvature, or deformation of the wafer centreline independent of any thickness variation present. Warp:
Deviation from a plane of a slice or wafer centreline containing both concave and convex regions.
Haze Free: A silicon wafer having the best possible surface finish and micro-roughness on the order of less than 10A. Prime
Grade: The highest grade of a silicon wafer. SEMI indicates the bulk, surface, and physical properties required to label
silicon wafers as “Prime Wafers”.
Test Grade: A virgin silicon wafer of lower quality than Prime, and used primarily for testing processes. SEMI indicates the
bulk, surface, and physical properties required to label silicon wafers as “Test Wafers”.
Silicon wafers are available in a variety of diameters from 25.4 mm (1 inch) to 300 mm (11.8 inches).Semiconductor
fabrication plants, colloquially known as fabs, are defined by the diameter of wafers that they are tooled to produce. The
diameter has gradually increased to improve throughput and reduce cost with the current state-of-the-art fab using 300 mm,
with a proposal to adopt 450 mm. Intel, TSMC and Samsung were separately conducting research to the advent of 450
mm "prototype" (research) fabs, though serious hurdles remain
Inside Hole Saw (Annular Saw)
The wafers are sawed inside a circular blade whose cutting edge is filled with diamond splinters (Fig.). After sawing, the
wafer surfaces are already relatively flat and smooth, so the subsequent lapping of the surfaces takes less time and effort.
However, only one wafer per annular saw can be cut at the same time, so this technique has a comparably low throughput
which makes the wafers more expensive compared to wafers cut by a wire saw.

Fig: Diagram of an inside hole saw with

the centrally mounted silicon ingot
 Wire Saw
In order to increase throughput, wire saws with many parallel wires are used which cut many wafers at once (Fig. 18).
A long (up to 100 km) high-grade steel wire with a diameter of e 100 - 200 μm is wrapped around rotating rollers with
hundreds of equidistant grooves at a speed of typically 10 m/s. The mounted silicon cylinder is drained into the wire
grid and thus cut into single wafers.

Fig: Diagram of the

wire saw process. The
two detailed
enlargements above
show the proportions
between the Si-
cylinder, wire spacing
and wire diameter
approximately to scale.

The wire is either coated with diamond splinters or wetted

with a suspension of abrasive particles such as diamonds
or silicon carbide grains, and a carrier (glycol or oil). The
main advantage of this sawing method is that hundreds of
wafers can be cut at a time with one wire. However, the
attained wafer surface is less smooth and more bumpy as
compared to wafers cut by an annular saw, so the
subsequent wafer lapping takes more time.
Lapping
After dicing, the wafers are lapped on both sides in order to i) remove the surface silicon which has been cracked or
otherwise damaged by the slicing process (e.g. grooves by the wire saw) and ii) thinned to the desired wafer thickness.
Several wafers at a time are lapped in between two counter-rotating pads by a slurry consisting of e.g. Al 2O3 or SiC abrasive
grains with a defined size distribution

Etching
Wafer dicing and lapping degrade the silicon surface crystal structure, so subsequently the wafers are etched in either
KOH- or HNO3 /HF based etchants in order to remove the damaged surface.

Polishing
After etching, both wafer surfaces appear like the rear side of finished single-side polished wafer. In order to attain the
super-flat, mirrored surface with a remaining roughness on atomic scale, the wafers have to be polished. Wafer polishing
is a multi-step process using an ultra-fine slurry with 10 - 100 nm sized grains consisting of e.g. Al2O3 , SiO2 or CeO2
which, combined with pressure, erode and mechanically and chemically smoothen the wafer surface between two
rotating pads.
Cleaning
Finally, the wafers are cleaned with ultra-pure chemicals in order to remove the polishing agents thereby making them
residual-free and guaranteeing the particle specification.
Fig: Diagram of a grinder (In principle also a polishing machine) for the wafer. The
opposing and superimposed rotation ensures uniform material removal from the
wafer surface without preference for one particular direction.
Silicon Wafer Specifications
Diameter
The diameter of the silicon wafers are specified either in inches or mm. Although an inch is 25.4 mm, the diameters of
wafers in inches are usually multiples of 25.0 mm (e.g. 4 inches = 100 mm), which should be clarified beforehand
with the supplier. The tolerance of the diameter is typically +/- 0.5 mm.

Orientation
The wafer orientation (e.g. , or ) denotes the crystallographic plane parallel to the wafer surface. For certain
applications, a defined tilting to the main crystallographic plane may be desirable, but usually an attempt is made to
orient the wafer surface as precisely as possible to the main crystal plane; corresponding tolerances are generally +/-
0.5°.

Surfaces
Usually both sides of silicon wafers are at least lapped and etched. Surface polishing is performed either on one (SSP =
Single-Side Polished) or both sides, DSP = Double-Side Polished). The roughness of the polished side(s) is
approximately 1 nm (0.5 nm is technically feasible), of the unpolished side in the range of several µm.

Doping and Resistivity

The dopant atoms incorporated during silicon crystal growth increase the electrical conductivity via an increase in the
free electron (in the case of phosphor or arsenic dopants) or hole (boron as dopant) concentration by up to many orders
of magnitude beyond the value of undoped silicon
Thickness
The usual thickness of Si wafers is dependent on their diameter due to reasons of mechanical stability during production
and further processing, and is about 280 μm (for wafers with 2 inch diameter), 380 μm (3 inch), 525 μm (4 inch), 675 μm
(6 inch) and 725 μm (8 inch).
Within the context of conventional production methods, the wafer thickness is limited upwards to approx. 2 mm, since the
polishing machines cannot accommodate thicker wafers. A limitation of the wafer thickness downwards to approx. 200 μm
as given by many manufacturers, is due to the risk of fracture during grinding and polishing. The thickness tolerance
corresponds to the variation of the thickness measured in the wafer centre of a batch. Usually this parameter is specified
with +/-25 µm independent of the wafer diameter, the measured values are often at approx. +/-15 µm.

This distribution does not, however, tell us how much a wafer deviates from the ideal cylindrical shape. With the
assistance of the planes and surfaces defined in Fig.

Fig: In addition to the thickness

inhomogeneity of a wafer (grey form), a
wafer is "warped" in itself in various ways,
which can be represented by so-called
median surfaces (blue), which ignore the
thickness inhomogeneity. The deviation of
the median surface of a wafer to the planar
reference surface (green) defines the
parameters of bow and warp.
Types of Etch
• Wet etch
• Physical dry etch
• Chemical dry etch
• Chemical + Physical
 Unit -II
Deposition
Deposition refers to a series of processes where materials at atomic or molecular levels are deposited on the wafer surface as a
thin layer to contain electrical properties.

Deposition is a process that deposits a blanket of materials on a surface. There are multiple ways to do this, including selective
deposition, atomic-layer deposition, chemical vapor deposition and physical vapor deposition.

Which technique is used depends upon the process node, the type of chip, and the amount of time needed to do the deposition.

The deposition methods can be largely divided into physical vapor deposition (PVD) and chemical vapor deposition (CVD).
 
Physical vapor deposition (PVD) is mainly used for depositing thin metal films and does not involve chemical reactions.

Chemical vapor deposition (CVD) occurs as particles from the chemical reaction of gas are deposited in the form of vapor
activated by an external energy source. CVD can be used on conductors and nonconductors, as well as semiconductors.
 Schematic Diagram of IC process
• In order to obtain thin films with good quality, there are two common deposition techniques: physical and chemical
depositions. It can be summarized as shown in Table.

Physical deposition Chemical deposition

1. Evaporation techniques 1. Sol-gel technique
a. Vacuum thermal evaporation. 2. Chemical bath deposition
b. Electron beam evaporation. 3. Spray pyrolysis technique
c. Laser beam evaporation. 4. Plating
d. Arc evaporation. a. Electroplating technique.
e. Molecular beam epitaxy. b. Electroless deposition.
f. Ion plating evaporation.

2. Sputtering techniques 5. Chemical vapor deposition (CVD)

a. Direct current sputtering (DC sputtering). a. Low pressure (LPCVD)
b. Radio frequency sputtering (RF sputtering). b. Plasma enhanced (PECVD)
c. Atomic layer deposition (ALD)
 Deposition: Air-brushing with chemicals

For this reason, CVD is more commonly used in today’s semiconductor manufacturing processes. The CVD method is
further broken down into thermal, plasma-enhanced and optical CVD depending on the source of external energy
used. Plasma-enhanced CVD, in particular, yields many benefits as it can be processed at lower temperatures in large
volumes while offering greater control over thickness uniformity, making it a preferred method of choice these days.
 
The thin film fabricated through the deposition process can be categorized into metal (conducting) layers for electrical
connections between circuits, and dielectric (insulating) layers that electrically isolate the internal layers or protect them
from contaminants.
 What is PVD?
PVD is physical vapour deposition. It is mainly a vaporisation coating technique. This process involves several steps.
However, we do the whole process under vacuum conditions. Firstly, the solid precursor material is bombarded with a
beam of electrons, so that it will give atoms of that material.

Secondly, these atoms then enter the reacting chamber where the coating
substrate exists. There, while transporting, the atoms can react with other
gases to produce a coating material or the atoms themselves can become
the coating material. Finally, they deposit on the substrate making a thin
coat. PVD coating is useful in reducing friction, or to
improve oxidation resistance of a substance or to improve the hardness,
etc.

Fig: PVD Apparatus

What is CVD?

CVD is chemical vapour deposition. It is a method to deposit solid and form a thin film from gaseous phase material.
Even though this method is somewhat similar to PVD, there is some difference between PVD and CVD. Moreover, there
are different types of CVD such as laser CVD, photochemical CVD, low-pressure CVD, metal organic CVD, etc.
In CVD, we are coating material on a substrate material. To do this coating, we need to send the coating material into a
reaction chamber in the form of vapour at a certain temperature. There, the gas reacts with the substrate, or it decomposes
and deposits on the substrate. Therefore, in a CVD apparatus, we need to have a gas delivery system, reacting chamber,
substrate loading mechanism and an energy supplier.
Furthermore, the reaction occurs in a vacuum to ensure that there are no gases other than the reacting gas. More importantly,
the substrate temperature is critical for determining the deposition; thus, we need a way to control the temperature and
pressure inside the apparatus.
Finally, the apparatus should have a way to
remove the excess gaseous waste out. We
need to choose a volatile coating material.
Similarly, it has to be stable; then we can
convert it into the gaseous phase and then
coat onto the substrate. Hydrides like SiH4,
GeH4, NH3, halides, metal carbonyls, metal
alkyls, and metal alkoxides are some of the
precursors. CVD technique is useful in
producing coatings, semiconductors,
composites, nanomachines, optical fibres,
catalysts, etc. Fig: A Plasma Assisted CVD Apparatus
 Physical deposition techniques
1. Evaporation techniques
Evaporation methods are considered as the common deposition of materials in the form of thin-layer films. The general
mechanism of these methods is obtained by changing the phase of the material from solid phase to vapor phase and converting
again to solid phase on the specific substrate. It takes place under vacuum or controlled atmospheric condition.

a. Vacuum thermal evaporation technique

Vacuum evaporation technique is the simplest technique used to prepare amorphous thin films especially chalcogenide films
such as CdSSe, MnS, Ge-Te-Ga, and so on. In general, chalcogenide materials can be used for memory-switching
applications, phase-change materials, and solar applications.

The technique of thermal evaporation is strongly dependent on two

parameters: thermally vaporized material and applying a potential difference
to the substrate under medium- or higher-vacuum level ranging from 10 -5 to
10-9 mbar. The schematic diagram for thermal evaporation is shown in Figure
taken from elsewhere.

Figure Schematic of thermal evaporation system with substrate holder on a

planetary rotation system and directly above the evaporating source.
 Electron beam evaporation
This type of evaporation is another method of physical deposition where the intensive beam of electrons is generated from
a filament and steered through both electric and magnetic fields to hit the target and vaporize it under vacuum environment
as shown in Figure. Thin films prepared by electron beam evaporation are of good quality and purity.

Large categories of materials can be prepared by electron beam evaporation

technique such as amorphous and crystalline semiconductors, metals, oxides ,
and molecular materials.

Figure . Schematic diagram of electron beam evaporation.

Laser beam evaporation (pulsed-laser deposition)

Pulsed-laser deposition (PLD) is another physical deposition technique to deposit the thin film-coating system. During the
thin-film deposition process, the laser beam is used to ablate the material for depositing the thin films inside a vacuum
chamber as shown in Figure.

When the laser beam strikes the target material, it produces the
plume which could deposit on the various substrates. The
created plume may contain neural- and ground-state atoms and
ionized species. In the case of metal oxide thin films, oxygen is
used to deposit the oxides of metals. The thin-film quality from
the PLD depends on the various parameters such as wavelength
of the laser, energy, ambient gas pressure, pulsed duration, and
the distance of the target to the substrate.

Figure. Schematic of pulsed-laser deposition.

PLD has some advantages over other physical deposition systems because of its fast deposition time
and its compatibility to oxygen and other inert gases.
 Sputtering technique
Sputtering technique is mostly used for depositing metal and oxide films by
controlling the crystalline structure and surface roughness. The simple form
of the sputtering system consists of an evacuated chamber containing
metallic anode and cathode in order to obtain a glow discharge in the
residual gas in the chamber. Also, an applied voltage in the order of several
KeV with pressure more than 0.01 mbar is sufficient for film deposition. The
sputtering process depends on the bombardment of the ions released from the
discharge to the molecules in the cathode leading to the liberation of the
molecules from the cathode with higher kinetic energy. The atomic weight of
the bombarding ions should be nearly to that of the target material in order to
maximize the momentum transfer. These molecules move in straight lines
and strike on the anode or on the substrate to form a dense thin film. The
diagram of the sputtering system is shown in Figure.
The process of sputtering has several advantages.
• High-melting point materials can be easily formed by sputtering. Figure 4. Sputtering system diagram.
• The deposited films have composition similar to the composition of the starting materials.
• Sputtering technique is available to use for ultrahigh vacuum applications.
The sputtering sources are compatible with reactive gases such as oxygen.
• Contrarily,’ thick coatings cannot be obtained and there is a difficulty to deposit uniformly on complex shapes

There are two common types of sputtering process: direct current (DC) and radio frequency (RF) sputtering. The first one depends on DC power, which is
generally used with electrically conductive target materials. It is easy to control with low-cost option. The RF sputtering uses RF power for most dielectric
materials. A common example for sputtered films is aluminum nitride films. These films were prepared by both DC- and RF-sputtering technique, and their
structure and optical properties were compared.