Time Allowed: 1 HR

Mid term Exam 2nd Year Students

Total Marks: 20
Digital Design 2050 - 2051

Solve the following Questions

XY
1/1 0/0
First Question:
0/1 1/0
(a) Design the sequential circuit for the state diagram 11 00
shown in the figure, use J-K flip flops.
0/0 10 1/0
1/0
(b) Design a counter with the following sequence 0/0
2, 3, 5, 6, 7 (using T- flip flop).
01
(c) Draw (ONLY ) the following circuits:
 4-bit up-down Synchronous counter.
 4-bit register with load control.
 3-bit shift left register.
 Ripple counter that counts from 15 to 0 at +ve edge.
(14 marks)

Second Question:

The following circuit represents a 4 bit ripple counter which counts from 0 to 9, (count
sequence is 0,1,2,3,4,5,6,7,8,9), is this counter self starting or not?

A B C D

Q j Q j 1 Q j Q j 1
CP
Q k 1 k 1 k 1 k 1

(6 marks)

With Best Wishes